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riscv: Implement ReverseBits in jit.

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Unknown W. Brackets 2023-08-06 21:33:00 -07:00
parent ad4cbbab8e
commit 0b4e7d60f9
1 changed files with 35 additions and 1 deletions
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36
Core/MIPS/RiscV/RiscVCompALU.cpp
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@ -232,7 +232,41 @@ void RiscVJitBackend::CompIR_Bits(IRInst inst) {
switch (inst.op) {
case IROp::ReverseBits:
CompIR_Generic(inst);
if (cpu_info.RiscV_Zbb) {
gpr.MapDirtyIn(inst.dest, inst.src1);
// Start by reversing bytes (note: this puts in upper 32 of XLEN.)
REV8(gpr.R(inst.dest), gpr.R(inst.src1));
// Swap nibbles.
LI(SCRATCH1, (s32)0xF0F0F0F0);
SRLI(SCRATCH2, gpr.R(inst.dest), XLEN - 32 - 4);
AND(SCRATCH2, SCRATCH2, SCRATCH1);
if (XLEN >= 64)
SRLI(gpr.R(inst.dest), gpr.R(inst.dest), XLEN - 28);
else
SLLI(gpr.R(inst.dest), gpr.R(inst.dest), 4);
SRLIW(SCRATCH1, SCRATCH1, 4);
AND(gpr.R(inst.dest), gpr.R(inst.dest), SCRATCH1);
OR(gpr.R(inst.dest), gpr.R(inst.dest), SCRATCH2);
// Now the consecutive pairs.
LI(SCRATCH1, (s32)0x33333333);
SRLI(SCRATCH2, gpr.R(inst.dest), 2);
AND(SCRATCH2, SCRATCH2, SCRATCH1);
AND(gpr.R(inst.dest), gpr.R(inst.dest), SCRATCH1);
SLLIW(gpr.R(inst.dest), gpr.R(inst.dest), 2);
OR(gpr.R(inst.dest), gpr.R(inst.dest), SCRATCH2);
// And finally the even and odd bits.
LI(SCRATCH1, (s32)0x55555555);
SRLI(SCRATCH2, gpr.R(inst.dest), 1);
AND(SCRATCH2, SCRATCH2, SCRATCH1);
AND(gpr.R(inst.dest), gpr.R(inst.dest), SCRATCH1);
SLLIW(gpr.R(inst.dest), gpr.R(inst.dest), 1);
OR(gpr.R(inst.dest), gpr.R(inst.dest), SCRATCH2);
} else {
CompIR_Generic(inst);
}
break;
case IROp::BSwap16: