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This commit is contained in:
Henrik Rydgard 2013-07-31 11:25:35 +02:00
parent 9bf8bfbed4
commit 3303a71796
2 changed files with 5 additions and 1 deletions
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4
Core/MIPS/ARM/ArmCompVFPU.cpp
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@ -185,10 +185,12 @@ namespace MIPSComp
MOVI2F(S0, 0.0f, R0);
MOVI2F(S1, 1.0f, R0);
VCMP(fpr.V(vregs[i]), S0);
VMRS_APSR(); // Move FP flags from FPSCR to APSR (regular flags).
SetCC(CC_LE);
VMOV(fpr.V(vregs[i]), S0);
SetCC(CC_AL);
VCMP(fpr.V(vregs[i]), S1);
VMRS_APSR(); // Move FP flags from FPSCR to APSR (regular flags).
SetCC(CC_GT);
VMOV(fpr.V(vregs[i]), S1);
SetCC(CC_AL);
@ -205,10 +207,12 @@ namespace MIPSComp
MOVI2F(S0, -1.0f, R0);
MOVI2F(S1, 1.0f, R0);
VCMP(fpr.V(vregs[i]), S0);
VMRS_APSR(); // Move FP flags from FPSCR to APSR (regular flags).
SetCC(CC_LT);
VMOV(fpr.V(vregs[i]), S0);
SetCC(CC_AL);
VCMP(fpr.V(vregs[i]), S1);
VMRS_APSR(); // Move FP flags from FPSCR to APSR (regular flags).
SetCC(CC_GT);
VMOV(fpr.V(vregs[i]), S1);
SetCC(CC_AL);

2
Core/MIPS/ARM/ArmRegCacheFPU.cpp
View File

@ -370,7 +370,7 @@ void ArmRegCacheFPU::ReleaseSpillLocksAndDiscardTemps() {
DiscardR(i);
}
ARMReg ArmRegCacheFPU::R(int mi psReg) {
ARMReg ArmRegCacheFPU::R(int mipsReg) {
if (mr[mipsReg].loc == ML_ARMREG) {
return (ARMReg)(mr[mipsReg].reg + S0);
} else {