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https://github.com/hrydgard/ppsspp.git
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Quick hacked-up ARM VFP disassembler. Buggy.
This commit is contained in:
Henrik Rydgard
parent
7e373c206d
commit
65f8430c32
@ -920,14 +920,8 @@ void ARMXEmitter::VSUB(IntegerSize Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
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| ((Vm & 0x10) << 2) | (Vm & 0xF));
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}
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// VFP Specific
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struct VFPEnc
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{
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s16 opc1;
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s16 opc2;
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};
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// Double/single, Neon
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const VFPEnc VFPOps[][2] = {
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extern const VFPEnc VFPOps[16][2] = {
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{{0xE0, 0xA0}, {0x20, 0xD1}}, // 0: VMLA
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{{0xE1, 0xA4}, { -1, -1}}, // 1: VNMLA
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{{0xE0, 0xA4}, {0x22, 0xD1}}, // 2: VMLS
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@ -944,7 +938,8 @@ const VFPEnc VFPOps[][2] = {
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{{0xEB, 0xAC}, { -1, -1}}, // 13: VCMPE (Vn(0x4 | #0 ? 1 : 0) used for encoding)
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{{ -1, -1}, {0x3B, 0x30}}, // 14: VABSi
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};
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const char *VFPOpNames[] = {
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extern const char *VFPOpNames[16] = {
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"VMLA",
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"VNMLA",
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"VMLS",
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@ -656,6 +656,14 @@ public:
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}
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};
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// VFP Specific
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struct VFPEnc {
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s16 opc1;
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s16 opc2;
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};
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extern const VFPEnc VFPOps[16][2];
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extern const char *VFPOpNames[16];
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} // namespace
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#endif // _DOLPHIN_INTEL_CODEGEN_
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325
ext/disarm.cpp
325
ext/disarm.cpp
@ -63,6 +63,194 @@
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include "base/basictypes.h"
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#include "Common/ArmEmitter.h"
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static const char *CCFlagsStr[] = {
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"EQ", // Equal
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"NEQ", // Not equal
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"CS", // Carry Set
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"CC", // Carry Clear
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"MI", // Minus (Negative)
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"PL", // Plus
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"VS", // Overflow
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"VC", // No Overflow
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"HI", // Unsigned higher
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"LS", // Unsigned lower or same
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"GE", // Signed greater than or equal
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"LT", // Signed less than
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"GT", // Signed greater than
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"LE", // Signed less than or equal
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"", // Always (unconditional) 14
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};
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int GetVd(uint32_t op, bool quad = false, bool dbl = false) {
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if (!quad && !dbl) {
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return ((op >> 22) & 1) | ((op >> 11) & 0x1E);
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}
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return 0;
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}
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int GetVn(uint32_t op, bool quad = false, bool dbl = false) {
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if (!quad && !dbl) {
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return ((op >> 7) & 1) | ((op >> 15) & 0x1E);
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} else if (dbl) {
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return ((op >> 16) & 0xF) | ((op >> 3) & 0x10);
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}
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return 0;
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}
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int GetVm(uint32_t op, bool quad = false, bool dbl = false) {
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if (!quad && !dbl) {
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return ((op >> 5) & 1) | ((op << 1) & 0x1E);
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}
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return 0;
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}
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// Modern VFP disassembler, written entirely separately because I can't figure out the old stuff :P
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// Horrible array of hacks but hey. Can be cleaned up later.
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bool DisasmVFP(uint32_t op, char *text) {
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const char *cond = CCFlagsStr[op >> 28];
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switch ((op >> 24) & 0xF) {
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case 0xD:
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// VLDR/VSTR
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{
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int base = (op >> 16) & 0xF;
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bool add = (op >> 23) & 1;
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int freg = ((op >> 11) & 0x1E) | ((op >> 22) & 1);
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int offset = (op & 0xFF) << 2;
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if (!add) offset = -offset;
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bool vldr = (op >> 20) & 1;
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bool single_reg = ((op >> 8) & 0xF) == 10;
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sprintf(text, "%s%s s%i, [r%i, #%i]", vldr ? "VLDR" : "VSTR", cond, freg, base, offset);
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return true;
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}
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case 0xE:
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{
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switch ((op >> 20) & 0xF) {
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case 0xE: // VMSR
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if ((op & 0xFFF) != 0xA10)
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break;
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sprintf(text, "VMSR%s r%i", cond, (op >> 12) & 0xF);
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return true;
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case 0xF: // VMRS
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if ((op & 0xFFF) != 0xA10)
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break;
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if (op == 0xEEF1FA10) {
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sprintf(text, "VMRS APSR", cond);
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} else {
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sprintf(text, "VMRS%s r%i", cond, (op >> 12) & 0xF);
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}
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return true;
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default:
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break;
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}
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if (((op >> 19) & 0x7) == 0x7) {
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// VCVT
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sprintf(text, "VCVT ...");
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return true;
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}
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int part1 = ((op >> 23) & 0x1F);
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int part2 = ((op >> 9) & 0x7) ;
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int part3 = ((op >> 20) & 0x3) ;
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if (part3 == 3 && part2 == 5 && part1 == 0x1D && (op & (1<<6))) {
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// VMOV
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int vn = GetVn(op);
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if (vn != 1 && vn != 3) {
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int vm = GetVm(op);
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int vd = GetVd(op);
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sprintf(text, "VMOV%s s%i, s%i", cond, vd, vm);
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return true;
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}
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}
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// Arithmetic (buggy!)
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bool quad_reg = (op >> 6) & 1;
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bool double_reg = (op >> 8) & 1;
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int opnum = -1;
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int opc1 = (op >> 20) & 0xFB;
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int opc2 = (op >> 4) & 0xAC;
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for (int i = 0; i < 16; i++) {
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if (ArmGen::VFPOps[i][0].opc1 == opc1 && ArmGen::VFPOps[i][0].opc2 == opc2) {
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opnum = i;
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break;
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}
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}
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if (opnum < 0)
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return false;
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switch (opnum) {
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case 8:
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case 10:
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case 11:
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case 12:
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case 13:
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case 14:
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{
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quad_reg = false;
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int vd = GetVd(op, quad_reg, double_reg);
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int vn = GetVn(op, quad_reg, true);
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int vm = GetVm(op, quad_reg, double_reg);
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if (opnum == 8 && vn == 0x11) opnum += 3;
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sprintf(text, "%s%s s%i, s%i", ArmGen::VFPOpNames[opnum], cond, vd, vm);
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return true;
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}
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default:
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{
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quad_reg = false;
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int vd = GetVd(op, quad_reg, double_reg);
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int vn = GetVn(op, quad_reg, double_reg);
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int vm = GetVm(op, quad_reg, double_reg);
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sprintf(text, "%s%s s%i, s%i, s%i", ArmGen::VFPOpNames[opnum], cond, vd, vn, vm);
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return true;
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}
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}
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return true;
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}
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break;
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}
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return false;
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}
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typedef unsigned int word;
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typedef unsigned int address;
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@ -489,132 +677,17 @@ lMaybeLDRHetc:
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break;
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case 12:
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case 13:
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/* STC or LDC */
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if (CP_is(1)) {
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/* copro 1: FPU. This is STF or LDF. */
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mnemonic = "STF\0LDF" + ((instr&Lbit) >> 18);
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format = "8,/";
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*flagp++ = "SDEP"[fpn];
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poss_tt = (eTargetType)(target_FloatS+fpn);
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}
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else if (CP_is(2)) {
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/* copro 2: this is LFM or SFM. */
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mnemonic = "SFM\0LFM" + ((instr&Lbit) >> 18);
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if (!fpn) fpn=4;
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if (RN_is(13) && BitsDiffer(23,24)) {
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if ((instr&255)!=fpn) goto lNonStackLFM;
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/* r13 and U!=P, so treat as stack */
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if (BitsDiffer(20,24)) {
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/* L != P, so FD */
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*flagp++ = 'F'; *flagp++ = 'D';
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}
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else {
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/* L == P, so EA */
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*flagp++ = 'E'; *flagp++ = 'A';
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}
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format = "8,(,[4]'";
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}
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else {
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lNonStackLFM:
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/* not r13 or U=P or wrong offset, so don't treat as stack */
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format = "8,(,/";
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poss_tt = target_FloatE;
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}
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}
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else {
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/* some other copro number: STC or LDC. */
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mnemonic = "STC\0LDC" + ((instr&Lbit) >> 18);
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format = ";,\004,/";
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if (instr&(1<<22)) *flagp++ = 'L';
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poss_tt = target_Unknown;
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}
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break;
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case 14:
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/* CDP or MRC/MCR */
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if (instr&(1<<4)) {
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/* MRC/MCR. */
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if (CP_is(1)) {
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/* copro 1: FPU. */
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if ((instr&Lbit) && RD_is(15)) {
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/* MCR in FPU with Rd=r15: comparison (ugh) */
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if (!(instr&(1<<23))) goto lUndefined; /* unused operation */
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mnemonic = "CMF\0\0CNF\0\0CMFE\0CNFE" + (5*(instr&(3<<21)) >> 21);
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format = "9,+";
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if (instr&((1<<19)+(7<<5)))
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result.badbits=1; /* size,rmode reseved */
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}
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else {
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/* normal FPU MCR/MRC */
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word op20 = instr&(15<<20);
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if (op20>=6<<20) goto lUndefined;
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mnemonic = "FLT\0FIX\0WFS\0RFS\0WFC\0RFC" + (op20>>18);
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if (op20==0) {
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/* FLT instruction */
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format = "9,3";
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{ char c = "SDE*"[((instr>>7)&1) + ((instr>>18)&2)];
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if (c=='*') goto lUndefined; else *flagp++=c;
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}
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if (instr&15) result.oddbits=1; /* Fm and const flag unused */
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}
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else {
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/* not FLT instruction */
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if (instr&((1<<7)+(1<<19)))
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result.badbits=1; /* size bits reserved */
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if (op20==1<<20) {
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/* FIX instruction */
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format = "3,+";
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if (opts->flags&disopt_FIXS)
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*flagp++ = "SDEP"[((instr>>7)&1) + ((instr>>18)&2)];
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*flagp++ = "\0PMZ"[(instr&(3<<5))>>5];
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if (instr&(7<<15)) result.oddbits=1; /* Fn unused */
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if (instr&(1<<3)) result.badbits=1; /* no immediate consts */
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}
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else {
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/* neither FLT nor FIX */
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format = "3";
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if (instr&(3<<5)) result.badbits=1; /* rmode reserved */
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if (instr&(15+(7<<15))) result.oddbits=1;/* iFm, Fn unused */
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}
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}
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}
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}
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else {
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/* some other copro number. Not FPU. */
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/* NB that ObjAsm documentation gets MCR and MRC the wrong way round!
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*/
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mnemonic = "MCR\0MRC";
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mnemonic += (instr&Lbit) >> 18;
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format = ";,:,3,\005,\001-";
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}
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}
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else {
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/* CDP. */
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if (CP_is(1)) {
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/* copro 1: FPU. */
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mnemonic = /* dyadics: */
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"ADF\0MUF\0SUF\0RSF\0"
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"DVF\0RDF\0POW\0RPW\0"
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"RMF\0FML\0FDV\0FRD\0"
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"POL\0***\0***\0***\0"
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/* monadics: */
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"MVF\0MNF\0ABS\0RND\0"
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"SQT\0LOG\0LGN\0EXP\0"
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"SIN\0COS\0TAN\0ASN\0"
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"ACS\0ATN\0URD\0NRM\0"
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+ ((instr&(15<<20)) >> 18) /* opcode -> bits 5432 */
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+ ((instr&(1<<15)) >> 9); /* monadicP -> bit 6 */
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format = (instr&(1<<15)) ? "8,+" : "8,9,+";
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*flagp++ = "SDE*"[((instr>>7)&1) + ((instr>>18)&2)];
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*flagp++ = "\0PMZ"[(instr&(3<<5))>>5];
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/* NB that foregoing relies on this being the last flag! */
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if (*mnemonic=='*' || *flagchars=='*') goto lUndefined;
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}
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else {
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/* some other copro number. Not FPU. */
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mnemonic = "CDP";
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format = ";,),\004,\005,\001-";
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}
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}
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case 14: // FPU
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{
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char text[256];
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if (!DisasmVFP(instr, text)) {
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goto lUndefined;
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break;
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}
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strcpy(result.text, text);
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result.undefined = 0;
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return &result;
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}
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break;
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case 15:
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/* SWI */
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@ -37,7 +37,20 @@
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#define EXPECT_TRUE(a) if (!(a)) { printf(__FUNCTION__ ":%i: Test Fail\n", __LINE__); return false; }
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#define EXPECT_FALSE(a) if ((a)) { printf(__FUNCTION__ ":%i: Test Fail\n", __LINE__); return false; }
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#define EXPECT_EQ_FLOAT(a, b) if ((a) != (b)) { printf(__FUNCTION__ ":" __LINE__ ": Test Fail\n%f\nvs\n%f\n", a, b); return false; }
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#define EXPECT_EQ_STR(a, b) if ((a) != (b)) { printf(__FUNCTION__ ": Test Fail\n%s\nvs\n%s\n", a.c_str(), b.c_str()); return false; }
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#define EXPECT_EQ_STR(a, b) if (a != b) { printf(__FUNCTION__ ": Test Fail\n%s\nvs\n%s\n", a.c_str(), b.c_str()); return false; }
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#define RET(a) if (!(a)) { return false; }
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bool CheckLast(ArmGen::ARMXEmitter &emit, const char *comp) {
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u32 instr;
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memcpy(&instr, emit.GetCodePtr() - 4, 4);
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char disasm[512];
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ArmDis(0, instr, disasm);
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EXPECT_EQ_STR(std::string(disasm), std::string(comp));
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return true;
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}
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bool TestArmEmitter() {
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using namespace ArmGen;
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@ -45,12 +58,42 @@ bool TestArmEmitter() {
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u32 code[512];
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ARMXEmitter emitter((u8 *)code);
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emitter.LDR(R3, R7);
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RET(CheckLast(emitter, "e5973000 LDR r3, [r7, #0]"));
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emitter.VLDR(S3, R8, 48);
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RET(CheckLast(emitter, "edd81a0c VLDR s3, [r8, #48]"));
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emitter.VSTR(S5, R12, -36);
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RET(CheckLast(emitter, "ed4c2a09 VSTR s5, [r12, #-36]"));
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emitter.VADD(S1, S2, S3);
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RET(CheckLast(emitter, "ee710a21 VADD s1, s2, s3"));
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emitter.VMUL(S7, S8, S9);
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RET(CheckLast(emitter, "ee643a24 VMUL s7, s8, s9"));
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emitter.VMLA(S7, S8, S9);
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RET(CheckLast(emitter, "ee443a24 VMLA s7, s8, s9"));
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emitter.VNMLA(S7, S8, S9);
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RET(CheckLast(emitter, "ee543a64 VNMLA s7, s8, s9"));
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emitter.VABS(S1, S2);
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RET(CheckLast(emitter, "eef00ac1 VABS s1, s2"));
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emitter.VSQRT(S1, S2);
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RET(CheckLast(emitter, "eef10ac1 VSQRT s1, s2"));
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emitter.VDIV(S1, S2, S3);
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RET(CheckLast(emitter, "eec10a21 VDIV s1, s2, s3"));
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emitter.VMRS(R1);
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RET(CheckLast(emitter, "eef11a10 VMRS r1"));
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emitter.VMSR(R7);
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RET(CheckLast(emitter, "eee17a10 VMSR r7"));
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emitter.VMRS_APSR();
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RET(CheckLast(emitter, "eef1fa10 VMRS APSR"));
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emitter.VCVT(S0, S1, TO_INT | IS_SIGNED);
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RET(CheckLast(emitter, "eebd0a60 VCVT ..."));
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char disasm[512];
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ArmDis(0, code[0] & 0xFFFFFFFF, disasm);
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std::string dis(disasm);
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EXPECT_EQ_STR(dis, std::string("e4973000 LDR r3, [r7, #0]"));
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// WTF?
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//emitter.VSUB(S4, S5, S6);
|
||||
//RET(CheckLast(emitter, "ee322ac3 VSUB s4, s5, s6"));
|
||||
|
||||
|
||||
emitter.VMOV(S3, S6);
|
||||
RET(CheckLast(emitter, "eef01a43 VMOV s3, s6"));
|
||||
return true;
|
||||
}
|
||||
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user