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Author	SHA1	Message	Date
Henrik Rydgård	77355a1568	Merge pull request #17954 from unknownbrackets/x86-jit-ir ... x86jit: Fix Ext8to32/Ext16to32, some reg issues	2023-08-23 08:50:02 +02:00
Henrik Rydgård	092c6e5bca	Merge pull request #17953 from unknownbrackets/jit-prefix-cleanup ... jit: Skip known prefix writes	2023-08-23 08:47:37 +02:00
Unknown W. Brackets	efaf14a19f	x86jit: Fix spilling zero register. ... We can't flush it, but it's likely not to get "clobbered".	2023-08-22 23:29:13 -07:00
Unknown W. Brackets	c397e2e4da	x86jit: Flush reg if dirty on map as ptr.	2023-08-22 23:29:13 -07:00
Unknown W. Brackets	a1bddd880d	x86jit: Fix sign extension.	2023-08-22 23:29:13 -07:00
Unknown W. Brackets	74e5e43fdc	jit: Skip known prefix writes. ... If we already know what's in memory and it's default, we can skip overwriting with default values. This is common, actually.	2023-08-22 23:26:31 -07:00
Henrik Rydgård	a5a2af4892	Merge pull request #17944 from hrydgard/some-ir-alu ... Implement a few ALU ops in the x86 JIT-IR backend.	2023-08-22 16:38:28 +02:00
Henrik Rydgård	6a3840d9b6	Implement bswap just because	2023-08-22 16:18:03 +02:00
Henrik Rydgård	7384d3d49f	Debug mode buildfix	2023-08-22 16:15:07 +02:00
Henrik Rydgård	c5a076487e	Disable extends on x86-32	2023-08-22 16:09:45 +02:00
Henrik Rydgård	b67741509c	Implement a few ALU ops in the x86 JIT-from-IR.	2023-08-22 16:08:12 +02:00
Unknown W. Brackets	11c40e6889	x86: Implement a few basic float/vec4 ops.	2023-08-22 10:39:46 +02:00
Unknown W. Brackets	521b63dd2b	x86jit: Implement FMul.	2023-08-22 10:39:46 +02:00
Unknown W. Brackets	edcb156897	x86jit: Add Vec4 and Float load/store.	2023-08-22 10:39:46 +02:00
Henrik Rydgård	951c35ba71	Merge pull request #17948 from unknownbrackets/x86-ir ... x86jit: Fix some issues in 32-bit	2023-08-22 09:41:10 +02:00
Henrik Rydgård	a78c2e66f1	Merge pull request #17947 from ANR2ME/adhocctl ... [Adhocctl] Fix for Metal Gear Acid issue	2023-08-22 08:19:24 +02:00
Unknown W. Brackets	07fa1ed573	x86jit: Automatically flush incompatible regs.	2023-08-21 21:16:54 -07:00
Unknown W. Brackets	55654f52b2	x86jit: Fix Store8 on i386. ... Require an 8-bit capable register in mapping.	2023-08-21 21:05:51 -07:00
Unknown W. Brackets	db34b85107	irjit: Allow flag-based allocation order. ... Sometimes backends have needs, like XMM0/v0-only, or similar.	2023-08-21 20:46:05 -07:00
Unknown W. Brackets	bea74ba162	x86jit: Avoid negative offset warning.	2023-08-21 20:38:56 -07:00
ANR2ME	3c66523f04	A quick fix for Metal Gear Acid due to adhocctl's busy state never reset to false when there are no adhocctl's handler.	2023-08-22 04:29:07 +07:00
Unknown W. Brackets	1ccc2d5d2f	x86jit: Fix address offsets with memview mask.	2023-08-21 09:03:10 -07:00
Unknown W. Brackets	40b3ff9573	x86jit: Fix spill issue.	2023-08-21 08:23:58 -07:00
Henrik Rydgård	1066cac91a	Merge pull request #17945 from DDinghoya/DDinghoya-patch-1-1 ... Update ko_KR.ini	2023-08-21 16:30:38 +02:00
DDinghoya	3c61f4f5ce	Update ko_KR.ini	2023-08-21 22:53:17 +09:00
Henrik Rydgård	a06cf1cc47	Merge pull request #17914 from basharast/master ... [Windows] OSVersion improvements	2023-08-21 14:40:42 +02:00
Henrik Rydgård	1e269c1d3c	Merge pull request #17943 from unknownbrackets/x86-ir ... Add an x86/x64 backend for IR	2023-08-21 09:21:37 +02:00
Unknown W. Brackets	538832940a	x86jit: Implement some shifts.	2023-08-21 00:07:42 -07:00
Henrik Rydgård	61bf366d30	Merge pull request #17942 from unknownbrackets/irjit-clobber ... irjit: Fix regalloc clobber on exit	2023-08-21 08:04:50 +02:00
Unknown W. Brackets	2b914046ff	x86jit: Implement most exits.	2023-08-20 22:28:54 -07:00
Unknown W. Brackets	104b6d8c15	x86jit: Implement some basic arithmetic.	2023-08-20 22:28:54 -07:00
Unknown W. Brackets	5045cf012e	x86jit: Fix flushing of zero register.	2023-08-20 22:28:54 -07:00
Unknown W. Brackets	08ea31f405	x86jit: Improve debug disasm.	2023-08-20 22:28:54 -07:00
Unknown W. Brackets	4e7f8cf213	x86jit: Implement load/store.	2023-08-20 22:28:54 -07:00
Unknown W. Brackets	a47b4424e5	x86jit: Fix some silly mistakes.	2023-08-20 22:28:54 -07:00
Unknown W. Brackets	4e3f3860f9	x86jit: Stub out op categories to files.	2023-08-20 22:28:54 -07:00
Unknown W. Brackets	622c69dbb9	x86jit: Expose option to select new IR based jit.	2023-08-20 22:28:54 -07:00
Unknown W. Brackets	c491f701ba	x86jit: Add initial IR-based jit backend. ... It works, but pretty slow in some parts with everything stubbed.	2023-08-20 22:28:54 -07:00
Unknown W. Brackets	81e24a9fee	irjit: Fix regalloc clobber on exit.	2023-08-20 22:12:52 -07:00
Henrik Rydgård	4d285305f4	Merge pull request #17941 from unknownbrackets/riscv-jit-opt ... riscv: Use a single reg for LO/HI	2023-08-21 00:30:47 +02:00
Unknown W. Brackets	8dfc2f04d7	riscv: Use a single reg for LO/HI. ... This is the same optimization we have for arm64, basically.	2023-08-20 14:49:09 -07:00
Henrik Rydgård	629d46ef5b	Merge pull request #17938 from unknownbrackets/riscv-centralize ... Centralize IR regcache from RISC-V	2023-08-20 23:47:02 +02:00
Henrik Rydgård	6554b3eb75	Merge pull request #17939 from unknownbrackets/ir-vec-minor ... irjit: Implement vtfm 4x4 using dots	2023-08-20 23:40:04 +02:00
Henrik Rydgård	b90d628137	Merge pull request #17937 from unknownbrackets/irjit-compile ... Reduce time spent in IR compile	2023-08-20 23:38:07 +02:00
Unknown W. Brackets	82fb41cba0	irjit: Implement vtfm 4x4 using dots.	2023-08-20 13:50:02 -07:00
Unknown W. Brackets	36b6aa4728	riscv: Allow GPR "SIMD" without FPR SIMD.	2023-08-20 12:42:11 -07:00
Unknown W. Brackets	6a75e6712e	riscv: Use automapping for special cases too.	2023-08-20 12:42:11 -07:00
Unknown W. Brackets	a190793ad2	riscv: Simplify mapping for more instructions.	2023-08-20 12:42:11 -07:00
Unknown W. Brackets	cc4bc406d5	riscv: Cleanup VfpuCtrlToReg meta, use auto-map.	2023-08-20 12:42:11 -07:00
Unknown W. Brackets	e40ae60029	riscv: Mark normalized32 after mapping. ... It's less confusing to separate it.	2023-08-20 12:42:11 -07:00