Unknown W. Brackets
52db66e7ad
riscv: Add vector bitmanip encoding.
2023-12-29 09:42:23 -08:00
Unknown W. Brackets
e5467d2706
riscv: Add czero instruction encoding.
2023-12-29 09:42:23 -08:00
Unknown W. Brackets
e3c6add63a
riscv: Add encoding for Zcb.
2023-12-29 09:42:23 -08:00
Unknown W. Brackets
15cb782f85
riscv: Implement Zfa encoding.
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Not yet enabled/detected.
2023-12-29 09:42:23 -08:00
Unknown W. Brackets
4b9011e475
riscv: Reduce call bloat using temps.
2023-08-08 23:17:32 -07:00
Unknown W. Brackets
720f868a10
riscv: Use R_RA as a temporary for calls.
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This is the most logical thing, since we're about to write it anyway.
2023-07-23 18:01:00 -07:00
Unknown W. Brackets
76e3246065
riscv: Reduce jit codesize a bit.
2023-07-23 18:01:00 -07:00
Unknown W. Brackets
47b81985bd
riscv: Initial untested dispatcher.
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The minimum to actually, probably, running code. Pretty slow.
2023-07-23 18:01:00 -07:00
Unknown W. Brackets
fa1da3118f
riscv: Add some quick aliases.
2023-06-06 23:48:08 -07:00
Unknown W. Brackets
27e60a9f2e
riscv: Sum weighted matrices in vertexjit.
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Not yet doing pos/norm, so not used yet.
2023-02-16 18:32:58 -08:00
Unknown W. Brackets
77b2e63876
riscv: Add colors to vertexjit.
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This don't feel very efficient, but they overall beat non-jit.
2023-02-12 23:05:35 -08:00
Unknown W. Brackets
89c18d8077
riscv: Cleanup missing Poison, Crash.
2023-02-12 12:10:29 -08:00
Unknown W. Brackets
a0ef9ce103
riscv: Add half-float encodings.
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These are simple.
2023-01-29 16:31:01 -08:00
Unknown W. Brackets
3bc2450b5e
riscv: Add bitmanip instructions to emitter ( #16832 )
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* riscv: Cleanup emitter, add bitmanip detect.
Better to encode using Funct7::ZERO, and obviously for SRA.
* riscv: Add bitmanip instructions to emitter.
2023-01-22 21:37:47 +01:00
Unknown W. Brackets
2aeee83971
riscv: Add vector transfer instructions.
2023-01-22 00:17:40 -08:00
Unknown W. Brackets
c99eb18f33
riscv: Add vector mask instructions.
2023-01-21 23:43:28 -08:00
Unknown W. Brackets
88de043329
riscv: Add vector reduce instructions.
2023-01-21 22:35:38 -08:00
Unknown W. Brackets
2a7bdbf802
riscv: Add vector float move/compare/unary.
2023-01-21 22:05:13 -08:00
Unknown W. Brackets
f0796676fd
riscv: Add vector float arith/mul funcs.
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Including all the fused multiplies.
2023-01-21 20:48:49 -08:00
Unknown W. Brackets
a1ca291362
riscv: Add vector fixed-point arith instructions.
2023-01-21 20:23:10 -08:00
Unknown W. Brackets
a313e440b4
riscv: Add vector integer move/broadcast.
2023-01-21 19:46:50 -08:00
Unknown W. Brackets
6f78f2a2d2
riscv: Add vector integer muliplies.
2023-01-21 19:46:34 -08:00
Unknown W. Brackets
b3be901557
riscv: Add vector bitwise/compare funcs.
2023-01-21 19:36:22 -08:00
Unknown W. Brackets
6fa50eaa82
riscv: Add vector int add/sub and many encodings.
2023-01-21 19:36:11 -08:00
Unknown W. Brackets
bfd60a67ad
riscv: Add vector load/store ops.
2023-01-21 19:36:11 -08:00
Unknown W. Brackets
9cfcbc46e6
Global: Cleanup initialization/pointer checks.
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Cleaning up a lot of cases of uninitialized data, unchecked return values
for failures, and similar.
2022-12-10 21:13:36 -08:00
Unknown W. Brackets
08d82ec15b
riscv: Emit compressed instructions.
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Includes automatically using compressed, optionally.
2022-08-27 15:44:19 -07:00
Unknown W. Brackets
c81d887a86
riscv: Include an LI helper in the emitter.
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Can be used for integers and floats.
2022-08-27 15:44:18 -07:00
Unknown W. Brackets
4a93647acb
riscv: Emit CSR manipulation instructions.
2022-08-25 21:20:49 -07:00
Unknown W. Brackets
b5755b6cf7
riscv: Validate FixupBranch usage better.
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Also avoid FixupBranch alignment issues.
2022-08-25 21:20:49 -07:00
Unknown W. Brackets
591de6be1d
riscv: Emit float instructions.
2022-08-25 21:19:28 -07:00
Unknown W. Brackets
53693072d2
riscv: Emit atomic operations.
2022-08-25 21:19:28 -07:00
Unknown W. Brackets
c66d02d4db
riscv: Emit mul/div instructions.
2022-08-25 21:19:28 -07:00
Unknown W. Brackets
00280ab2ad
riscv: Emit fence and 64-bit instructions.
2022-08-25 21:19:28 -07:00
Unknown W. Brackets
49ec8a207d
riscv: Emit 32-bit 3-op instructions, validate GPR.
2022-08-25 21:19:27 -07:00
Unknown W. Brackets
1c35cfb325
riscv: Emit 32-bit load/store and imm ops.
2022-08-25 21:19:27 -07:00
Unknown W. Brackets
1dab9d1875
riscv: Emit standard B/U/J type ops.
2022-08-25 21:19:27 -07:00
Unknown W. Brackets
9fcad83940
riscv: Add initial emitter shell.
2022-08-25 21:17:11 -07:00
