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37,623 Commits 72 Branches 122 Tags 697 MiB
c2f9ae2e16
Commit Graph

12263 Commits

Author SHA1 Message Date
Nemoumbra
c2f9ae2e16 Buildfix for VS2017 2023-08-06 15:06:54 +03:00
Henrik Rydgård
a32249a3cf Move DebugOverlay rendering to the overlay screen, allowing drawing it on top of the menu 2023-08-03 16:19:18 +02:00
Henrik Rydgård
ece6a505b3
Merge pull request #17837 from hrydgard/frame-history 
Vulkan: Keep track of a short history of some timestamps in each frame
 2023-08-02 17:06:55 +02:00
Hoe Hao Cheng
805821e01e Core: decouple UpdateScreenScale from preprocessor defines 2023-08-02 22:34:46 +08:00
Hoe Hao Cheng
0d7a1831b6 sdl: support HiDPI on wayland 2023-08-02 22:34:46 +08:00
Henrik Rydgård
cda59e8510 Vulkan: Keep track of some timestamps in a frame 2023-08-02 16:25:17 +02:00
Henrik Rydgård
0b4fee1259 One too much 2023-08-02 14:07:47 +02:00
Henrik Rydgård
c3511529e4 Somehow forgot to delete some unused bools 2023-08-02 14:07:05 +02:00
Henrik Rydgård
fc6879674e Refactor overlays into an enum 2023-08-02 13:03:04 +02:00
Henrik Rydgård
9a8919810b Translation cleanups 2023-08-01 13:04:52 +02:00
Henrik Rydgård
f45176fd25 Allow configuring in which corner achievement notifications can show up. 2023-08-01 12:52:09 +02:00
Henrik Rydgård
1071e1f248 Move towards separate types for leaderboard events 2023-08-01 11:57:28 +02:00
Henrik Rydgård
d268dd639a Move the ScreenEdgePosition enum to a more appropriate location 2023-08-01 01:01:57 +02:00
Henrik Rydgård
3563d625b9 Allow configuring the location on-screen of leaderboard trackers. 2023-08-01 00:28:54 +02:00
Henrik Rydgård
48d577014a Refactor the on-screen display to be more customizable 2023-08-01 00:28:54 +02:00
Henrik Rydgård
f39b9640b7 Rename the ChatPosition enum to a ScreenEdgePosition enum class (for future use) 2023-08-01 00:28:54 +02:00
Unknown W. Brackets
0d0029fc9d riscv: Add bitmanip ops to disasm. 2023-07-30 17:45:36 -07:00
Unknown W. Brackets
c24dca12bb Build: Fix link issue for rv64 disasm. 2023-07-30 16:06:55 -07:00
Unknown W. Brackets
b03398a46c
Merge pull request #17815 from unknownbrackets/riscv-jit 
riscv: Spill registers more intelligently
 2023-07-30 14:49:37 -07:00
Henrik Rydgård
fa2b831dbc
Merge pull request #17814 from unknownbrackets/riscv-jit-debug 
riscv: Implement block debug interface
 2023-07-30 23:42:14 +02:00
Henrik Rydgård
fa558b5b71
Merge pull request #17813 from unknownbrackets/riscv-jit-fixes 
Fix some typos and mistakes in RISC-V jit
 2023-07-30 23:41:13 +02:00
Henrik Rydgård
100f7c838e
Merge pull request #17812 from unknownbrackets/irjit-floats 
Cleanup IR cond move flag, fmov to self
 2023-07-30 23:36:37 +02:00
Unknown W. Brackets
f870271011 riscv: Spill registers more intelligently. 2023-07-30 14:24:12 -07:00
Unknown W. Brackets
020706f545 riscv: Implement float saturate clamping. 2023-07-30 14:24:12 -07:00
Unknown W. Brackets
45d44c1d4f riscv: Implement block debug interface. 
This gives us the target disasm in jit compare, bloat, etc.
 2023-07-30 14:21:43 -07:00
Unknown W. Brackets
5ef4b2b5fa riscv: Fix assert when flushing not mapped reg. 2023-07-30 14:19:28 -07:00
Unknown W. Brackets
9f917488c3 riscv: Fix PC in disassembly. 2023-07-30 14:19:28 -07:00
Unknown W. Brackets
e34736fbb2 riscv: Reduce norms in Slt/Sltu overlap cases. 
We can skip an SEXT.W in common cases where the dest and src overlap.
 2023-07-30 14:19:28 -07:00
Unknown W. Brackets
d1dc346899 riscv: Fix pointer add/sub. 2023-07-30 14:19:28 -07:00
Unknown W. Brackets
09f3842a32 riscv: Fix VFPU compare typos. 2023-07-30 14:19:28 -07:00
Unknown W. Brackets
f3240393fa irjit: Use vf for vfpu regs, v0 is a gpr. 2023-07-30 14:16:17 -07:00
Unknown W. Brackets
6819acd29f irjit: Fix flag on float cond move. 2023-07-30 14:16:17 -07:00
Unknown W. Brackets
5db6b11ef2 irjit: Cleanup self-fmovs. 
These were sometimes getting emitted.
 2023-07-30 14:16:17 -07:00
Henrik Rydgård
f0fd9e85aa Try dirtying CULL_PLANES in Execute_BoundingBox in SoftGPU 2023-07-30 18:35:18 +02:00
Henrik Rydgård
36951a0b98
Merge pull request #17806 from hrydgard/update-rcheevos 
Update to the latest version of rcheevos.
 2023-07-30 12:19:40 +02:00
Henrik Rydgård
1c05f71b50 Update to the latest version of rcheevos. 2023-07-30 11:58:55 +02:00
Unknown W. Brackets
c24e3ef831 riscv: Implement ll/sc. 2023-07-30 00:45:51 -07:00
Unknown W. Brackets
26a527bdf8 riscv: Implement float/int conversion. 2023-07-30 00:45:51 -07:00
Henrik Rydgård
b93275bb35
Merge pull request #17800 from unknownbrackets/riscv-jit 
More RISC-V jit ops
 2023-07-30 09:26:22 +02:00
Henrik Rydgård
c8447ff4b7
Merge pull request #17801 from unknownbrackets/irjit-vminmax 
irjit: Fix vmin/vmax nan handling
 2023-07-30 09:18:25 +02:00
Henrik Rydgård
180bda6f6b
Merge pull request #17799 from unknownbrackets/irjit-lsu 
Add ll/sc to IR and x86jit
 2023-07-30 09:15:55 +02:00
Unknown W. Brackets
0036f3c494 riscv: Implement FMin/FMax. 2023-07-30 00:02:10 -07:00
Unknown W. Brackets
8e8081c686 riscv: Implement VFPU compares. 2023-07-30 00:02:10 -07:00
Unknown W. Brackets
9c9330a207 riscv: Implement float conditional move. 2023-07-30 00:02:10 -07:00
Unknown W. Brackets
70ff18a463 riscv: Implement count leading zeros. 2023-07-30 00:02:10 -07:00
Unknown W. Brackets
a5671bc716 riscv: Add simple debug log of missed ops. 2023-07-30 00:02:10 -07:00
Unknown W. Brackets
6aa4b0c5e1 irjit: Fix vmin/vmax nan handling. 
Should be relevant to NFS MW and possibly other game bugs.
 2023-07-29 19:13:12 -07:00
Unknown W. Brackets
6d4fb949c2 riscv: Implement float compare ops. 2023-07-29 19:02:15 -07:00
Unknown W. Brackets
6b632a103d riscv: Implement FSin/similar. 2023-07-29 19:02:15 -07:00
Unknown W. Brackets
921bd2391c riscv: Implement vi2s. 2023-07-29 19:02:15 -07:00