mirror of
https://github.com/hrydgard/ppsspp.git
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125 lines
3.4 KiB
C++
125 lines
3.4 KiB
C++
// Copyright (c) 2012- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#include "Core/Config.h"
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#include "Core/MemMap.h"
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#include "Core/MIPS/MIPS.h"
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#include "Core/MIPS/MIPSAnalyst.h"
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#include "Core/MIPS/MIPSCodeUtils.h"
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#include "Core/MIPS/IR/IRFrontend.h"
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#include "Core/MIPS/IR/IRRegCache.h"
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#define _RS MIPS_GET_RS(op)
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#define _RT MIPS_GET_RT(op)
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#define _RD MIPS_GET_RD(op)
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#define _FS MIPS_GET_FS(op)
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#define _FT MIPS_GET_FT(op)
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#define _FD MIPS_GET_FD(op)
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#define _SA MIPS_GET_SA(op)
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#define _POS ((op>> 6) & 0x1F)
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#define _SIZE ((op>>11) & 0x1F)
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#define _IMM16 (signed short)(op & 0xFFFF)
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#define _IMM26 (op & 0x03FFFFFF)
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// All functions should have CONDITIONAL_DISABLE, so we can narrow things down to a file quickly.
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// Currently known non working ones should have DISABLE.
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// #define CONDITIONAL_DISABLE(flag) { Comp_Generic(op); return; }
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#define CONDITIONAL_DISABLE(flag) if (opts.disableFlags & (uint32_t)JitDisable::flag) { Comp_Generic(op); return; }
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#define DISABLE { Comp_Generic(op); return; }
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#define INVALIDOP { Comp_Generic(op); return; }
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namespace MIPSComp {
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void IRFrontend::Comp_ITypeMem(MIPSOpcode op) {
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CONDITIONAL_DISABLE(LSU);
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int offset = _IMM16;
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MIPSGPReg rt = _RT;
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MIPSGPReg rs = _RS;
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int o = op >> 26;
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if (((op >> 29) & 1) == 0 && rt == MIPS_REG_ZERO) {
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// Don't load anything into $zr
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return;
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}
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CheckMemoryBreakpoint(rs, offset);
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switch (o) {
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// Load
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case 35:
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ir.Write(IROp::Load32, rt, rs, ir.AddConstant(offset));
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break;
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case 37:
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ir.Write(IROp::Load16, rt, rs, ir.AddConstant(offset));
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break;
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case 33:
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ir.Write(IROp::Load16Ext, rt, rs, ir.AddConstant(offset));
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break;
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case 36:
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ir.Write(IROp::Load8, rt, rs, ir.AddConstant(offset));
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break;
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case 32:
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ir.Write(IROp::Load8Ext, rt, rs, ir.AddConstant(offset));
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break;
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// Store
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case 43:
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ir.Write(IROp::Store32, rt, rs, ir.AddConstant(offset));
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break;
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case 41:
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ir.Write(IROp::Store16, rt, rs, ir.AddConstant(offset));
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break;
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case 40:
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ir.Write(IROp::Store8, rt, rs, ir.AddConstant(offset));
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break;
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case 34: //lwl
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ir.Write(IROp::Load32Left, rt, rs, ir.AddConstant(offset));
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break;
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case 38: //lwr
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ir.Write(IROp::Load32Right, rt, rs, ir.AddConstant(offset));
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break;
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case 42: //swl
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ir.Write(IROp::Store32Left, rt, rs, ir.AddConstant(offset));
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break;
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case 46: //swr
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ir.Write(IROp::Store32Right, rt, rs, ir.AddConstant(offset));
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break;
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default:
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INVALIDOP;
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return;
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}
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}
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void IRFrontend::Comp_Cache(MIPSOpcode op) {
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CONDITIONAL_DISABLE(LSU);
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int func = (op >> 16) & 0x1F;
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// See Int_Cache for the definitions.
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switch (func) {
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case 24: break;
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case 25: break;
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case 27: break;
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case 30: break;
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default:
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// Fall back to the interpreter.
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DISABLE;
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}
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}
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}
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