mirror of
https://github.com/FEX-Emu/FEX.git
synced 2025-02-09 08:32:57 +00:00
InstCountCI: Update
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
This commit is contained in:
Alyssa Rosenzweig
parent
80e632db8a
commit
045549f166
@ -15,10 +15,10 @@
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"Comment": "0x00",
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"ExpectedArm64ASM": [
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"ldaddalb w5, w20, [x4]",
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"add w26, w20, w5",
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"eor w27, w20, w5",
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"lsl w0, w20, #24",
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"cmn w0, w5, lsl #24"
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"cmn w0, w5, lsl #24",
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"add w26, w20, w5"
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]
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},
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"lock add word [rax], cx": {
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@ -26,20 +26,19 @@
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"Comment": "0x01",
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"ExpectedArm64ASM": [
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"ldaddalh w5, w20, [x4]",
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"add w26, w20, w5",
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"eor w27, w20, w5",
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"lsl w0, w20, #16",
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"cmn w0, w5, lsl #16"
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"cmn w0, w5, lsl #16",
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"add w26, w20, w5"
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]
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},
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"lock add dword [rax], ecx": {
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"ExpectedInstructionCount": 4,
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"ExpectedInstructionCount": 3,
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"Comment": "0x01",
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"ExpectedArm64ASM": [
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"ldaddal w5, w20, [x4]",
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"add w26, w20, w5",
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"eor w27, w20, w5",
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"cmn w20, w5"
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"adds w26, w20, w5"
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]
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},
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"lock or byte [rax], cl": {
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@ -251,10 +250,10 @@
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"ExpectedArm64ASM": [
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"neg w1, w5",
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"ldaddalb w1, w20, [x4]",
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"sub w26, w20, w5",
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"eor w27, w20, w5",
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"lsl w0, w20, #24",
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"cmp w0, w5, lsl #24",
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"sub w26, w20, w5",
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"mrs x20, nzcv",
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"eor w20, w20, #0x20000000",
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"msr nzcv, x20"
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@ -266,24 +265,23 @@
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"ExpectedArm64ASM": [
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"neg w1, w5",
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"ldaddalh w1, w20, [x4]",
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"sub w26, w20, w5",
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"eor w27, w20, w5",
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"lsl w0, w20, #16",
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"cmp w0, w5, lsl #16",
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"sub w26, w20, w5",
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"mrs x20, nzcv",
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"eor w20, w20, #0x20000000",
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"msr nzcv, x20"
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]
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},
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"lock sub dword [rax], ecx": {
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"ExpectedInstructionCount": 8,
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"ExpectedInstructionCount": 7,
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"Comment": "0x29",
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"ExpectedArm64ASM": [
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"neg w1, w5",
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"ldaddal w1, w20, [x4]",
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"sub w26, w20, w5",
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"eor w27, w20, w5",
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"cmp w20, w5",
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"subs w26, w20, w5",
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"mrs x20, nzcv",
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"eor w20, w20, #0x20000000",
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"msr nzcv, x20"
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@ -317,13 +315,12 @@
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]
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},
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"lock add qword [rax], rcx": {
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"ExpectedInstructionCount": 4,
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"ExpectedInstructionCount": 3,
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"Comment": "0x01",
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"ExpectedArm64ASM": [
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"ldaddal x5, x20, [x4]",
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"add x26, x20, x5",
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"eor w27, w20, w5",
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"cmn x20, x5"
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"adds x26, x20, x5"
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]
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},
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"xchg byte [rax], cl": {
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@ -367,10 +364,10 @@
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"uxtb w20, w7",
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"ldaddalb w20, w21, [x4]",
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"bfxil x7, x21, #0, #8",
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"add w26, w21, w20",
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"eor w27, w21, w20",
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"lsl w0, w21, #24",
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"cmn w0, w20, lsl #24"
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"cmn w0, w20, lsl #24",
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"add w26, w21, w20"
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]
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},
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"xadd word [rax], bx": {
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@ -380,32 +377,30 @@
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"uxth w20, w7",
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"ldaddalh w20, w21, [x4]",
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"bfxil x7, x21, #0, #16",
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"add w26, w21, w20",
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"eor w27, w21, w20",
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"lsl w0, w21, #16",
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"cmn w0, w20, lsl #16"
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"cmn w0, w20, lsl #16",
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"add w26, w21, w20"
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]
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},
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"xadd dword [rax], ebx": {
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"ExpectedInstructionCount": 5,
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"ExpectedInstructionCount": 4,
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"Comment": "0x0f 0xc1",
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"ExpectedArm64ASM": [
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"mov w20, w7",
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"ldaddal w20, w7, [x4]",
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"add w26, w7, w20",
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"eor w27, w7, w20",
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"cmn w7, w20"
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"adds w26, w7, w20"
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]
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},
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"xadd qword [rax], rbx": {
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"ExpectedInstructionCount": 5,
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"ExpectedInstructionCount": 4,
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"Comment": "0x0f 0xc1",
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"ExpectedArm64ASM": [
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"mov x20, x7",
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"ldaddal x20, x7, [x4]",
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"add x26, x7, x20",
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"eor w27, w7, w20",
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"cmn x7, x20"
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"adds x26, x7, x20"
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]
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},
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"lock add byte [rax], 1": {
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@ -414,9 +409,9 @@
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"ExpectedArm64ASM": [
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"mov w20, #0x1",
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"ldaddalb w20, w27, [x4]",
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"add w26, w27, #0x1 (1)",
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"lsl w0, w27, #24",
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"cmn w0, w20, lsl #24"
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"cmn w0, w20, lsl #24",
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"add w26, w27, #0x1 (1)"
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]
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},
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"lock add byte [rax], 0xFF": {
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@ -425,10 +420,10 @@
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"ExpectedArm64ASM": [
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"mov w20, #0xff",
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"ldaddalb w20, w21, [x4]",
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"add w26, w21, #0xff (255)",
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"eor w27, w21, #0xff",
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"lsl w0, w21, #24",
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"cmn w0, w20, lsl #24"
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"cmn w0, w20, lsl #24",
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"add w26, w21, #0xff (255)"
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]
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},
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"lock add word [rax], 0x100": {
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@ -437,9 +432,9 @@
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"ExpectedArm64ASM": [
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"mov w20, #0x100",
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"ldaddalh w20, w27, [x4]",
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"add w26, w27, #0x100 (256)",
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"lsl w0, w27, #16",
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"cmn w0, w20, lsl #16"
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"cmn w0, w20, lsl #16",
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"add w26, w27, #0x100 (256)"
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]
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},
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"lock add word [rax], 0xFFFF": {
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@ -448,51 +443,47 @@
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"ExpectedArm64ASM": [
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"mov w20, #0xffff",
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"ldaddalh w20, w21, [x4]",
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"add w26, w21, w20",
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"eor w27, w21, #0xffff",
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"lsl w0, w21, #16",
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"cmn w0, w20, lsl #16"
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"cmn w0, w20, lsl #16",
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"add w26, w21, w20"
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]
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},
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"lock add dword [rax], 0x100": {
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"ExpectedInstructionCount": 4,
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"ExpectedInstructionCount": 3,
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"Comment": "GROUP1 0x81 /0",
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"ExpectedArm64ASM": [
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"mov w20, #0x100",
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"ldaddal w20, w27, [x4]",
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"add w26, w27, #0x100 (256)",
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"cmn w27, #0x100 (256)"
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"adds w26, w27, #0x100 (256)"
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]
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},
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"lock add dword [rax], 0xFFFFFFFF": {
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"ExpectedInstructionCount": 5,
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"ExpectedInstructionCount": 4,
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"Comment": "GROUP1 0x81 /0",
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"ExpectedArm64ASM": [
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"mov w20, #0xffffffff",
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"ldaddal w20, w21, [x4]",
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"add w26, w21, w20",
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"eor w27, w21, w20",
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"cmn w21, w20"
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"adds w26, w21, w20"
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]
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},
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"lock add qword [rax], 0x100": {
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"ExpectedInstructionCount": 4,
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"ExpectedInstructionCount": 3,
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"Comment": "GROUP1 0x81 /0",
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"ExpectedArm64ASM": [
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"mov w20, #0x100",
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"ldaddal x20, x27, [x4]",
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"add x26, x27, #0x100 (256)",
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"cmn x27, #0x100 (256)"
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"adds x26, x27, #0x100 (256)"
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]
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},
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"lock add qword [rax], -2147483647": {
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"ExpectedInstructionCount": 4,
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"ExpectedInstructionCount": 3,
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"Comment": "GROUP1 0x81 /0",
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"ExpectedArm64ASM": [
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"mov x20, #0xffffffff80000001",
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"ldaddal x20, x27, [x4]",
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"add x26, x27, x20",
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"cmn x27, x20"
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"adds x26, x27, x20"
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]
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},
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"lock add word [rax], 1": {
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@ -501,29 +492,27 @@
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"ExpectedArm64ASM": [
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"mov w20, #0x1",
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"ldaddalh w20, w27, [x4]",
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"add w26, w27, #0x1 (1)",
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"lsl w0, w27, #16",
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"cmn w0, w20, lsl #16"
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"cmn w0, w20, lsl #16",
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"add w26, w27, #0x1 (1)"
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]
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},
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"lock add dword [rax], 1": {
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"ExpectedInstructionCount": 4,
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"ExpectedInstructionCount": 3,
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"Comment": "GROUP1 0x83 /0",
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"ExpectedArm64ASM": [
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"mov w20, #0x1",
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"ldaddal w20, w27, [x4]",
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"add w26, w27, #0x1 (1)",
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"cmn w27, #0x1 (1)"
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"adds w26, w27, #0x1 (1)"
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]
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},
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"lock add qword [rax], 1": {
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"ExpectedInstructionCount": 4,
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"ExpectedInstructionCount": 3,
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"Comment": "GROUP1 0x83 /0",
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"ExpectedArm64ASM": [
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"mov w20, #0x1",
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"ldaddal x20, x27, [x4]",
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"add x26, x27, #0x1 (1)",
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"cmn x27, #0x1 (1)"
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"adds x26, x27, #0x1 (1)"
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]
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},
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"lock or byte [rax], 1": {
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@ -1205,9 +1194,9 @@
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"mov w20, #0x1",
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"neg w1, w20",
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"ldaddalb w1, w27, [x4]",
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"sub w26, w27, #0x1 (1)",
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"lsl w0, w27, #24",
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"cmp w0, w20, lsl #24",
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"sub w26, w27, #0x1 (1)",
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"mrs x20, nzcv",
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"eor w20, w20, #0x20000000",
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"msr nzcv, x20"
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@ -1220,10 +1209,10 @@
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"mov w20, #0xff",
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"neg w1, w20",
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"ldaddalb w1, w21, [x4]",
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"sub w26, w21, #0xff (255)",
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"eor w27, w21, #0xff",
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"lsl w0, w21, #24",
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"cmp w0, w20, lsl #24",
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"sub w26, w21, #0xff (255)",
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"mrs x20, nzcv",
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"eor w20, w20, #0x20000000",
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"msr nzcv, x20"
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@ -1236,9 +1225,9 @@
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"mov w20, #0x100",
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"neg w1, w20",
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"ldaddalh w1, w27, [x4]",
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"sub w26, w27, #0x100 (256)",
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"lsl w0, w27, #16",
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"cmp w0, w20, lsl #16",
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"sub w26, w27, #0x100 (256)",
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"mrs x20, nzcv",
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"eor w20, w20, #0x20000000",
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"msr nzcv, x20"
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@ -1251,67 +1240,63 @@
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"mov w20, #0xffff",
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"neg w1, w20",
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"ldaddalh w1, w21, [x4]",
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"sub w26, w21, w20",
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"eor w27, w21, #0xffff",
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"lsl w0, w21, #16",
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"cmp w0, w20, lsl #16",
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"sub w26, w21, w20",
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"mrs x20, nzcv",
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"eor w20, w20, #0x20000000",
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"msr nzcv, x20"
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]
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},
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"lock sub dword [rax], 0x100": {
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"ExpectedInstructionCount": 8,
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"ExpectedInstructionCount": 7,
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"Comment": "GROUP1 0x81 /5",
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"ExpectedArm64ASM": [
|
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"mov w20, #0x100",
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"neg w1, w20",
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"ldaddal w1, w27, [x4]",
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"sub w26, w27, #0x100 (256)",
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"cmp w27, #0x100 (256)",
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"subs w26, w27, #0x100 (256)",
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"mrs x20, nzcv",
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"eor w20, w20, #0x20000000",
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"msr nzcv, x20"
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]
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},
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"lock sub dword [rax], 0xFFFFFFFF": {
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"ExpectedInstructionCount": 9,
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"ExpectedInstructionCount": 8,
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"Comment": "GROUP1 0x81 /5",
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"ExpectedArm64ASM": [
|
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"mov w20, #0xffffffff",
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"neg w1, w20",
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"ldaddal w1, w21, [x4]",
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"sub w26, w21, w20",
|
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"eor w27, w21, w20",
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"cmp w21, w20",
|
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"subs w26, w21, w20",
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"mrs x20, nzcv",
|
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"eor w20, w20, #0x20000000",
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"msr nzcv, x20"
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]
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},
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"lock sub qword [rax], 0x100": {
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"ExpectedInstructionCount": 8,
|
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"ExpectedInstructionCount": 7,
|
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"Comment": "GROUP1 0x81 /5",
|
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"ExpectedArm64ASM": [
|
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"mov w20, #0x100",
|
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"neg x1, x20",
|
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"ldaddal x1, x27, [x4]",
|
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"sub x26, x27, #0x100 (256)",
|
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"cmp x27, #0x100 (256)",
|
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"subs x26, x27, #0x100 (256)",
|
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"mrs x20, nzcv",
|
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"eor w20, w20, #0x20000000",
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"msr nzcv, x20"
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]
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},
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"lock sub qword [rax], -2147483647": {
|
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"ExpectedInstructionCount": 8,
|
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"ExpectedInstructionCount": 7,
|
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"Comment": "GROUP1 0x81 /5",
|
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"ExpectedArm64ASM": [
|
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"mov x20, #0xffffffff80000001",
|
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"neg x1, x20",
|
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"ldaddal x1, x27, [x4]",
|
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"sub x26, x27, x20",
|
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"cmp x27, x20",
|
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"subs x26, x27, x20",
|
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"mrs x20, nzcv",
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"eor w20, w20, #0x20000000",
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"msr nzcv, x20"
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@ -1324,37 +1309,35 @@
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"mov w20, #0x1",
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"neg w1, w20",
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"ldaddalh w1, w27, [x4]",
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"sub w26, w27, #0x1 (1)",
|
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"lsl w0, w27, #16",
|
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"cmp w0, w20, lsl #16",
|
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"sub w26, w27, #0x1 (1)",
|
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"mrs x20, nzcv",
|
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"eor w20, w20, #0x20000000",
|
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"msr nzcv, x20"
|
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]
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},
|
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"lock sub dword [rax], 1": {
|
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"ExpectedInstructionCount": 8,
|
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"ExpectedInstructionCount": 7,
|
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"Comment": "GROUP1 0x83 /5",
|
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"ExpectedArm64ASM": [
|
||||
"mov w20, #0x1",
|
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"neg w1, w20",
|
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"ldaddal w1, w27, [x4]",
|
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"sub w26, w27, #0x1 (1)",
|
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"cmp w27, #0x1 (1)",
|
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"subs w26, w27, #0x1 (1)",
|
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"mrs x20, nzcv",
|
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"eor w20, w20, #0x20000000",
|
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"msr nzcv, x20"
|
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]
|
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},
|
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"lock sub qword [rax], 1": {
|
||||
"ExpectedInstructionCount": 8,
|
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"ExpectedInstructionCount": 7,
|
||||
"Comment": "GROUP1 0x83 /5",
|
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"ExpectedArm64ASM": [
|
||||
"mov w20, #0x1",
|
||||
"neg x1, x20",
|
||||
"ldaddal x1, x27, [x4]",
|
||||
"sub x26, x27, #0x1 (1)",
|
||||
"cmp x27, #0x1 (1)",
|
||||
"subs x26, x27, #0x1 (1)",
|
||||
"mrs x20, nzcv",
|
||||
"eor w20, w20, #0x20000000",
|
||||
"msr nzcv, x20"
|
||||
@ -1477,10 +1460,10 @@
|
||||
"mov w20, #0x1",
|
||||
"neg w1, w20",
|
||||
"ldaddalb w1, w27, [x4]",
|
||||
"sub w26, w27, #0x1 (1)",
|
||||
"cset w21, hs",
|
||||
"lsl w0, w27, #24",
|
||||
"cmp w0, w20, lsl #24",
|
||||
"sub w26, w27, #0x1 (1)",
|
||||
"mrs x20, nzcv",
|
||||
"bfi w20, w21, #29, #1",
|
||||
"msr nzcv, x20"
|
||||
@ -1527,8 +1510,8 @@
|
||||
"stlxrb w3, w2, [x4]",
|
||||
"cbnz w3, #-0xc",
|
||||
"mov w27, w1",
|
||||
"neg w26, w27",
|
||||
"cmp wzr, w27, lsl #24",
|
||||
"neg w26, w27",
|
||||
"mrs x20, nzcv",
|
||||
"eor w20, w20, #0x20000000",
|
||||
"msr nzcv, x20"
|
||||
@ -1543,15 +1526,15 @@
|
||||
"stlxrh w3, w2, [x4]",
|
||||
"cbnz w3, #-0xc",
|
||||
"mov w27, w1",
|
||||
"neg w26, w27",
|
||||
"cmp wzr, w27, lsl #16",
|
||||
"neg w26, w27",
|
||||
"mrs x20, nzcv",
|
||||
"eor w20, w20, #0x20000000",
|
||||
"msr nzcv, x20"
|
||||
]
|
||||
},
|
||||
"lock neg dword [rax]": {
|
||||
"ExpectedInstructionCount": 10,
|
||||
"ExpectedInstructionCount": 9,
|
||||
"Comment": "GROUP2 0xf7 /3",
|
||||
"ExpectedArm64ASM": [
|
||||
"ldaxr w1, [x4]",
|
||||
@ -1559,15 +1542,14 @@
|
||||
"stlxr w3, w2, [x4]",
|
||||
"cbnz w3, #-0xc",
|
||||
"mov w27, w1",
|
||||
"neg w26, w27",
|
||||
"cmp wzr, w27",
|
||||
"negs w26, w27",
|
||||
"mrs x20, nzcv",
|
||||
"eor w20, w20, #0x20000000",
|
||||
"msr nzcv, x20"
|
||||
]
|
||||
},
|
||||
"lock neg qword [rax]": {
|
||||
"ExpectedInstructionCount": 10,
|
||||
"ExpectedInstructionCount": 9,
|
||||
"Comment": "GROUP2 0xf7 /3",
|
||||
"ExpectedArm64ASM": [
|
||||
"ldaxr x1, [x4]",
|
||||
@ -1575,8 +1557,7 @@
|
||||
"stlxr w3, x2, [x4]",
|
||||
"cbnz x3, #-0xc",
|
||||
"mov x27, x1",
|
||||
"neg x26, x27",
|
||||
"cmp xzr, x27",
|
||||
"negs x26, x27",
|
||||
"mrs x20, nzcv",
|
||||
"eor w20, w20, #0x20000000",
|
||||
"msr nzcv, x20"
|
||||
@ -1589,25 +1570,24 @@
|
||||
"mov w20, #0x1",
|
||||
"neg w1, w20",
|
||||
"ldaddalh w1, w27, [x4]",
|
||||
"sub w26, w27, #0x1 (1)",
|
||||
"cset w21, hs",
|
||||
"lsl w0, w27, #16",
|
||||
"cmp w0, w20, lsl #16",
|
||||
"sub w26, w27, #0x1 (1)",
|
||||
"mrs x20, nzcv",
|
||||
"bfi w20, w21, #29, #1",
|
||||
"msr nzcv, x20"
|
||||
]
|
||||
},
|
||||
"lock dec dword [rax]": {
|
||||
"ExpectedInstructionCount": 11,
|
||||
"ExpectedInstructionCount": 10,
|
||||
"Comment": "GROUP4 0xfe /1",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0x1",
|
||||
"neg w1, w20",
|
||||
"ldaddal w1, w27, [x4]",
|
||||
"sub w26, w27, #0x1 (1)",
|
||||
"cset w20, hs",
|
||||
"cmp w27, #0x1 (1)",
|
||||
"subs w26, w27, #0x1 (1)",
|
||||
"mrs x21, nzcv",
|
||||
"mov w0, w21",
|
||||
"bfi w0, w20, #29, #1",
|
||||
@ -1616,15 +1596,14 @@
|
||||
]
|
||||
},
|
||||
"lock dec qword [rax]": {
|
||||
"ExpectedInstructionCount": 11,
|
||||
"ExpectedInstructionCount": 10,
|
||||
"Comment": "GROUP4 0xfe /1",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0x1",
|
||||
"neg x1, x20",
|
||||
"ldaddal x1, x27, [x4]",
|
||||
"sub x26, x27, #0x1 (1)",
|
||||
"cset w20, hs",
|
||||
"cmp x27, #0x1 (1)",
|
||||
"subs x26, x27, #0x1 (1)",
|
||||
"mrs x21, nzcv",
|
||||
"mov w0, w21",
|
||||
"bfi w0, w20, #29, #1",
|
||||
@ -1638,10 +1617,10 @@
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0x1",
|
||||
"ldaddalb w20, w27, [x4]",
|
||||
"add w26, w27, #0x1 (1)",
|
||||
"cset w21, hs",
|
||||
"lsl w0, w27, #24",
|
||||
"cmn w0, w20, lsl #24",
|
||||
"add w26, w27, #0x1 (1)",
|
||||
"mrs x20, nzcv",
|
||||
"bfi w20, w21, #29, #1",
|
||||
"msr nzcv, x20"
|
||||
@ -1653,24 +1632,23 @@
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0x1",
|
||||
"ldaddalh w20, w27, [x4]",
|
||||
"add w26, w27, #0x1 (1)",
|
||||
"cset w21, hs",
|
||||
"lsl w0, w27, #16",
|
||||
"cmn w0, w20, lsl #16",
|
||||
"add w26, w27, #0x1 (1)",
|
||||
"mrs x20, nzcv",
|
||||
"bfi w20, w21, #29, #1",
|
||||
"msr nzcv, x20"
|
||||
]
|
||||
},
|
||||
"lock inc dword [rax]": {
|
||||
"ExpectedInstructionCount": 10,
|
||||
"ExpectedInstructionCount": 9,
|
||||
"Comment": "GROUP4 0xfe /0",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0x1",
|
||||
"ldaddal w20, w27, [x4]",
|
||||
"add w26, w27, #0x1 (1)",
|
||||
"cset w20, hs",
|
||||
"cmn w27, #0x1 (1)",
|
||||
"adds w26, w27, #0x1 (1)",
|
||||
"mrs x21, nzcv",
|
||||
"mov w0, w21",
|
||||
"bfi w0, w20, #29, #1",
|
||||
@ -1679,14 +1657,13 @@
|
||||
]
|
||||
},
|
||||
"lock inc qword [rax]": {
|
||||
"ExpectedInstructionCount": 10,
|
||||
"ExpectedInstructionCount": 9,
|
||||
"Comment": "GROUP4 0xfe /0",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0x1",
|
||||
"ldaddal x20, x27, [x4]",
|
||||
"add x26, x27, #0x1 (1)",
|
||||
"cset w20, hs",
|
||||
"cmn x27, #0x1 (1)",
|
||||
"adds x26, x27, #0x1 (1)",
|
||||
"mrs x21, nzcv",
|
||||
"mov w0, w21",
|
||||
"bfi w0, w20, #29, #1",
|
||||
|
||||
@ -16,10 +16,10 @@
|
||||
"Comment": "0x00",
|
||||
"ExpectedArm64ASM": [
|
||||
"ldaddalb w5, w20, [x4]",
|
||||
"add w26, w20, w5",
|
||||
"eor w27, w20, w5",
|
||||
"lsl w0, w20, #24",
|
||||
"cmn w0, w5, lsl #24"
|
||||
"cmn w0, w5, lsl #24",
|
||||
"add w26, w20, w5"
|
||||
]
|
||||
},
|
||||
"lock add word [rax], cx": {
|
||||
@ -27,20 +27,19 @@
|
||||
"Comment": "0x01",
|
||||
"ExpectedArm64ASM": [
|
||||
"ldaddalh w5, w20, [x4]",
|
||||
"add w26, w20, w5",
|
||||
"eor w27, w20, w5",
|
||||
"lsl w0, w20, #16",
|
||||
"cmn w0, w5, lsl #16"
|
||||
"cmn w0, w5, lsl #16",
|
||||
"add w26, w20, w5"
|
||||
]
|
||||
},
|
||||
"lock add dword [rax], ecx": {
|
||||
"ExpectedInstructionCount": 4,
|
||||
"ExpectedInstructionCount": 3,
|
||||
"Comment": "0x01",
|
||||
"ExpectedArm64ASM": [
|
||||
"ldaddal w5, w20, [x4]",
|
||||
"add w26, w20, w5",
|
||||
"eor w27, w20, w5",
|
||||
"cmn w20, w5"
|
||||
"adds w26, w20, w5"
|
||||
]
|
||||
},
|
||||
"lock or byte [rax], cl": {
|
||||
@ -244,10 +243,10 @@
|
||||
"ExpectedArm64ASM": [
|
||||
"neg w1, w5",
|
||||
"ldaddalb w1, w20, [x4]",
|
||||
"sub w26, w20, w5",
|
||||
"eor w27, w20, w5",
|
||||
"lsl w0, w20, #24",
|
||||
"cmp w0, w5, lsl #24",
|
||||
"sub w26, w20, w5",
|
||||
"cfinv"
|
||||
]
|
||||
},
|
||||
@ -257,22 +256,21 @@
|
||||
"ExpectedArm64ASM": [
|
||||
"neg w1, w5",
|
||||
"ldaddalh w1, w20, [x4]",
|
||||
"sub w26, w20, w5",
|
||||
"eor w27, w20, w5",
|
||||
"lsl w0, w20, #16",
|
||||
"cmp w0, w5, lsl #16",
|
||||
"sub w26, w20, w5",
|
||||
"cfinv"
|
||||
]
|
||||
},
|
||||
"lock sub dword [rax], ecx": {
|
||||
"ExpectedInstructionCount": 6,
|
||||
"ExpectedInstructionCount": 5,
|
||||
"Comment": "0x29",
|
||||
"ExpectedArm64ASM": [
|
||||
"neg w1, w5",
|
||||
"ldaddal w1, w20, [x4]",
|
||||
"sub w26, w20, w5",
|
||||
"eor w27, w20, w5",
|
||||
"cmp w20, w5",
|
||||
"subs w26, w20, w5",
|
||||
"cfinv"
|
||||
]
|
||||
},
|
||||
@ -304,13 +302,12 @@
|
||||
]
|
||||
},
|
||||
"lock add qword [rax], rcx": {
|
||||
"ExpectedInstructionCount": 4,
|
||||
"ExpectedInstructionCount": 3,
|
||||
"Comment": "0x01",
|
||||
"ExpectedArm64ASM": [
|
||||
"ldaddal x5, x20, [x4]",
|
||||
"add x26, x20, x5",
|
||||
"eor w27, w20, w5",
|
||||
"cmn x20, x5"
|
||||
"adds x26, x20, x5"
|
||||
]
|
||||
},
|
||||
"xadd byte [rax], bl": {
|
||||
@ -320,10 +317,10 @@
|
||||
"uxtb w20, w7",
|
||||
"ldaddalb w20, w21, [x4]",
|
||||
"bfxil x7, x21, #0, #8",
|
||||
"add w26, w21, w20",
|
||||
"eor w27, w21, w20",
|
||||
"lsl w0, w21, #24",
|
||||
"cmn w0, w20, lsl #24"
|
||||
"cmn w0, w20, lsl #24",
|
||||
"add w26, w21, w20"
|
||||
]
|
||||
},
|
||||
"xadd word [rax], bx": {
|
||||
@ -333,32 +330,30 @@
|
||||
"uxth w20, w7",
|
||||
"ldaddalh w20, w21, [x4]",
|
||||
"bfxil x7, x21, #0, #16",
|
||||
"add w26, w21, w20",
|
||||
"eor w27, w21, w20",
|
||||
"lsl w0, w21, #16",
|
||||
"cmn w0, w20, lsl #16"
|
||||
"cmn w0, w20, lsl #16",
|
||||
"add w26, w21, w20"
|
||||
]
|
||||
},
|
||||
"xadd dword [rax], ebx": {
|
||||
"ExpectedInstructionCount": 5,
|
||||
"ExpectedInstructionCount": 4,
|
||||
"Comment": "0x0f 0xc1",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, w7",
|
||||
"ldaddal w20, w7, [x4]",
|
||||
"add w26, w7, w20",
|
||||
"eor w27, w7, w20",
|
||||
"cmn w7, w20"
|
||||
"adds w26, w7, w20"
|
||||
]
|
||||
},
|
||||
"xadd qword [rax], rbx": {
|
||||
"ExpectedInstructionCount": 5,
|
||||
"ExpectedInstructionCount": 4,
|
||||
"Comment": "0x0f 0xc1",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x20, x7",
|
||||
"ldaddal x20, x7, [x4]",
|
||||
"add x26, x7, x20",
|
||||
"eor w27, w7, w20",
|
||||
"cmn x7, x20"
|
||||
"adds x26, x7, x20"
|
||||
]
|
||||
},
|
||||
"lock add byte [rax], 1": {
|
||||
@ -367,9 +362,9 @@
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0x1",
|
||||
"ldaddalb w20, w27, [x4]",
|
||||
"add w26, w27, #0x1 (1)",
|
||||
"lsl w0, w27, #24",
|
||||
"cmn w0, w20, lsl #24"
|
||||
"cmn w0, w20, lsl #24",
|
||||
"add w26, w27, #0x1 (1)"
|
||||
]
|
||||
},
|
||||
"lock add byte [rax], 0xFF": {
|
||||
@ -378,10 +373,10 @@
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0xff",
|
||||
"ldaddalb w20, w21, [x4]",
|
||||
"add w26, w21, #0xff (255)",
|
||||
"eor w27, w21, #0xff",
|
||||
"lsl w0, w21, #24",
|
||||
"cmn w0, w20, lsl #24"
|
||||
"cmn w0, w20, lsl #24",
|
||||
"add w26, w21, #0xff (255)"
|
||||
]
|
||||
},
|
||||
"lock add word [rax], 0x100": {
|
||||
@ -390,9 +385,9 @@
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0x100",
|
||||
"ldaddalh w20, w27, [x4]",
|
||||
"add w26, w27, #0x100 (256)",
|
||||
"lsl w0, w27, #16",
|
||||
"cmn w0, w20, lsl #16"
|
||||
"cmn w0, w20, lsl #16",
|
||||
"add w26, w27, #0x100 (256)"
|
||||
]
|
||||
},
|
||||
"lock add word [rax], 0xFFFF": {
|
||||
@ -401,51 +396,47 @@
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0xffff",
|
||||
"ldaddalh w20, w21, [x4]",
|
||||
"add w26, w21, w20",
|
||||
"eor w27, w21, #0xffff",
|
||||
"lsl w0, w21, #16",
|
||||
"cmn w0, w20, lsl #16"
|
||||
"cmn w0, w20, lsl #16",
|
||||
"add w26, w21, w20"
|
||||
]
|
||||
},
|
||||
"lock add dword [rax], 0x100": {
|
||||
"ExpectedInstructionCount": 4,
|
||||
"ExpectedInstructionCount": 3,
|
||||
"Comment": "GROUP1 0x81 /0",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0x100",
|
||||
"ldaddal w20, w27, [x4]",
|
||||
"add w26, w27, #0x100 (256)",
|
||||
"cmn w27, #0x100 (256)"
|
||||
"adds w26, w27, #0x100 (256)"
|
||||
]
|
||||
},
|
||||
"lock add dword [rax], 0xFFFFFFFF": {
|
||||
"ExpectedInstructionCount": 5,
|
||||
"ExpectedInstructionCount": 4,
|
||||
"Comment": "GROUP1 0x81 /0",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0xffffffff",
|
||||
"ldaddal w20, w21, [x4]",
|
||||
"add w26, w21, w20",
|
||||
"eor w27, w21, w20",
|
||||
"cmn w21, w20"
|
||||
"adds w26, w21, w20"
|
||||
]
|
||||
},
|
||||
"lock add qword [rax], 0x100": {
|
||||
"ExpectedInstructionCount": 4,
|
||||
"ExpectedInstructionCount": 3,
|
||||
"Comment": "GROUP1 0x81 /0",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0x100",
|
||||
"ldaddal x20, x27, [x4]",
|
||||
"add x26, x27, #0x100 (256)",
|
||||
"cmn x27, #0x100 (256)"
|
||||
"adds x26, x27, #0x100 (256)"
|
||||
]
|
||||
},
|
||||
"lock add qword [rax], -2147483647": {
|
||||
"ExpectedInstructionCount": 4,
|
||||
"ExpectedInstructionCount": 3,
|
||||
"Comment": "GROUP1 0x81 /0",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x20, #0xffffffff80000001",
|
||||
"ldaddal x20, x27, [x4]",
|
||||
"add x26, x27, x20",
|
||||
"cmn x27, x20"
|
||||
"adds x26, x27, x20"
|
||||
]
|
||||
},
|
||||
"lock add word [rax], 1": {
|
||||
@ -454,29 +445,27 @@
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0x1",
|
||||
"ldaddalh w20, w27, [x4]",
|
||||
"add w26, w27, #0x1 (1)",
|
||||
"lsl w0, w27, #16",
|
||||
"cmn w0, w20, lsl #16"
|
||||
"cmn w0, w20, lsl #16",
|
||||
"add w26, w27, #0x1 (1)"
|
||||
]
|
||||
},
|
||||
"lock add dword [rax], 1": {
|
||||
"ExpectedInstructionCount": 4,
|
||||
"ExpectedInstructionCount": 3,
|
||||
"Comment": "GROUP1 0x83 /0",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0x1",
|
||||
"ldaddal w20, w27, [x4]",
|
||||
"add w26, w27, #0x1 (1)",
|
||||
"cmn w27, #0x1 (1)"
|
||||
"adds w26, w27, #0x1 (1)"
|
||||
]
|
||||
},
|
||||
"lock add qword [rax], 1": {
|
||||
"ExpectedInstructionCount": 4,
|
||||
"ExpectedInstructionCount": 3,
|
||||
"Comment": "GROUP1 0x83 /0",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0x1",
|
||||
"ldaddal x20, x27, [x4]",
|
||||
"add x26, x27, #0x1 (1)",
|
||||
"cmn x27, #0x1 (1)"
|
||||
"adds x26, x27, #0x1 (1)"
|
||||
]
|
||||
},
|
||||
"lock or byte [rax], 1": {
|
||||
@ -1124,9 +1113,9 @@
|
||||
"mov w20, #0x1",
|
||||
"neg w1, w20",
|
||||
"ldaddalb w1, w27, [x4]",
|
||||
"sub w26, w27, #0x1 (1)",
|
||||
"lsl w0, w27, #24",
|
||||
"cmp w0, w20, lsl #24",
|
||||
"sub w26, w27, #0x1 (1)",
|
||||
"cfinv"
|
||||
]
|
||||
},
|
||||
@ -1137,10 +1126,10 @@
|
||||
"mov w20, #0xff",
|
||||
"neg w1, w20",
|
||||
"ldaddalb w1, w21, [x4]",
|
||||
"sub w26, w21, #0xff (255)",
|
||||
"eor w27, w21, #0xff",
|
||||
"lsl w0, w21, #24",
|
||||
"cmp w0, w20, lsl #24",
|
||||
"sub w26, w21, #0xff (255)",
|
||||
"cfinv"
|
||||
]
|
||||
},
|
||||
@ -1151,9 +1140,9 @@
|
||||
"mov w20, #0x100",
|
||||
"neg w1, w20",
|
||||
"ldaddalh w1, w27, [x4]",
|
||||
"sub w26, w27, #0x100 (256)",
|
||||
"lsl w0, w27, #16",
|
||||
"cmp w0, w20, lsl #16",
|
||||
"sub w26, w27, #0x100 (256)",
|
||||
"cfinv"
|
||||
]
|
||||
},
|
||||
@ -1164,59 +1153,55 @@
|
||||
"mov w20, #0xffff",
|
||||
"neg w1, w20",
|
||||
"ldaddalh w1, w21, [x4]",
|
||||
"sub w26, w21, w20",
|
||||
"eor w27, w21, #0xffff",
|
||||
"lsl w0, w21, #16",
|
||||
"cmp w0, w20, lsl #16",
|
||||
"sub w26, w21, w20",
|
||||
"cfinv"
|
||||
]
|
||||
},
|
||||
"lock sub dword [rax], 0x100": {
|
||||
"ExpectedInstructionCount": 6,
|
||||
"ExpectedInstructionCount": 5,
|
||||
"Comment": "GROUP1 0x81 /5",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0x100",
|
||||
"neg w1, w20",
|
||||
"ldaddal w1, w27, [x4]",
|
||||
"sub w26, w27, #0x100 (256)",
|
||||
"cmp w27, #0x100 (256)",
|
||||
"subs w26, w27, #0x100 (256)",
|
||||
"cfinv"
|
||||
]
|
||||
},
|
||||
"lock sub dword [rax], 0xFFFFFFFF": {
|
||||
"ExpectedInstructionCount": 7,
|
||||
"ExpectedInstructionCount": 6,
|
||||
"Comment": "GROUP1 0x81 /5",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0xffffffff",
|
||||
"neg w1, w20",
|
||||
"ldaddal w1, w21, [x4]",
|
||||
"sub w26, w21, w20",
|
||||
"eor w27, w21, w20",
|
||||
"cmp w21, w20",
|
||||
"subs w26, w21, w20",
|
||||
"cfinv"
|
||||
]
|
||||
},
|
||||
"lock sub qword [rax], 0x100": {
|
||||
"ExpectedInstructionCount": 6,
|
||||
"ExpectedInstructionCount": 5,
|
||||
"Comment": "GROUP1 0x81 /5",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0x100",
|
||||
"neg x1, x20",
|
||||
"ldaddal x1, x27, [x4]",
|
||||
"sub x26, x27, #0x100 (256)",
|
||||
"cmp x27, #0x100 (256)",
|
||||
"subs x26, x27, #0x100 (256)",
|
||||
"cfinv"
|
||||
]
|
||||
},
|
||||
"lock sub qword [rax], -2147483647": {
|
||||
"ExpectedInstructionCount": 6,
|
||||
"ExpectedInstructionCount": 5,
|
||||
"Comment": "GROUP1 0x81 /5",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x20, #0xffffffff80000001",
|
||||
"neg x1, x20",
|
||||
"ldaddal x1, x27, [x4]",
|
||||
"sub x26, x27, x20",
|
||||
"cmp x27, x20",
|
||||
"subs x26, x27, x20",
|
||||
"cfinv"
|
||||
]
|
||||
},
|
||||
@ -1227,33 +1212,31 @@
|
||||
"mov w20, #0x1",
|
||||
"neg w1, w20",
|
||||
"ldaddalh w1, w27, [x4]",
|
||||
"sub w26, w27, #0x1 (1)",
|
||||
"lsl w0, w27, #16",
|
||||
"cmp w0, w20, lsl #16",
|
||||
"sub w26, w27, #0x1 (1)",
|
||||
"cfinv"
|
||||
]
|
||||
},
|
||||
"lock sub dword [rax], 1": {
|
||||
"ExpectedInstructionCount": 6,
|
||||
"ExpectedInstructionCount": 5,
|
||||
"Comment": "GROUP1 0x83 /5",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0x1",
|
||||
"neg w1, w20",
|
||||
"ldaddal w1, w27, [x4]",
|
||||
"sub w26, w27, #0x1 (1)",
|
||||
"cmp w27, #0x1 (1)",
|
||||
"subs w26, w27, #0x1 (1)",
|
||||
"cfinv"
|
||||
]
|
||||
},
|
||||
"lock sub qword [rax], 1": {
|
||||
"ExpectedInstructionCount": 6,
|
||||
"ExpectedInstructionCount": 5,
|
||||
"Comment": "GROUP1 0x83 /5",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0x1",
|
||||
"neg x1, x20",
|
||||
"ldaddal x1, x27, [x4]",
|
||||
"sub x26, x27, #0x1 (1)",
|
||||
"cmp x27, #0x1 (1)",
|
||||
"subs x26, x27, #0x1 (1)",
|
||||
"cfinv"
|
||||
]
|
||||
},
|
||||
@ -1374,10 +1357,10 @@
|
||||
"mov w20, #0x1",
|
||||
"neg w1, w20",
|
||||
"ldaddalb w1, w27, [x4]",
|
||||
"sub w26, w27, #0x1 (1)",
|
||||
"cset w21, hs",
|
||||
"lsl w0, w27, #24",
|
||||
"cmp w0, w20, lsl #24",
|
||||
"sub w26, w27, #0x1 (1)",
|
||||
"rmif x21, #63, #nzCv"
|
||||
]
|
||||
},
|
||||
@ -1422,8 +1405,8 @@
|
||||
"stlxrb w3, w2, [x4]",
|
||||
"cbnz w3, #-0xc",
|
||||
"mov w27, w1",
|
||||
"neg w26, w27",
|
||||
"cmp wzr, w27, lsl #24",
|
||||
"neg w26, w27",
|
||||
"cfinv"
|
||||
]
|
||||
},
|
||||
@ -1436,13 +1419,13 @@
|
||||
"stlxrh w3, w2, [x4]",
|
||||
"cbnz w3, #-0xc",
|
||||
"mov w27, w1",
|
||||
"neg w26, w27",
|
||||
"cmp wzr, w27, lsl #16",
|
||||
"neg w26, w27",
|
||||
"cfinv"
|
||||
]
|
||||
},
|
||||
"lock neg dword [rax]": {
|
||||
"ExpectedInstructionCount": 8,
|
||||
"ExpectedInstructionCount": 7,
|
||||
"Comment": "GROUP2 0xf7 /3",
|
||||
"ExpectedArm64ASM": [
|
||||
"ldaxr w1, [x4]",
|
||||
@ -1450,13 +1433,12 @@
|
||||
"stlxr w3, w2, [x4]",
|
||||
"cbnz w3, #-0xc",
|
||||
"mov w27, w1",
|
||||
"neg w26, w27",
|
||||
"cmp wzr, w27",
|
||||
"negs w26, w27",
|
||||
"cfinv"
|
||||
]
|
||||
},
|
||||
"lock neg qword [rax]": {
|
||||
"ExpectedInstructionCount": 8,
|
||||
"ExpectedInstructionCount": 7,
|
||||
"Comment": "GROUP2 0xf7 /3",
|
||||
"ExpectedArm64ASM": [
|
||||
"ldaxr x1, [x4]",
|
||||
@ -1464,8 +1446,7 @@
|
||||
"stlxr w3, x2, [x4]",
|
||||
"cbnz x3, #-0xc",
|
||||
"mov x27, x1",
|
||||
"neg x26, x27",
|
||||
"cmp xzr, x27",
|
||||
"negs x26, x27",
|
||||
"cfinv"
|
||||
]
|
||||
},
|
||||
@ -1476,36 +1457,34 @@
|
||||
"mov w20, #0x1",
|
||||
"neg w1, w20",
|
||||
"ldaddalh w1, w27, [x4]",
|
||||
"sub w26, w27, #0x1 (1)",
|
||||
"cset w21, hs",
|
||||
"lsl w0, w27, #16",
|
||||
"cmp w0, w20, lsl #16",
|
||||
"sub w26, w27, #0x1 (1)",
|
||||
"rmif x21, #63, #nzCv"
|
||||
]
|
||||
},
|
||||
"lock dec dword [rax]": {
|
||||
"ExpectedInstructionCount": 7,
|
||||
"ExpectedInstructionCount": 6,
|
||||
"Comment": "GROUP4 0xfe /1",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0x1",
|
||||
"neg w1, w20",
|
||||
"ldaddal w1, w27, [x4]",
|
||||
"sub w26, w27, #0x1 (1)",
|
||||
"cset w20, hs",
|
||||
"cmp w27, #0x1 (1)",
|
||||
"subs w26, w27, #0x1 (1)",
|
||||
"rmif x20, #63, #nzCv"
|
||||
]
|
||||
},
|
||||
"lock dec qword [rax]": {
|
||||
"ExpectedInstructionCount": 7,
|
||||
"ExpectedInstructionCount": 6,
|
||||
"Comment": "GROUP4 0xfe /1",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0x1",
|
||||
"neg x1, x20",
|
||||
"ldaddal x1, x27, [x4]",
|
||||
"sub x26, x27, #0x1 (1)",
|
||||
"cset w20, hs",
|
||||
"cmp x27, #0x1 (1)",
|
||||
"subs x26, x27, #0x1 (1)",
|
||||
"rmif x20, #63, #nzCv"
|
||||
]
|
||||
},
|
||||
@ -1515,10 +1494,10 @@
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0x1",
|
||||
"ldaddalb w20, w27, [x4]",
|
||||
"add w26, w27, #0x1 (1)",
|
||||
"cset w21, hs",
|
||||
"lsl w0, w27, #24",
|
||||
"cmn w0, w20, lsl #24",
|
||||
"add w26, w27, #0x1 (1)",
|
||||
"rmif x21, #63, #nzCv"
|
||||
]
|
||||
},
|
||||
@ -1528,34 +1507,32 @@
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0x1",
|
||||
"ldaddalh w20, w27, [x4]",
|
||||
"add w26, w27, #0x1 (1)",
|
||||
"cset w21, hs",
|
||||
"lsl w0, w27, #16",
|
||||
"cmn w0, w20, lsl #16",
|
||||
"add w26, w27, #0x1 (1)",
|
||||
"rmif x21, #63, #nzCv"
|
||||
]
|
||||
},
|
||||
"lock inc dword [rax]": {
|
||||
"ExpectedInstructionCount": 6,
|
||||
"ExpectedInstructionCount": 5,
|
||||
"Comment": "GROUP4 0xfe /0",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0x1",
|
||||
"ldaddal w20, w27, [x4]",
|
||||
"add w26, w27, #0x1 (1)",
|
||||
"cset w20, hs",
|
||||
"cmn w27, #0x1 (1)",
|
||||
"adds w26, w27, #0x1 (1)",
|
||||
"rmif x20, #63, #nzCv"
|
||||
]
|
||||
},
|
||||
"lock inc qword [rax]": {
|
||||
"ExpectedInstructionCount": 6,
|
||||
"ExpectedInstructionCount": 5,
|
||||
"Comment": "GROUP4 0xfe /0",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0x1",
|
||||
"ldaddal x20, x27, [x4]",
|
||||
"add x26, x27, #0x1 (1)",
|
||||
"cset w20, hs",
|
||||
"cmn x27, #0x1 (1)",
|
||||
"adds x26, x27, #0x1 (1)",
|
||||
"rmif x20, #63, #nzCv"
|
||||
]
|
||||
}
|
||||
|
||||
@ -11,15 +11,13 @@
|
||||
},
|
||||
"Instructions": {
|
||||
"Chained add": {
|
||||
"ExpectedInstructionCount": 10,
|
||||
"ExpectedInstructionCount": 8,
|
||||
"x86Insts": [
|
||||
"add rax, rbx",
|
||||
"adc rcx, rcx"
|
||||
],
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x20, x4",
|
||||
"add x4, x20, x7",
|
||||
"cmn x20, x7",
|
||||
"adds x4, x4, x7",
|
||||
"mov x20, x5",
|
||||
"cset w21, hs",
|
||||
"add x21, x20, x21",
|
||||
@ -30,15 +28,13 @@
|
||||
]
|
||||
},
|
||||
"Chained sub": {
|
||||
"ExpectedInstructionCount": 13,
|
||||
"ExpectedInstructionCount": 11,
|
||||
"x86Insts": [
|
||||
"sub rax, rbx",
|
||||
"sbb rcx, rdx"
|
||||
],
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x20, x4",
|
||||
"sub x4, x20, x7",
|
||||
"cmp x20, x7",
|
||||
"subs x4, x4, x7",
|
||||
"cfinv",
|
||||
"cset w20, hs",
|
||||
"add x20, x6, x20",
|
||||
@ -52,16 +48,14 @@
|
||||
]
|
||||
},
|
||||
"Inverted add": {
|
||||
"ExpectedInstructionCount": 11,
|
||||
"ExpectedInstructionCount": 9,
|
||||
"x86Insts": [
|
||||
"add rax, rbx",
|
||||
"adc rcx, rdx",
|
||||
"cmc"
|
||||
],
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x20, x4",
|
||||
"add x4, x20, x7",
|
||||
"cmn x20, x7",
|
||||
"adds x4, x4, x7",
|
||||
"cset w20, hs",
|
||||
"add x20, x6, x20",
|
||||
"mov x21, x5",
|
||||
@ -73,16 +67,14 @@
|
||||
]
|
||||
},
|
||||
"Inverted sub": {
|
||||
"ExpectedInstructionCount": 14,
|
||||
"ExpectedInstructionCount": 12,
|
||||
"x86Insts": [
|
||||
"sub rax, rbx",
|
||||
"sbb rcx, rcx",
|
||||
"cmc"
|
||||
],
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x20, x4",
|
||||
"sub x4, x20, x7",
|
||||
"cmp x20, x7",
|
||||
"subs x4, x4, x7",
|
||||
"cfinv",
|
||||
"mov x20, x5",
|
||||
"cset w21, hs",
|
||||
@ -97,22 +89,18 @@
|
||||
]
|
||||
},
|
||||
"INC consumed": {
|
||||
"ExpectedInstructionCount": 10,
|
||||
"ExpectedInstructionCount": 6,
|
||||
"x86Insts": [
|
||||
"add rax, rbx",
|
||||
"inc rax"
|
||||
],
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x20, x4",
|
||||
"add x21, x20, x7",
|
||||
"mov x4, x21",
|
||||
"add x4, x21, #0x1 (1)",
|
||||
"cmn x20, x7",
|
||||
"mov x27, x21",
|
||||
"mov x26, x4",
|
||||
"adds x4, x4, x7",
|
||||
"cset w20, hs",
|
||||
"cmn x21, #0x1 (1)",
|
||||
"rmif x20, #63, #nzCv"
|
||||
"mov x27, x4",
|
||||
"adds x26, x4, #0x1 (1)",
|
||||
"rmif x20, #63, #nzCv",
|
||||
"mov x4, x26"
|
||||
]
|
||||
},
|
||||
"INC dead": {
|
||||
@ -129,23 +117,19 @@
|
||||
]
|
||||
},
|
||||
"DEC consumed": {
|
||||
"ExpectedInstructionCount": 11,
|
||||
"ExpectedInstructionCount": 7,
|
||||
"x86Insts": [
|
||||
"sub rax, rbx",
|
||||
"dec rax"
|
||||
],
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x20, x4",
|
||||
"sub x21, x20, x7",
|
||||
"mov x4, x21",
|
||||
"sub x4, x21, #0x1 (1)",
|
||||
"cmp x20, x7",
|
||||
"subs x4, x4, x7",
|
||||
"cfinv",
|
||||
"mov x27, x21",
|
||||
"mov x26, x4",
|
||||
"cset w20, hs",
|
||||
"cmp x21, #0x1 (1)",
|
||||
"rmif x20, #63, #nzCv"
|
||||
"mov x27, x4",
|
||||
"subs x26, x4, #0x1 (1)",
|
||||
"rmif x20, #63, #nzCv",
|
||||
"mov x4, x26"
|
||||
]
|
||||
},
|
||||
"DEC dead": {
|
||||
@ -205,7 +189,7 @@
|
||||
"test cl, cl"
|
||||
],
|
||||
"ExpectedArm64ASM": [
|
||||
"cmp x4, x7",
|
||||
"subs x20, x4, x7",
|
||||
"cset x20, eq",
|
||||
"bfxil x5, x20, #0, #8",
|
||||
"mov x26, x5",
|
||||
@ -213,16 +197,14 @@
|
||||
]
|
||||
},
|
||||
"Partial NZCV select (add)": {
|
||||
"ExpectedInstructionCount": 7,
|
||||
"ExpectedInstructionCount": 5,
|
||||
"x86Insts": [
|
||||
"add rax, rbx",
|
||||
"setz cl",
|
||||
"test cl, cl"
|
||||
],
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x20, x4",
|
||||
"add x4, x20, x7",
|
||||
"cmn x20, x7",
|
||||
"adds x4, x4, x7",
|
||||
"cset x20, eq",
|
||||
"bfxil x5, x20, #0, #8",
|
||||
"mov x26, x5",
|
||||
|
||||
@ -13,7 +13,7 @@
|
||||
},
|
||||
"Instructions": {
|
||||
"The Witcher 3": {
|
||||
"ExpectedInstructionCount": 11,
|
||||
"ExpectedInstructionCount": 9,
|
||||
"x86Insts": [
|
||||
"mov eax, 0x1",
|
||||
"lock xadd qword [rcx], rax",
|
||||
@ -29,16 +29,14 @@
|
||||
"mov x6, x4",
|
||||
"and w6, w4, #0x1f",
|
||||
"add x6, x6, #0x1 (1)",
|
||||
"lsl x20, x6, #6",
|
||||
"mov x6, x20",
|
||||
"add x6, x20, x5",
|
||||
"eor w27, w20, w5",
|
||||
"mov x26, x6",
|
||||
"cmn x20, x5"
|
||||
"lsl x6, x6, #6",
|
||||
"eor w27, w6, w5",
|
||||
"adds x26, x6, x5",
|
||||
"mov x6, x26"
|
||||
]
|
||||
},
|
||||
"FMOD scalar loop": {
|
||||
"ExpectedInstructionCount": 90,
|
||||
"ExpectedInstructionCount": 88,
|
||||
"x86Insts": [
|
||||
"mov esi, ecx",
|
||||
"mov rdx, rbp",
|
||||
@ -80,8 +78,7 @@
|
||||
"sub esi, 0x1"
|
||||
],
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, w5",
|
||||
"mov x10, x20",
|
||||
"mov w10, w5",
|
||||
"mov x6, x9",
|
||||
"mov x4, x7",
|
||||
"ldr s18, [x6]",
|
||||
@ -89,91 +86,90 @@
|
||||
"fmul s0, s18, s16",
|
||||
"mov v18.s[0], v0.s[0]",
|
||||
"add x6, x6, #0x20 (32)",
|
||||
"sub x21, x4, #0x20 (32)",
|
||||
"ldr s2, [x21]",
|
||||
"sub x20, x4, #0x20 (32)",
|
||||
"ldr s2, [x20]",
|
||||
"fadd s0, s18, s2",
|
||||
"mov v18.s[0], v0.s[0]",
|
||||
"sub x21, x4, #0x20 (32)",
|
||||
"str s18, [x21]",
|
||||
"sub x21, x6, #0x1c (28)",
|
||||
"ldr s18, [x21]",
|
||||
"sub x20, x4, #0x20 (32)",
|
||||
"str s18, [x20]",
|
||||
"sub x20, x6, #0x1c (28)",
|
||||
"ldr s18, [x20]",
|
||||
"fmul s0, s18, s17",
|
||||
"mov v18.s[0], v0.s[0]",
|
||||
"sub x21, x4, #0x1c (28)",
|
||||
"ldr s2, [x21]",
|
||||
"sub x20, x4, #0x1c (28)",
|
||||
"ldr s2, [x20]",
|
||||
"fadd s0, s18, s2",
|
||||
"mov v18.s[0], v0.s[0]",
|
||||
"sub x21, x4, #0x1c (28)",
|
||||
"str s18, [x21]",
|
||||
"sub x21, x6, #0x18 (24)",
|
||||
"ldr s18, [x21]",
|
||||
"sub x20, x4, #0x1c (28)",
|
||||
"str s18, [x20]",
|
||||
"sub x20, x6, #0x18 (24)",
|
||||
"ldr s18, [x20]",
|
||||
"fmul s0, s18, s16",
|
||||
"mov v18.s[0], v0.s[0]",
|
||||
"sub x21, x4, #0x18 (24)",
|
||||
"ldr s2, [x21]",
|
||||
"sub x20, x4, #0x18 (24)",
|
||||
"ldr s2, [x20]",
|
||||
"fadd s0, s18, s2",
|
||||
"mov v18.s[0], v0.s[0]",
|
||||
"sub x21, x4, #0x18 (24)",
|
||||
"str s18, [x21]",
|
||||
"sub x21, x6, #0x14 (20)",
|
||||
"ldr s18, [x21]",
|
||||
"sub x20, x4, #0x18 (24)",
|
||||
"str s18, [x20]",
|
||||
"sub x20, x6, #0x14 (20)",
|
||||
"ldr s18, [x20]",
|
||||
"fmul s0, s18, s17",
|
||||
"mov v18.s[0], v0.s[0]",
|
||||
"sub x21, x4, #0x14 (20)",
|
||||
"ldr s2, [x21]",
|
||||
"sub x20, x4, #0x14 (20)",
|
||||
"ldr s2, [x20]",
|
||||
"fadd s0, s18, s2",
|
||||
"mov v18.s[0], v0.s[0]",
|
||||
"sub x21, x4, #0x14 (20)",
|
||||
"str s18, [x21]",
|
||||
"sub x21, x6, #0x10 (16)",
|
||||
"ldr s18, [x21]",
|
||||
"sub x20, x4, #0x14 (20)",
|
||||
"str s18, [x20]",
|
||||
"sub x20, x6, #0x10 (16)",
|
||||
"ldr s18, [x20]",
|
||||
"fmul s0, s18, s16",
|
||||
"mov v18.s[0], v0.s[0]",
|
||||
"sub x21, x4, #0x10 (16)",
|
||||
"ldr s2, [x21]",
|
||||
"sub x20, x4, #0x10 (16)",
|
||||
"ldr s2, [x20]",
|
||||
"fadd s0, s18, s2",
|
||||
"mov v18.s[0], v0.s[0]",
|
||||
"sub x21, x4, #0x10 (16)",
|
||||
"str s18, [x21]",
|
||||
"sub x21, x6, #0xc (12)",
|
||||
"ldr s18, [x21]",
|
||||
"sub x20, x4, #0x10 (16)",
|
||||
"str s18, [x20]",
|
||||
"sub x20, x6, #0xc (12)",
|
||||
"ldr s18, [x20]",
|
||||
"fmul s0, s18, s17",
|
||||
"mov v18.s[0], v0.s[0]",
|
||||
"sub x21, x4, #0xc (12)",
|
||||
"ldr s2, [x21]",
|
||||
"sub x20, x4, #0xc (12)",
|
||||
"ldr s2, [x20]",
|
||||
"fadd s0, s18, s2",
|
||||
"mov v18.s[0], v0.s[0]",
|
||||
"sub x21, x4, #0xc (12)",
|
||||
"str s18, [x21]",
|
||||
"sub x21, x6, #0x8 (8)",
|
||||
"ldr s18, [x21]",
|
||||
"sub x20, x4, #0xc (12)",
|
||||
"str s18, [x20]",
|
||||
"sub x20, x6, #0x8 (8)",
|
||||
"ldr s18, [x20]",
|
||||
"fmul s0, s18, s16",
|
||||
"mov v18.s[0], v0.s[0]",
|
||||
"sub x21, x4, #0x8 (8)",
|
||||
"ldr s2, [x21]",
|
||||
"sub x20, x4, #0x8 (8)",
|
||||
"ldr s2, [x20]",
|
||||
"fadd s0, s18, s2",
|
||||
"mov v18.s[0], v0.s[0]",
|
||||
"sub x21, x4, #0x8 (8)",
|
||||
"str s18, [x21]",
|
||||
"sub x21, x6, #0x4 (4)",
|
||||
"ldr s18, [x21]",
|
||||
"sub x20, x4, #0x8 (8)",
|
||||
"str s18, [x20]",
|
||||
"sub x20, x6, #0x4 (4)",
|
||||
"ldr s18, [x20]",
|
||||
"fmul s0, s18, s17",
|
||||
"mov v18.s[0], v0.s[0]",
|
||||
"sub x21, x4, #0x4 (4)",
|
||||
"ldr s2, [x21]",
|
||||
"sub x20, x4, #0x4 (4)",
|
||||
"ldr s2, [x20]",
|
||||
"fadd s0, s18, s2",
|
||||
"mov v18.s[0], v0.s[0]",
|
||||
"sub x21, x4, #0x4 (4)",
|
||||
"str s18, [x21]",
|
||||
"sub w10, w20, #0x1 (1)",
|
||||
"mov x27, x20",
|
||||
"mov x26, x10",
|
||||
"cmp w20, #0x1 (1)",
|
||||
"cfinv"
|
||||
"sub x20, x4, #0x4 (4)",
|
||||
"str s18, [x20]",
|
||||
"mov x27, x10",
|
||||
"subs w26, w10, #0x1 (1)",
|
||||
"cfinv",
|
||||
"mov x10, x26"
|
||||
]
|
||||
},
|
||||
"Scalar vector add loop": {
|
||||
"ExpectedInstructionCount": 10,
|
||||
"ExpectedInstructionCount": 9,
|
||||
"Comment": [
|
||||
"Saw this in bytemark"
|
||||
],
|
||||
@ -191,14 +187,13 @@
|
||||
"add x20, x16, x4",
|
||||
"str q16, [x20]",
|
||||
"add x4, x4, #0x10 (16)",
|
||||
"sub x26, x10, x4",
|
||||
"eor w27, w10, w4",
|
||||
"cmp x10, x4",
|
||||
"subs x26, x10, x4",
|
||||
"cfinv"
|
||||
]
|
||||
},
|
||||
"bytemark data xor loop": {
|
||||
"ExpectedInstructionCount": 17,
|
||||
"ExpectedInstructionCount": 16,
|
||||
"Comment": [
|
||||
"Saw this in bytemark"
|
||||
],
|
||||
@ -227,9 +222,8 @@
|
||||
"eor x20, x20, x19",
|
||||
"add x21, x7, x6, lsl #3",
|
||||
"str x20, [x21]",
|
||||
"sub x26, x11, x4",
|
||||
"eor w27, w11, w4",
|
||||
"cmp x11, x4",
|
||||
"subs x26, x11, x4",
|
||||
"cfinv"
|
||||
]
|
||||
}
|
||||
|
||||
@ -12,7 +12,7 @@
|
||||
},
|
||||
"Instructions": {
|
||||
"Sonic Mania movie player": {
|
||||
"ExpectedInstructionCount": 18,
|
||||
"ExpectedInstructionCount": 17,
|
||||
"Comment": "Used to be hottest block in Sonic Mania",
|
||||
"x86Insts": [
|
||||
"movzx edx, byte [esi+ecx]",
|
||||
@ -41,14 +41,13 @@
|
||||
"orr w20, w20, w6",
|
||||
"str w20, [x4]",
|
||||
"add w4, w4, #0x4 (4)",
|
||||
"sub w26, w10, w7",
|
||||
"eor w27, w10, w7",
|
||||
"cmp w10, w7",
|
||||
"subs w26, w10, w7",
|
||||
"cfinv"
|
||||
]
|
||||
},
|
||||
"wine mscrt.dll memmove": {
|
||||
"ExpectedInstructionCount": 21,
|
||||
"ExpectedInstructionCount": 20,
|
||||
"Comment": "Hot in Sonic Mania",
|
||||
"x86Insts": [
|
||||
"movdqu xmm0, [esi]",
|
||||
@ -82,9 +81,8 @@
|
||||
"add w10, w10, #0x40 (64)",
|
||||
"add w11, w11, #0x40 (64)",
|
||||
"sub w5, w5, #0x40 (64)",
|
||||
"sub w26, w5, #0x40 (64)",
|
||||
"mov w27, w5",
|
||||
"cmp w5, #0x40 (64)",
|
||||
"subs w26, w5, #0x40 (64)",
|
||||
"cfinv"
|
||||
]
|
||||
}
|
||||
|
||||
@ -13,7 +13,7 @@
|
||||
},
|
||||
"Instructions": {
|
||||
"FMOD scalar loop": {
|
||||
"ExpectedInstructionCount": 74,
|
||||
"ExpectedInstructionCount": 72,
|
||||
"x86Insts": [
|
||||
"mov esi, ecx",
|
||||
"mov rdx, rbp",
|
||||
@ -55,80 +55,78 @@
|
||||
"sub esi, 0x1"
|
||||
],
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, w5",
|
||||
"mov x10, x20",
|
||||
"mov w10, w5",
|
||||
"mov x6, x9",
|
||||
"mov x4, x7",
|
||||
"ldr s18, [x6]",
|
||||
"add x4, x4, #0x20 (32)",
|
||||
"fmul s18, s18, s16",
|
||||
"add x6, x6, #0x20 (32)",
|
||||
"sub x21, x4, #0x20 (32)",
|
||||
"ldr s2, [x21]",
|
||||
"sub x20, x4, #0x20 (32)",
|
||||
"ldr s2, [x20]",
|
||||
"fadd s18, s18, s2",
|
||||
"sub x21, x4, #0x20 (32)",
|
||||
"str s18, [x21]",
|
||||
"sub x21, x6, #0x1c (28)",
|
||||
"ldr s18, [x21]",
|
||||
"sub x20, x4, #0x20 (32)",
|
||||
"str s18, [x20]",
|
||||
"sub x20, x6, #0x1c (28)",
|
||||
"ldr s18, [x20]",
|
||||
"fmul s18, s18, s17",
|
||||
"sub x21, x4, #0x1c (28)",
|
||||
"ldr s2, [x21]",
|
||||
"sub x20, x4, #0x1c (28)",
|
||||
"ldr s2, [x20]",
|
||||
"fadd s18, s18, s2",
|
||||
"sub x21, x4, #0x1c (28)",
|
||||
"str s18, [x21]",
|
||||
"sub x21, x6, #0x18 (24)",
|
||||
"ldr s18, [x21]",
|
||||
"sub x20, x4, #0x1c (28)",
|
||||
"str s18, [x20]",
|
||||
"sub x20, x6, #0x18 (24)",
|
||||
"ldr s18, [x20]",
|
||||
"fmul s18, s18, s16",
|
||||
"sub x21, x4, #0x18 (24)",
|
||||
"ldr s2, [x21]",
|
||||
"sub x20, x4, #0x18 (24)",
|
||||
"ldr s2, [x20]",
|
||||
"fadd s18, s18, s2",
|
||||
"sub x21, x4, #0x18 (24)",
|
||||
"str s18, [x21]",
|
||||
"sub x21, x6, #0x14 (20)",
|
||||
"ldr s18, [x21]",
|
||||
"sub x20, x4, #0x18 (24)",
|
||||
"str s18, [x20]",
|
||||
"sub x20, x6, #0x14 (20)",
|
||||
"ldr s18, [x20]",
|
||||
"fmul s18, s18, s17",
|
||||
"sub x21, x4, #0x14 (20)",
|
||||
"ldr s2, [x21]",
|
||||
"sub x20, x4, #0x14 (20)",
|
||||
"ldr s2, [x20]",
|
||||
"fadd s18, s18, s2",
|
||||
"sub x21, x4, #0x14 (20)",
|
||||
"str s18, [x21]",
|
||||
"sub x21, x6, #0x10 (16)",
|
||||
"ldr s18, [x21]",
|
||||
"sub x20, x4, #0x14 (20)",
|
||||
"str s18, [x20]",
|
||||
"sub x20, x6, #0x10 (16)",
|
||||
"ldr s18, [x20]",
|
||||
"fmul s18, s18, s16",
|
||||
"sub x21, x4, #0x10 (16)",
|
||||
"ldr s2, [x21]",
|
||||
"sub x20, x4, #0x10 (16)",
|
||||
"ldr s2, [x20]",
|
||||
"fadd s18, s18, s2",
|
||||
"sub x21, x4, #0x10 (16)",
|
||||
"str s18, [x21]",
|
||||
"sub x21, x6, #0xc (12)",
|
||||
"ldr s18, [x21]",
|
||||
"sub x20, x4, #0x10 (16)",
|
||||
"str s18, [x20]",
|
||||
"sub x20, x6, #0xc (12)",
|
||||
"ldr s18, [x20]",
|
||||
"fmul s18, s18, s17",
|
||||
"sub x21, x4, #0xc (12)",
|
||||
"ldr s2, [x21]",
|
||||
"sub x20, x4, #0xc (12)",
|
||||
"ldr s2, [x20]",
|
||||
"fadd s18, s18, s2",
|
||||
"sub x21, x4, #0xc (12)",
|
||||
"str s18, [x21]",
|
||||
"sub x21, x6, #0x8 (8)",
|
||||
"ldr s18, [x21]",
|
||||
"sub x20, x4, #0xc (12)",
|
||||
"str s18, [x20]",
|
||||
"sub x20, x6, #0x8 (8)",
|
||||
"ldr s18, [x20]",
|
||||
"fmul s18, s18, s16",
|
||||
"sub x21, x4, #0x8 (8)",
|
||||
"ldr s2, [x21]",
|
||||
"sub x20, x4, #0x8 (8)",
|
||||
"ldr s2, [x20]",
|
||||
"fadd s18, s18, s2",
|
||||
"sub x21, x4, #0x8 (8)",
|
||||
"str s18, [x21]",
|
||||
"sub x21, x6, #0x4 (4)",
|
||||
"ldr s18, [x21]",
|
||||
"sub x20, x4, #0x8 (8)",
|
||||
"str s18, [x20]",
|
||||
"sub x20, x6, #0x4 (4)",
|
||||
"ldr s18, [x20]",
|
||||
"fmul s18, s18, s17",
|
||||
"sub x21, x4, #0x4 (4)",
|
||||
"ldr s2, [x21]",
|
||||
"sub x20, x4, #0x4 (4)",
|
||||
"ldr s2, [x20]",
|
||||
"fadd s18, s18, s2",
|
||||
"sub x21, x4, #0x4 (4)",
|
||||
"str s18, [x21]",
|
||||
"sub w10, w20, #0x1 (1)",
|
||||
"mov x27, x20",
|
||||
"mov x26, x10",
|
||||
"cmp w20, #0x1 (1)",
|
||||
"cfinv"
|
||||
"sub x20, x4, #0x4 (4)",
|
||||
"str s18, [x20]",
|
||||
"mov x27, x10",
|
||||
"subs w26, w10, #0x1 (1)",
|
||||
"cfinv",
|
||||
"mov x10, x26"
|
||||
]
|
||||
}
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -17,11 +17,11 @@
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0x1",
|
||||
"mov x27, x4",
|
||||
"lsl w0, w27, #24",
|
||||
"cmn w0, w20, lsl #24",
|
||||
"add w26, w27, #0x1 (1)",
|
||||
"mov x4, x27",
|
||||
"bfxil x4, x26, #0, #8",
|
||||
"lsl w0, w27, #24",
|
||||
"cmn w0, w20, lsl #24"
|
||||
"bfxil x4, x26, #0, #8"
|
||||
]
|
||||
},
|
||||
"or al, 1": {
|
||||
@ -98,12 +98,12 @@
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0x1",
|
||||
"mov x27, x4",
|
||||
"sub w26, w27, #0x1 (1)",
|
||||
"mov x4, x27",
|
||||
"bfxil x4, x26, #0, #8",
|
||||
"lsl w0, w27, #24",
|
||||
"cmp w0, w20, lsl #24",
|
||||
"cfinv"
|
||||
"sub w26, w27, #0x1 (1)",
|
||||
"cfinv",
|
||||
"mov x4, x27",
|
||||
"bfxil x4, x26, #0, #8"
|
||||
]
|
||||
},
|
||||
"xor al, 1": {
|
||||
@ -121,24 +121,22 @@
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0x1",
|
||||
"mov x27, x4",
|
||||
"sub w26, w27, #0x1 (1)",
|
||||
"lsl w0, w27, #24",
|
||||
"cmp w0, w20, lsl #24",
|
||||
"sub w26, w27, #0x1 (1)",
|
||||
"cfinv"
|
||||
]
|
||||
},
|
||||
"add al, -1": {
|
||||
"ExpectedInstructionCount": 8,
|
||||
"ExpectedInstructionCount": 6,
|
||||
"Comment": "GROUP1 0x80 /0",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0xff",
|
||||
"mov x21, x4",
|
||||
"add w26, w21, #0xff (255)",
|
||||
"mov x4, x21",
|
||||
"bfxil x4, x26, #0, #8",
|
||||
"eor w27, w21, #0xff",
|
||||
"lsl w0, w21, #24",
|
||||
"cmn w0, w20, lsl #24"
|
||||
"eor w27, w4, #0xff",
|
||||
"lsl w0, w4, #24",
|
||||
"cmn w0, w20, lsl #24",
|
||||
"add w26, w4, #0xff (255)",
|
||||
"bfxil x4, x26, #0, #8"
|
||||
]
|
||||
},
|
||||
"or al, -1": {
|
||||
@ -212,18 +210,16 @@
|
||||
]
|
||||
},
|
||||
"sub al, -1": {
|
||||
"ExpectedInstructionCount": 9,
|
||||
"ExpectedInstructionCount": 7,
|
||||
"Comment": "GROUP1 0x80 /5",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0xff",
|
||||
"mov x21, x4",
|
||||
"sub w26, w21, #0xff (255)",
|
||||
"mov x4, x21",
|
||||
"bfxil x4, x26, #0, #8",
|
||||
"eor w27, w21, #0xff",
|
||||
"lsl w0, w21, #24",
|
||||
"eor w27, w4, #0xff",
|
||||
"lsl w0, w4, #24",
|
||||
"cmp w0, w20, lsl #24",
|
||||
"cfinv"
|
||||
"sub w26, w4, #0xff (255)",
|
||||
"cfinv",
|
||||
"bfxil x4, x26, #0, #8"
|
||||
]
|
||||
},
|
||||
"xor al, -1": {
|
||||
@ -240,10 +236,10 @@
|
||||
"Comment": "GROUP1 0x80 /7",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0xff",
|
||||
"sub w26, w4, #0xff (255)",
|
||||
"eor w27, w4, #0xff",
|
||||
"lsl w0, w4, #24",
|
||||
"cmp w0, w20, lsl #24",
|
||||
"sub w26, w4, #0xff (255)",
|
||||
"cfinv"
|
||||
]
|
||||
},
|
||||
@ -253,31 +249,29 @@
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0x100",
|
||||
"mov x27, x4",
|
||||
"lsl w0, w27, #16",
|
||||
"cmn w0, w20, lsl #16",
|
||||
"add w26, w27, #0x100 (256)",
|
||||
"mov x4, x27",
|
||||
"bfxil x4, x26, #0, #16",
|
||||
"lsl w0, w27, #16",
|
||||
"cmn w0, w20, lsl #16"
|
||||
"bfxil x4, x26, #0, #16"
|
||||
]
|
||||
},
|
||||
"add eax, 256": {
|
||||
"ExpectedInstructionCount": 4,
|
||||
"ExpectedInstructionCount": 3,
|
||||
"Comment": "GROUP1 0x81 /0",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x27, x4",
|
||||
"add w4, w27, #0x100 (256)",
|
||||
"mov x26, x4",
|
||||
"cmn w27, #0x100 (256)"
|
||||
"adds w26, w27, #0x100 (256)",
|
||||
"mov x4, x26"
|
||||
]
|
||||
},
|
||||
"add rax, 256": {
|
||||
"ExpectedInstructionCount": 4,
|
||||
"ExpectedInstructionCount": 3,
|
||||
"Comment": "GROUP1 0x81 /0",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x27, x4",
|
||||
"add x4, x27, #0x100 (256)",
|
||||
"mov x26, x4",
|
||||
"cmn x27, #0x100 (256)"
|
||||
"adds x26, x27, #0x100 (256)",
|
||||
"mov x4, x26"
|
||||
]
|
||||
},
|
||||
"or eax, 256": {
|
||||
@ -358,38 +352,36 @@
|
||||
"ExpectedInstructionCount": 2,
|
||||
"Comment": "GROUP1 0x81 /4",
|
||||
"ExpectedArm64ASM": [
|
||||
"ands w4, w4, #0x100",
|
||||
"mov x26, x4"
|
||||
"ands w26, w4, #0x100",
|
||||
"mov x4, x26"
|
||||
]
|
||||
},
|
||||
"and rax, 256": {
|
||||
"ExpectedInstructionCount": 2,
|
||||
"Comment": "GROUP1 0x81 /4",
|
||||
"ExpectedArm64ASM": [
|
||||
"ands x4, x4, #0x100",
|
||||
"mov x26, x4"
|
||||
"ands x26, x4, #0x100",
|
||||
"mov x4, x26"
|
||||
]
|
||||
},
|
||||
"sub eax, 256": {
|
||||
"ExpectedInstructionCount": 5,
|
||||
"ExpectedInstructionCount": 4,
|
||||
"Comment": "GROUP1 0x81 /5",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x27, x4",
|
||||
"sub w4, w27, #0x100 (256)",
|
||||
"mov x26, x4",
|
||||
"cmp w27, #0x100 (256)",
|
||||
"cfinv"
|
||||
"subs w26, w27, #0x100 (256)",
|
||||
"cfinv",
|
||||
"mov x4, x26"
|
||||
]
|
||||
},
|
||||
"sub rax, 256": {
|
||||
"ExpectedInstructionCount": 5,
|
||||
"ExpectedInstructionCount": 4,
|
||||
"Comment": "GROUP1 0x81 /5",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x27, x4",
|
||||
"sub x4, x27, #0x100 (256)",
|
||||
"mov x26, x4",
|
||||
"cmp x27, #0x100 (256)",
|
||||
"cfinv"
|
||||
"subs x26, x27, #0x100 (256)",
|
||||
"cfinv",
|
||||
"mov x4, x26"
|
||||
]
|
||||
},
|
||||
"xor eax, 256": {
|
||||
@ -411,22 +403,20 @@
|
||||
]
|
||||
},
|
||||
"cmp eax, 256": {
|
||||
"ExpectedInstructionCount": 4,
|
||||
"ExpectedInstructionCount": 3,
|
||||
"Comment": "GROUP1 0x81 /7",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x27, x4",
|
||||
"sub w26, w27, #0x100 (256)",
|
||||
"cmp w27, #0x100 (256)",
|
||||
"subs w26, w27, #0x100 (256)",
|
||||
"cfinv"
|
||||
]
|
||||
},
|
||||
"cmp rax, 256": {
|
||||
"ExpectedInstructionCount": 4,
|
||||
"ExpectedInstructionCount": 3,
|
||||
"Comment": "GROUP1 0x81 /7",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x27, x4",
|
||||
"sub x26, x27, #0x100 (256)",
|
||||
"cmp x27, #0x100 (256)",
|
||||
"subs x26, x27, #0x100 (256)",
|
||||
"cfinv"
|
||||
]
|
||||
},
|
||||
@ -436,33 +426,31 @@
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0xff00",
|
||||
"mov x27, x4",
|
||||
"lsl w0, w27, #16",
|
||||
"cmn w0, w20, lsl #16",
|
||||
"add w26, w27, w20",
|
||||
"mov x4, x27",
|
||||
"bfxil x4, x26, #0, #16",
|
||||
"lsl w0, w27, #16",
|
||||
"cmn w0, w20, lsl #16"
|
||||
"bfxil x4, x26, #0, #16"
|
||||
]
|
||||
},
|
||||
"add eax, -256": {
|
||||
"ExpectedInstructionCount": 5,
|
||||
"ExpectedInstructionCount": 4,
|
||||
"Comment": "GROUP1 0x81 /0",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0xffffff00",
|
||||
"mov x27, x4",
|
||||
"add w4, w27, w20",
|
||||
"mov x26, x4",
|
||||
"cmn w27, w20"
|
||||
"adds w26, w27, w20",
|
||||
"mov x4, x26"
|
||||
]
|
||||
},
|
||||
"add rax, -256": {
|
||||
"ExpectedInstructionCount": 5,
|
||||
"ExpectedInstructionCount": 4,
|
||||
"Comment": "GROUP1 0x81 /0",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x20, #0xffffffffffffff00",
|
||||
"mov x27, x4",
|
||||
"sub x4, x27, #0x100 (256)",
|
||||
"mov x26, x4",
|
||||
"cmn x27, x20"
|
||||
"adds x26, x27, x20",
|
||||
"mov x4, x26"
|
||||
]
|
||||
},
|
||||
"or eax, -256": {
|
||||
@ -543,40 +531,38 @@
|
||||
"ExpectedInstructionCount": 2,
|
||||
"Comment": "GROUP1 0x81 /4",
|
||||
"ExpectedArm64ASM": [
|
||||
"ands w4, w4, #0xffffff00",
|
||||
"mov x26, x4"
|
||||
"ands w26, w4, #0xffffff00",
|
||||
"mov x4, x26"
|
||||
]
|
||||
},
|
||||
"and rax, -256": {
|
||||
"ExpectedInstructionCount": 2,
|
||||
"Comment": "GROUP1 0x81 /4",
|
||||
"ExpectedArm64ASM": [
|
||||
"ands x4, x4, #0xffffffffffffff00",
|
||||
"mov x26, x4"
|
||||
"ands x26, x4, #0xffffffffffffff00",
|
||||
"mov x4, x26"
|
||||
]
|
||||
},
|
||||
"sub eax, -256": {
|
||||
"ExpectedInstructionCount": 6,
|
||||
"ExpectedInstructionCount": 5,
|
||||
"Comment": "GROUP1 0x81 /5",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0xffffff00",
|
||||
"mov x27, x4",
|
||||
"sub w4, w27, w20",
|
||||
"mov x26, x4",
|
||||
"cmp w27, w20",
|
||||
"cfinv"
|
||||
"subs w26, w27, w20",
|
||||
"cfinv",
|
||||
"mov x4, x26"
|
||||
]
|
||||
},
|
||||
"sub rax, -256": {
|
||||
"ExpectedInstructionCount": 6,
|
||||
"ExpectedInstructionCount": 5,
|
||||
"Comment": "GROUP1 0x81 /5",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x20, #0xffffffffffffff00",
|
||||
"mov x27, x4",
|
||||
"sub x4, x27, x20",
|
||||
"mov x26, x4",
|
||||
"cmp x27, x20",
|
||||
"cfinv"
|
||||
"subs x26, x27, x20",
|
||||
"cfinv",
|
||||
"mov x4, x26"
|
||||
]
|
||||
},
|
||||
"xor eax, -256": {
|
||||
@ -598,24 +584,22 @@
|
||||
]
|
||||
},
|
||||
"cmp eax, -256": {
|
||||
"ExpectedInstructionCount": 5,
|
||||
"ExpectedInstructionCount": 4,
|
||||
"Comment": "GROUP1 0x81 /7",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0xffffff00",
|
||||
"mov x27, x4",
|
||||
"sub w26, w27, w20",
|
||||
"cmp w27, w20",
|
||||
"subs w26, w27, w20",
|
||||
"cfinv"
|
||||
]
|
||||
},
|
||||
"cmp rax, -256": {
|
||||
"ExpectedInstructionCount": 5,
|
||||
"ExpectedInstructionCount": 4,
|
||||
"Comment": "GROUP1 0x81 /7",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x20, #0xffffffffffffff00",
|
||||
"mov x27, x4",
|
||||
"sub x26, x27, x20",
|
||||
"cmp x27, x20",
|
||||
"subs x26, x27, x20",
|
||||
"cfinv"
|
||||
]
|
||||
},
|
||||
@ -625,31 +609,29 @@
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0x1",
|
||||
"mov x27, x4",
|
||||
"lsl w0, w27, #16",
|
||||
"cmn w0, w20, lsl #16",
|
||||
"add w26, w27, #0x1 (1)",
|
||||
"mov x4, x27",
|
||||
"bfxil x4, x26, #0, #16",
|
||||
"lsl w0, w27, #16",
|
||||
"cmn w0, w20, lsl #16"
|
||||
"bfxil x4, x26, #0, #16"
|
||||
]
|
||||
},
|
||||
"add eax, 1": {
|
||||
"ExpectedInstructionCount": 4,
|
||||
"ExpectedInstructionCount": 3,
|
||||
"Comment": "GROUP1 0x83 /0",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x27, x4",
|
||||
"add w4, w27, #0x1 (1)",
|
||||
"mov x26, x4",
|
||||
"cmn w27, #0x1 (1)"
|
||||
"adds w26, w27, #0x1 (1)",
|
||||
"mov x4, x26"
|
||||
]
|
||||
},
|
||||
"add rax, 1": {
|
||||
"ExpectedInstructionCount": 4,
|
||||
"ExpectedInstructionCount": 3,
|
||||
"Comment": "GROUP1 0x83 /0",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x27, x4",
|
||||
"add x4, x27, #0x1 (1)",
|
||||
"mov x26, x4",
|
||||
"cmn x27, #0x1 (1)"
|
||||
"adds x26, x27, #0x1 (1)",
|
||||
"mov x4, x26"
|
||||
]
|
||||
},
|
||||
"or eax, 1": {
|
||||
@ -730,38 +712,36 @@
|
||||
"ExpectedInstructionCount": 2,
|
||||
"Comment": "GROUP1 0x83 /4",
|
||||
"ExpectedArm64ASM": [
|
||||
"ands w4, w4, #0x1",
|
||||
"mov x26, x4"
|
||||
"ands w26, w4, #0x1",
|
||||
"mov x4, x26"
|
||||
]
|
||||
},
|
||||
"and rax, 1": {
|
||||
"ExpectedInstructionCount": 2,
|
||||
"Comment": "GROUP1 0x83 /4",
|
||||
"ExpectedArm64ASM": [
|
||||
"ands x4, x4, #0x1",
|
||||
"mov x26, x4"
|
||||
"ands x26, x4, #0x1",
|
||||
"mov x4, x26"
|
||||
]
|
||||
},
|
||||
"sub eax, 1": {
|
||||
"ExpectedInstructionCount": 5,
|
||||
"ExpectedInstructionCount": 4,
|
||||
"Comment": "GROUP1 0x83 /5",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x27, x4",
|
||||
"sub w4, w27, #0x1 (1)",
|
||||
"mov x26, x4",
|
||||
"cmp w27, #0x1 (1)",
|
||||
"cfinv"
|
||||
"subs w26, w27, #0x1 (1)",
|
||||
"cfinv",
|
||||
"mov x4, x26"
|
||||
]
|
||||
},
|
||||
"sub rax, 1": {
|
||||
"ExpectedInstructionCount": 5,
|
||||
"ExpectedInstructionCount": 4,
|
||||
"Comment": "GROUP1 0x83 /5",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x27, x4",
|
||||
"sub x4, x27, #0x1 (1)",
|
||||
"mov x26, x4",
|
||||
"cmp x27, #0x1 (1)",
|
||||
"cfinv"
|
||||
"subs x26, x27, #0x1 (1)",
|
||||
"cfinv",
|
||||
"mov x4, x26"
|
||||
]
|
||||
},
|
||||
"xor eax, 1": {
|
||||
@ -783,61 +763,53 @@
|
||||
]
|
||||
},
|
||||
"cmp eax, 1": {
|
||||
"ExpectedInstructionCount": 4,
|
||||
"ExpectedInstructionCount": 3,
|
||||
"Comment": "GROUP1 0x83 /7",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x27, x4",
|
||||
"sub w26, w27, #0x1 (1)",
|
||||
"cmp w27, #0x1 (1)",
|
||||
"subs w26, w27, #0x1 (1)",
|
||||
"cfinv"
|
||||
]
|
||||
},
|
||||
"cmp rax, 1": {
|
||||
"ExpectedInstructionCount": 4,
|
||||
"ExpectedInstructionCount": 3,
|
||||
"Comment": "GROUP1 0x83 /7",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x27, x4",
|
||||
"sub x26, x27, #0x1 (1)",
|
||||
"cmp x27, #0x1 (1)",
|
||||
"subs x26, x27, #0x1 (1)",
|
||||
"cfinv"
|
||||
]
|
||||
},
|
||||
"add ax, -1": {
|
||||
"ExpectedInstructionCount": 8,
|
||||
"ExpectedInstructionCount": 6,
|
||||
"Comment": "GROUP1 0x83 /0",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0xffff",
|
||||
"mov x21, x4",
|
||||
"add w26, w21, w20",
|
||||
"mov x4, x21",
|
||||
"bfxil x4, x26, #0, #16",
|
||||
"eor w27, w21, #0xffff",
|
||||
"lsl w0, w21, #16",
|
||||
"cmn w0, w20, lsl #16"
|
||||
"eor w27, w4, #0xffff",
|
||||
"lsl w0, w4, #16",
|
||||
"cmn w0, w20, lsl #16",
|
||||
"add w26, w4, w20",
|
||||
"bfxil x4, x26, #0, #16"
|
||||
]
|
||||
},
|
||||
"add eax, -1": {
|
||||
"ExpectedInstructionCount": 6,
|
||||
"ExpectedInstructionCount": 4,
|
||||
"Comment": "GROUP1 0x83 /0",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0xffffffff",
|
||||
"mov x21, x4",
|
||||
"add w4, w21, w20",
|
||||
"eor w27, w21, w20",
|
||||
"mov x26, x4",
|
||||
"cmn w21, w20"
|
||||
"eor w27, w4, w20",
|
||||
"adds w26, w4, w20",
|
||||
"mov x4, x26"
|
||||
]
|
||||
},
|
||||
"add rax, -1": {
|
||||
"ExpectedInstructionCount": 6,
|
||||
"ExpectedInstructionCount": 4,
|
||||
"Comment": "GROUP1 0x83 /0",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x20, #0xffffffffffffffff",
|
||||
"mov x21, x4",
|
||||
"sub x4, x21, #0x1 (1)",
|
||||
"eor w27, w21, w20",
|
||||
"mov x26, x4",
|
||||
"cmn x21, x20"
|
||||
"eor w27, w4, w20",
|
||||
"adds x26, x4, x20",
|
||||
"mov x4, x26"
|
||||
]
|
||||
},
|
||||
"or eax, -1": {
|
||||
@ -925,8 +897,8 @@
|
||||
"Comment": "GROUP1 0x83 /4",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0xffffffff",
|
||||
"ands w4, w4, w20",
|
||||
"mov x26, x4"
|
||||
"ands w26, w4, w20",
|
||||
"mov x4, x26"
|
||||
]
|
||||
},
|
||||
"and rax, -1": {
|
||||
@ -934,34 +906,30 @@
|
||||
"Comment": "GROUP1 0x83 /4",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x20, #0xffffffffffffffff",
|
||||
"ands x4, x4, x20",
|
||||
"mov x26, x4"
|
||||
"ands x26, x4, x20",
|
||||
"mov x4, x26"
|
||||
]
|
||||
},
|
||||
"sub eax, -1": {
|
||||
"ExpectedInstructionCount": 7,
|
||||
"ExpectedInstructionCount": 5,
|
||||
"Comment": "GROUP1 0x83 /5",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0xffffffff",
|
||||
"mov x21, x4",
|
||||
"sub w4, w21, w20",
|
||||
"eor w27, w21, w20",
|
||||
"mov x26, x4",
|
||||
"cmp w21, w20",
|
||||
"cfinv"
|
||||
"eor w27, w4, w20",
|
||||
"subs w26, w4, w20",
|
||||
"cfinv",
|
||||
"mov x4, x26"
|
||||
]
|
||||
},
|
||||
"sub rax, -1": {
|
||||
"ExpectedInstructionCount": 7,
|
||||
"ExpectedInstructionCount": 5,
|
||||
"Comment": "GROUP1 0x83 /5",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x20, #0xffffffffffffffff",
|
||||
"mov x21, x4",
|
||||
"sub x4, x21, x20",
|
||||
"eor w27, w21, w20",
|
||||
"mov x26, x4",
|
||||
"cmp x21, x20",
|
||||
"cfinv"
|
||||
"eor w27, w4, w20",
|
||||
"subs x26, x4, x20",
|
||||
"cfinv",
|
||||
"mov x4, x26"
|
||||
]
|
||||
},
|
||||
"xor eax, -1": {
|
||||
@ -985,24 +953,22 @@
|
||||
]
|
||||
},
|
||||
"cmp eax, -1": {
|
||||
"ExpectedInstructionCount": 5,
|
||||
"ExpectedInstructionCount": 4,
|
||||
"Comment": "GROUP1 0x83 /7",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0xffffffff",
|
||||
"sub w26, w4, w20",
|
||||
"eor w27, w4, w20",
|
||||
"cmp w4, w20",
|
||||
"subs w26, w4, w20",
|
||||
"cfinv"
|
||||
]
|
||||
},
|
||||
"cmp rax, -1": {
|
||||
"ExpectedInstructionCount": 5,
|
||||
"ExpectedInstructionCount": 4,
|
||||
"Comment": "GROUP1 0x83 /7",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x20, #0xffffffffffffffff",
|
||||
"sub x26, x4, x20",
|
||||
"eor w27, w4, w20",
|
||||
"cmp x4, x20",
|
||||
"subs x26, x4, x20",
|
||||
"cfinv"
|
||||
]
|
||||
},
|
||||
@ -2239,10 +2205,10 @@
|
||||
"Comment": "GROUP2 0xf6 /3",
|
||||
"ExpectedArm64ASM": [
|
||||
"uxtb w27, w7",
|
||||
"neg w26, w27",
|
||||
"bfxil x7, x26, #0, #8",
|
||||
"cmp wzr, w27, lsl #24",
|
||||
"cfinv"
|
||||
"neg w26, w27",
|
||||
"cfinv",
|
||||
"bfxil x7, x26, #0, #8"
|
||||
]
|
||||
},
|
||||
"mul bl": {
|
||||
@ -2357,32 +2323,30 @@
|
||||
"Comment": "GROUP2 0xf7 /2",
|
||||
"ExpectedArm64ASM": [
|
||||
"uxth w27, w7",
|
||||
"neg w26, w27",
|
||||
"bfxil x7, x26, #0, #16",
|
||||
"cmp wzr, w27, lsl #16",
|
||||
"cfinv"
|
||||
"neg w26, w27",
|
||||
"cfinv",
|
||||
"bfxil x7, x26, #0, #16"
|
||||
]
|
||||
},
|
||||
"neg ebx": {
|
||||
"ExpectedInstructionCount": 5,
|
||||
"ExpectedInstructionCount": 4,
|
||||
"Comment": "GROUP2 0xf7 /2",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w27, w7",
|
||||
"neg w7, w27",
|
||||
"mov x26, x7",
|
||||
"cmp wzr, w27",
|
||||
"cfinv"
|
||||
"negs w26, w27",
|
||||
"cfinv",
|
||||
"mov x7, x26"
|
||||
]
|
||||
},
|
||||
"neg rbx": {
|
||||
"ExpectedInstructionCount": 5,
|
||||
"ExpectedInstructionCount": 4,
|
||||
"Comment": "GROUP2 0xf7 /2",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x27, x7",
|
||||
"neg x7, x27",
|
||||
"mov x26, x7",
|
||||
"cmp xzr, x27",
|
||||
"cfinv"
|
||||
"negs x26, x27",
|
||||
"cfinv",
|
||||
"mov x7, x26"
|
||||
]
|
||||
},
|
||||
"mul bx": {
|
||||
@ -2489,12 +2453,12 @@
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0x1",
|
||||
"uxtb w27, w4",
|
||||
"add w26, w27, #0x1 (1)",
|
||||
"bfxil x4, x26, #0, #8",
|
||||
"cset w21, hs",
|
||||
"lsl w0, w27, #24",
|
||||
"cmn w0, w20, lsl #24",
|
||||
"rmif x21, #63, #nzCv"
|
||||
"add w26, w27, #0x1 (1)",
|
||||
"rmif x21, #63, #nzCv",
|
||||
"bfxil x4, x26, #0, #8"
|
||||
]
|
||||
},
|
||||
"dec al": {
|
||||
@ -2503,12 +2467,12 @@
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0x1",
|
||||
"uxtb w27, w4",
|
||||
"sub w26, w27, #0x1 (1)",
|
||||
"bfxil x4, x26, #0, #8",
|
||||
"cset w21, hs",
|
||||
"lsl w0, w27, #24",
|
||||
"cmp w0, w20, lsl #24",
|
||||
"rmif x21, #63, #nzCv"
|
||||
"sub w26, w27, #0x1 (1)",
|
||||
"rmif x21, #63, #nzCv",
|
||||
"bfxil x4, x26, #0, #8"
|
||||
]
|
||||
},
|
||||
"inc ax": {
|
||||
@ -2517,36 +2481,34 @@
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0x1",
|
||||
"uxth w27, w4",
|
||||
"add w26, w27, #0x1 (1)",
|
||||
"bfxil x4, x26, #0, #16",
|
||||
"cset w21, hs",
|
||||
"lsl w0, w27, #16",
|
||||
"cmn w0, w20, lsl #16",
|
||||
"rmif x21, #63, #nzCv"
|
||||
"add w26, w27, #0x1 (1)",
|
||||
"rmif x21, #63, #nzCv",
|
||||
"bfxil x4, x26, #0, #16"
|
||||
]
|
||||
},
|
||||
"inc eax": {
|
||||
"ExpectedInstructionCount": 6,
|
||||
"ExpectedInstructionCount": 5,
|
||||
"Comment": "GROUP4 0xfe /0",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x27, x4",
|
||||
"add w4, w27, #0x1 (1)",
|
||||
"mov x26, x4",
|
||||
"cset w20, hs",
|
||||
"cmn w27, #0x1 (1)",
|
||||
"rmif x20, #63, #nzCv"
|
||||
"adds w26, w27, #0x1 (1)",
|
||||
"rmif x20, #63, #nzCv",
|
||||
"mov x4, x26"
|
||||
]
|
||||
},
|
||||
"inc rax": {
|
||||
"ExpectedInstructionCount": 6,
|
||||
"ExpectedInstructionCount": 5,
|
||||
"Comment": "GROUP4 0xfe /0",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x27, x4",
|
||||
"add x4, x27, #0x1 (1)",
|
||||
"mov x26, x4",
|
||||
"cset w20, hs",
|
||||
"cmn x27, #0x1 (1)",
|
||||
"rmif x20, #63, #nzCv"
|
||||
"adds x26, x27, #0x1 (1)",
|
||||
"rmif x20, #63, #nzCv",
|
||||
"mov x4, x26"
|
||||
]
|
||||
},
|
||||
"dec ax": {
|
||||
@ -2555,36 +2517,34 @@
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0x1",
|
||||
"uxth w27, w4",
|
||||
"sub w26, w27, #0x1 (1)",
|
||||
"bfxil x4, x26, #0, #16",
|
||||
"cset w21, hs",
|
||||
"lsl w0, w27, #16",
|
||||
"cmp w0, w20, lsl #16",
|
||||
"rmif x21, #63, #nzCv"
|
||||
"sub w26, w27, #0x1 (1)",
|
||||
"rmif x21, #63, #nzCv",
|
||||
"bfxil x4, x26, #0, #16"
|
||||
]
|
||||
},
|
||||
"dec eax": {
|
||||
"ExpectedInstructionCount": 6,
|
||||
"ExpectedInstructionCount": 5,
|
||||
"Comment": "GROUP4 0xfe /1",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x27, x4",
|
||||
"sub w4, w27, #0x1 (1)",
|
||||
"mov x26, x4",
|
||||
"cset w20, hs",
|
||||
"cmp w27, #0x1 (1)",
|
||||
"rmif x20, #63, #nzCv"
|
||||
"subs w26, w27, #0x1 (1)",
|
||||
"rmif x20, #63, #nzCv",
|
||||
"mov x4, x26"
|
||||
]
|
||||
},
|
||||
"dec rax": {
|
||||
"ExpectedInstructionCount": 6,
|
||||
"ExpectedInstructionCount": 5,
|
||||
"Comment": "GROUP4 0xfe /1",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x27, x4",
|
||||
"sub x4, x27, #0x1 (1)",
|
||||
"mov x26, x4",
|
||||
"cset w20, hs",
|
||||
"cmp x27, #0x1 (1)",
|
||||
"rmif x20, #63, #nzCv"
|
||||
"subs x26, x27, #0x1 (1)",
|
||||
"rmif x20, #63, #nzCv",
|
||||
"mov x4, x26"
|
||||
]
|
||||
}
|
||||
}
|
||||
|
||||
@ -1026,10 +1026,10 @@
|
||||
"uxtb w20, w7",
|
||||
"uxtb w21, w5",
|
||||
"uxtb x22, w4",
|
||||
"sub x26, x22, x21",
|
||||
"eor w27, w22, w21",
|
||||
"lsl w0, w22, #24",
|
||||
"cmp w0, w21, lsl #24",
|
||||
"sub w26, w22, w21",
|
||||
"cfinv",
|
||||
"bfxil x4, x21, #0, #8",
|
||||
"csel x20, x20, x21, eq",
|
||||
@ -1042,10 +1042,10 @@
|
||||
"uxth w20, w7",
|
||||
"uxth w21, w5",
|
||||
"uxth x22, w4",
|
||||
"sub x26, x22, x21",
|
||||
"eor w27, w22, w21",
|
||||
"lsl w0, w22, #16",
|
||||
"cmp w0, w21, lsl #16",
|
||||
"sub w26, w22, w21",
|
||||
"cfinv",
|
||||
"bfxil x4, x21, #0, #16",
|
||||
"csel x20, x20, x21, eq",
|
||||
@ -1053,42 +1053,39 @@
|
||||
]
|
||||
},
|
||||
"cmpxchg ecx, ebx": {
|
||||
"ExpectedInstructionCount": 9,
|
||||
"ExpectedInstructionCount": 8,
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, w7",
|
||||
"mov w21, w5",
|
||||
"mov w22, w4",
|
||||
"sub x26, x22, x21",
|
||||
"eor w27, w22, w21",
|
||||
"cmp w22, w21",
|
||||
"subs w26, w22, w21",
|
||||
"cfinv",
|
||||
"csel x4, x4, x21, eq",
|
||||
"csel x5, x20, x5, eq"
|
||||
]
|
||||
},
|
||||
"cmpxchg rcx, rbx": {
|
||||
"ExpectedInstructionCount": 7,
|
||||
"ExpectedInstructionCount": 6,
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x20, x5",
|
||||
"sub x26, x4, x20",
|
||||
"eor w27, w4, w20",
|
||||
"cmp x4, x20",
|
||||
"subs x26, x4, x20",
|
||||
"cfinv",
|
||||
"mov x4, x20",
|
||||
"csel x5, x7, x20, eq"
|
||||
]
|
||||
},
|
||||
"cmpxchg [rax], rbx": {
|
||||
"ExpectedInstructionCount": 8,
|
||||
"ExpectedInstructionCount": 7,
|
||||
"Comment": "0x0f 0xb1",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x20, x4",
|
||||
"mov x1, x20",
|
||||
"casal x1, x7, [x20]",
|
||||
"mov x4, x1",
|
||||
"sub x26, x20, x4",
|
||||
"eor w27, w20, w4",
|
||||
"cmp x20, x4",
|
||||
"subs x26, x20, x4",
|
||||
"cfinv"
|
||||
]
|
||||
},
|
||||
@ -1099,10 +1096,10 @@
|
||||
"uxtb w20, w7",
|
||||
"uxtb w21, w4",
|
||||
"uxtb x22, w4",
|
||||
"sub x26, x22, x21",
|
||||
"eor w27, w22, w21",
|
||||
"lsl w0, w22, #24",
|
||||
"cmp w0, w21, lsl #24",
|
||||
"sub w26, w22, w21",
|
||||
"cfinv",
|
||||
"bfxil x4, x20, #0, #8"
|
||||
]
|
||||
@ -1117,10 +1114,10 @@
|
||||
"casalb w1, w20, [x4]",
|
||||
"mov w20, w1",
|
||||
"bfxil x4, x20, #0, #8",
|
||||
"sub w26, w21, w20",
|
||||
"eor w27, w21, w20",
|
||||
"lsl w0, w21, #24",
|
||||
"cmp w0, w20, lsl #24",
|
||||
"sub w26, w21, w20",
|
||||
"cfinv"
|
||||
]
|
||||
},
|
||||
@ -1131,10 +1128,10 @@
|
||||
"uxth w20, w7",
|
||||
"uxth w21, w4",
|
||||
"uxth x22, w4",
|
||||
"sub x26, x22, x21",
|
||||
"eor w27, w22, w21",
|
||||
"lsl w0, w22, #16",
|
||||
"cmp w0, w21, lsl #16",
|
||||
"sub w26, w22, w21",
|
||||
"cfinv",
|
||||
"bfxil x4, x20, #0, #16"
|
||||
]
|
||||
@ -1149,29 +1146,28 @@
|
||||
"casalh w1, w20, [x4]",
|
||||
"mov w20, w1",
|
||||
"bfxil x4, x20, #0, #16",
|
||||
"sub w26, w21, w20",
|
||||
"eor w27, w21, w20",
|
||||
"lsl w0, w21, #16",
|
||||
"cmp w0, w20, lsl #16",
|
||||
"sub w26, w21, w20",
|
||||
"cfinv"
|
||||
]
|
||||
},
|
||||
"cmpxchg eax, ebx": {
|
||||
"ExpectedInstructionCount": 8,
|
||||
"ExpectedInstructionCount": 7,
|
||||
"Comment": "0x0f 0xb1",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, w7",
|
||||
"mov w21, w4",
|
||||
"mov w22, w4",
|
||||
"sub x26, x22, x21",
|
||||
"eor w27, w22, w21",
|
||||
"cmp w22, w21",
|
||||
"subs w26, w22, w21",
|
||||
"cfinv",
|
||||
"mov x4, x20"
|
||||
]
|
||||
},
|
||||
"cmpxchg [rax], ebx": {
|
||||
"ExpectedInstructionCount": 11,
|
||||
"ExpectedInstructionCount": 10,
|
||||
"Comment": "0x0f 0xb1",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, w7",
|
||||
@ -1181,20 +1177,18 @@
|
||||
"mov w20, w1",
|
||||
"cmp w20, w21",
|
||||
"csel x4, x4, x20, eq",
|
||||
"sub w26, w21, w20",
|
||||
"eor w27, w21, w20",
|
||||
"cmp w21, w20",
|
||||
"subs w26, w21, w20",
|
||||
"cfinv"
|
||||
]
|
||||
},
|
||||
"cmpxchg rax, rbx": {
|
||||
"ExpectedInstructionCount": 6,
|
||||
"ExpectedInstructionCount": 5,
|
||||
"Comment": "0x0f 0xb1",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x20, x7",
|
||||
"sub x26, x4, x4",
|
||||
"mov w27, #0x0",
|
||||
"cmp x4, x4",
|
||||
"subs x26, x4, x4",
|
||||
"cfinv",
|
||||
"mov x4, x20"
|
||||
]
|
||||
@ -1530,12 +1524,12 @@
|
||||
"ExpectedArm64ASM": [
|
||||
"uxtb w20, w4",
|
||||
"uxtb w21, w7",
|
||||
"add w26, w20, w21",
|
||||
"bfxil x7, x20, #0, #8",
|
||||
"bfxil x4, x26, #0, #8",
|
||||
"eor w27, w20, w21",
|
||||
"lsl w0, w20, #24",
|
||||
"cmn w0, w21, lsl #24"
|
||||
"cmn w0, w21, lsl #24",
|
||||
"add w26, w20, w21",
|
||||
"bfxil x7, x20, #0, #8",
|
||||
"bfxil x4, x26, #0, #8"
|
||||
]
|
||||
},
|
||||
"xadd [rax], bl": {
|
||||
@ -1545,10 +1539,10 @@
|
||||
"uxtb w20, w7",
|
||||
"ldaddalb w20, w21, [x4]",
|
||||
"bfxil x7, x21, #0, #8",
|
||||
"add w26, w21, w20",
|
||||
"eor w27, w21, w20",
|
||||
"lsl w0, w21, #24",
|
||||
"cmn w0, w20, lsl #24"
|
||||
"cmn w0, w20, lsl #24",
|
||||
"add w26, w21, w20"
|
||||
]
|
||||
},
|
||||
"xadd ax, bx": {
|
||||
@ -1557,12 +1551,12 @@
|
||||
"ExpectedArm64ASM": [
|
||||
"uxth w20, w4",
|
||||
"uxth w21, w7",
|
||||
"add w26, w20, w21",
|
||||
"bfxil x7, x20, #0, #16",
|
||||
"bfxil x4, x26, #0, #16",
|
||||
"eor w27, w20, w21",
|
||||
"lsl w0, w20, #16",
|
||||
"cmn w0, w21, lsl #16"
|
||||
"cmn w0, w21, lsl #16",
|
||||
"add w26, w20, w21",
|
||||
"bfxil x7, x20, #0, #16",
|
||||
"bfxil x4, x26, #0, #16"
|
||||
]
|
||||
},
|
||||
"xadd [rax], bx": {
|
||||
@ -1572,58 +1566,53 @@
|
||||
"uxth w20, w7",
|
||||
"ldaddalh w20, w21, [x4]",
|
||||
"bfxil x7, x21, #0, #16",
|
||||
"add w26, w21, w20",
|
||||
"eor w27, w21, w20",
|
||||
"lsl w0, w21, #16",
|
||||
"cmn w0, w20, lsl #16"
|
||||
"cmn w0, w20, lsl #16",
|
||||
"add w26, w21, w20"
|
||||
]
|
||||
},
|
||||
"xadd eax, ebx": {
|
||||
"ExpectedInstructionCount": 7,
|
||||
"ExpectedInstructionCount": 6,
|
||||
"Comment": "0x0f 0xc1",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, w4",
|
||||
"mov w21, w7",
|
||||
"add w4, w20, w21",
|
||||
"mov x7, x20",
|
||||
"eor w27, w20, w21",
|
||||
"mov x26, x4",
|
||||
"cmn w20, w21"
|
||||
"adds w26, w20, w21",
|
||||
"mov x7, x20",
|
||||
"mov x4, x26"
|
||||
]
|
||||
},
|
||||
"xadd [rax], ebx": {
|
||||
"ExpectedInstructionCount": 5,
|
||||
"ExpectedInstructionCount": 4,
|
||||
"Comment": "0x0f 0xc1",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, w7",
|
||||
"ldaddal w20, w7, [x4]",
|
||||
"add w26, w7, w20",
|
||||
"eor w27, w7, w20",
|
||||
"cmn w7, w20"
|
||||
"adds w26, w7, w20"
|
||||
]
|
||||
},
|
||||
"xadd rax, rbx": {
|
||||
"ExpectedInstructionCount": 7,
|
||||
"ExpectedInstructionCount": 5,
|
||||
"Comment": "0x0f 0xc1",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x20, x4",
|
||||
"mov x21, x7",
|
||||
"add x4, x20, x21",
|
||||
"eor w27, w20, w7",
|
||||
"adds x26, x20, x7",
|
||||
"mov x7, x20",
|
||||
"eor w27, w20, w21",
|
||||
"mov x26, x4",
|
||||
"cmn x20, x21"
|
||||
"mov x4, x26"
|
||||
]
|
||||
},
|
||||
"xadd [rax], rbx": {
|
||||
"ExpectedInstructionCount": 5,
|
||||
"ExpectedInstructionCount": 4,
|
||||
"Comment": "0x0f 0xc1",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x20, x7",
|
||||
"ldaddal x20, x7, [x4]",
|
||||
"add x26, x7, x20",
|
||||
"eor w27, w7, w20",
|
||||
"cmn x7, x20"
|
||||
"adds x26, x7, x20"
|
||||
]
|
||||
},
|
||||
"pmovmskb eax, mm0": {
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -20,11 +20,11 @@
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0x1",
|
||||
"mov x27, x4",
|
||||
"lsl w0, w27, #24",
|
||||
"cmn w0, w20, lsl #24",
|
||||
"add w26, w27, #0x1 (1)",
|
||||
"mov x4, x27",
|
||||
"bfxil x4, x26, #0, #8",
|
||||
"lsl w0, w27, #24",
|
||||
"cmn w0, w20, lsl #24"
|
||||
"bfxil x4, x26, #0, #8"
|
||||
]
|
||||
},
|
||||
"or al, 1": {
|
||||
@ -103,13 +103,13 @@
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0x1",
|
||||
"mov x27, x4",
|
||||
"sub w26, w27, #0x1 (1)",
|
||||
"mov x4, x27",
|
||||
"bfxil x4, x26, #0, #8",
|
||||
"lsl w0, w27, #24",
|
||||
"cmp w0, w20, lsl #24",
|
||||
"sub w26, w27, #0x1 (1)",
|
||||
"mrs x20, nzcv",
|
||||
"eor w20, w20, #0x20000000",
|
||||
"mov x4, x27",
|
||||
"bfxil x4, x26, #0, #8",
|
||||
"msr nzcv, x20"
|
||||
]
|
||||
},
|
||||
@ -128,26 +128,24 @@
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0x1",
|
||||
"mov x27, x4",
|
||||
"sub w26, w27, #0x1 (1)",
|
||||
"lsl w0, w27, #24",
|
||||
"cmp w0, w20, lsl #24",
|
||||
"sub w26, w27, #0x1 (1)",
|
||||
"mrs x20, nzcv",
|
||||
"eor w20, w20, #0x20000000",
|
||||
"msr nzcv, x20"
|
||||
]
|
||||
},
|
||||
"add al, -1": {
|
||||
"ExpectedInstructionCount": 8,
|
||||
"ExpectedInstructionCount": 6,
|
||||
"Comment": "GROUP1 0x80 /0",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0xff",
|
||||
"mov x21, x4",
|
||||
"add w26, w21, #0xff (255)",
|
||||
"mov x4, x21",
|
||||
"bfxil x4, x26, #0, #8",
|
||||
"eor w27, w21, #0xff",
|
||||
"lsl w0, w21, #24",
|
||||
"cmn w0, w20, lsl #24"
|
||||
"eor w27, w4, #0xff",
|
||||
"lsl w0, w4, #24",
|
||||
"cmn w0, w20, lsl #24",
|
||||
"add w26, w4, #0xff (255)",
|
||||
"bfxil x4, x26, #0, #8"
|
||||
]
|
||||
},
|
||||
"or al, -1": {
|
||||
@ -223,19 +221,17 @@
|
||||
]
|
||||
},
|
||||
"sub al, -1": {
|
||||
"ExpectedInstructionCount": 11,
|
||||
"ExpectedInstructionCount": 9,
|
||||
"Comment": "GROUP1 0x80 /5",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0xff",
|
||||
"mov x21, x4",
|
||||
"sub w26, w21, #0xff (255)",
|
||||
"mov x4, x21",
|
||||
"bfxil x4, x26, #0, #8",
|
||||
"eor w27, w21, #0xff",
|
||||
"lsl w0, w21, #24",
|
||||
"eor w27, w4, #0xff",
|
||||
"lsl w0, w4, #24",
|
||||
"cmp w0, w20, lsl #24",
|
||||
"sub w26, w4, #0xff (255)",
|
||||
"mrs x20, nzcv",
|
||||
"eor w20, w20, #0x20000000",
|
||||
"bfxil x4, x26, #0, #8",
|
||||
"msr nzcv, x20"
|
||||
]
|
||||
},
|
||||
@ -253,10 +249,10 @@
|
||||
"Comment": "GROUP1 0x80 /7",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0xff",
|
||||
"sub w26, w4, #0xff (255)",
|
||||
"eor w27, w4, #0xff",
|
||||
"lsl w0, w4, #24",
|
||||
"cmp w0, w20, lsl #24",
|
||||
"sub w26, w4, #0xff (255)",
|
||||
"mrs x20, nzcv",
|
||||
"eor w20, w20, #0x20000000",
|
||||
"msr nzcv, x20"
|
||||
@ -268,31 +264,29 @@
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0x100",
|
||||
"mov x27, x4",
|
||||
"lsl w0, w27, #16",
|
||||
"cmn w0, w20, lsl #16",
|
||||
"add w26, w27, #0x100 (256)",
|
||||
"mov x4, x27",
|
||||
"bfxil x4, x26, #0, #16",
|
||||
"lsl w0, w27, #16",
|
||||
"cmn w0, w20, lsl #16"
|
||||
"bfxil x4, x26, #0, #16"
|
||||
]
|
||||
},
|
||||
"add eax, 256": {
|
||||
"ExpectedInstructionCount": 4,
|
||||
"ExpectedInstructionCount": 3,
|
||||
"Comment": "GROUP1 0x81 /0",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x27, x4",
|
||||
"add w4, w27, #0x100 (256)",
|
||||
"mov x26, x4",
|
||||
"cmn w27, #0x100 (256)"
|
||||
"adds w26, w27, #0x100 (256)",
|
||||
"mov x4, x26"
|
||||
]
|
||||
},
|
||||
"add rax, 256": {
|
||||
"ExpectedInstructionCount": 4,
|
||||
"ExpectedInstructionCount": 3,
|
||||
"Comment": "GROUP1 0x81 /0",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x27, x4",
|
||||
"add x4, x27, #0x100 (256)",
|
||||
"mov x26, x4",
|
||||
"cmn x27, #0x100 (256)"
|
||||
"adds x26, x27, #0x100 (256)",
|
||||
"mov x4, x26"
|
||||
]
|
||||
},
|
||||
"or eax, 256": {
|
||||
@ -381,41 +375,39 @@
|
||||
"ExpectedInstructionCount": 2,
|
||||
"Comment": "GROUP1 0x81 /4",
|
||||
"ExpectedArm64ASM": [
|
||||
"ands w4, w4, #0x100",
|
||||
"mov x26, x4"
|
||||
"ands w26, w4, #0x100",
|
||||
"mov x4, x26"
|
||||
]
|
||||
},
|
||||
"and rax, 256": {
|
||||
"ExpectedInstructionCount": 2,
|
||||
"Comment": "GROUP1 0x81 /4",
|
||||
"ExpectedArm64ASM": [
|
||||
"ands x4, x4, #0x100",
|
||||
"mov x26, x4"
|
||||
"ands x26, x4, #0x100",
|
||||
"mov x4, x26"
|
||||
]
|
||||
},
|
||||
"sub eax, 256": {
|
||||
"ExpectedInstructionCount": 7,
|
||||
"ExpectedInstructionCount": 6,
|
||||
"Comment": "GROUP1 0x81 /5",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x27, x4",
|
||||
"sub w4, w27, #0x100 (256)",
|
||||
"mov x26, x4",
|
||||
"cmp w27, #0x100 (256)",
|
||||
"subs w26, w27, #0x100 (256)",
|
||||
"mrs x20, nzcv",
|
||||
"eor w20, w20, #0x20000000",
|
||||
"mov x4, x26",
|
||||
"msr nzcv, x20"
|
||||
]
|
||||
},
|
||||
"sub rax, 256": {
|
||||
"ExpectedInstructionCount": 7,
|
||||
"ExpectedInstructionCount": 6,
|
||||
"Comment": "GROUP1 0x81 /5",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x27, x4",
|
||||
"sub x4, x27, #0x100 (256)",
|
||||
"mov x26, x4",
|
||||
"cmp x27, #0x100 (256)",
|
||||
"subs x26, x27, #0x100 (256)",
|
||||
"mrs x20, nzcv",
|
||||
"eor w20, w20, #0x20000000",
|
||||
"mov x4, x26",
|
||||
"msr nzcv, x20"
|
||||
]
|
||||
},
|
||||
@ -438,24 +430,22 @@
|
||||
]
|
||||
},
|
||||
"cmp eax, 256": {
|
||||
"ExpectedInstructionCount": 6,
|
||||
"ExpectedInstructionCount": 5,
|
||||
"Comment": "GROUP1 0x81 /7",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x27, x4",
|
||||
"sub w26, w27, #0x100 (256)",
|
||||
"cmp w27, #0x100 (256)",
|
||||
"subs w26, w27, #0x100 (256)",
|
||||
"mrs x20, nzcv",
|
||||
"eor w20, w20, #0x20000000",
|
||||
"msr nzcv, x20"
|
||||
]
|
||||
},
|
||||
"cmp rax, 256": {
|
||||
"ExpectedInstructionCount": 6,
|
||||
"ExpectedInstructionCount": 5,
|
||||
"Comment": "GROUP1 0x81 /7",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x27, x4",
|
||||
"sub x26, x27, #0x100 (256)",
|
||||
"cmp x27, #0x100 (256)",
|
||||
"subs x26, x27, #0x100 (256)",
|
||||
"mrs x20, nzcv",
|
||||
"eor w20, w20, #0x20000000",
|
||||
"msr nzcv, x20"
|
||||
@ -467,33 +457,31 @@
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0xff00",
|
||||
"mov x27, x4",
|
||||
"lsl w0, w27, #16",
|
||||
"cmn w0, w20, lsl #16",
|
||||
"add w26, w27, w20",
|
||||
"mov x4, x27",
|
||||
"bfxil x4, x26, #0, #16",
|
||||
"lsl w0, w27, #16",
|
||||
"cmn w0, w20, lsl #16"
|
||||
"bfxil x4, x26, #0, #16"
|
||||
]
|
||||
},
|
||||
"add eax, -256": {
|
||||
"ExpectedInstructionCount": 5,
|
||||
"ExpectedInstructionCount": 4,
|
||||
"Comment": "GROUP1 0x81 /0",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0xffffff00",
|
||||
"mov x27, x4",
|
||||
"add w4, w27, w20",
|
||||
"mov x26, x4",
|
||||
"cmn w27, w20"
|
||||
"adds w26, w27, w20",
|
||||
"mov x4, x26"
|
||||
]
|
||||
},
|
||||
"add rax, -256": {
|
||||
"ExpectedInstructionCount": 5,
|
||||
"ExpectedInstructionCount": 4,
|
||||
"Comment": "GROUP1 0x81 /0",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x20, #0xffffffffffffff00",
|
||||
"mov x27, x4",
|
||||
"sub x4, x27, #0x100 (256)",
|
||||
"mov x26, x4",
|
||||
"cmn x27, x20"
|
||||
"adds x26, x27, x20",
|
||||
"mov x4, x26"
|
||||
]
|
||||
},
|
||||
"or eax, -256": {
|
||||
@ -582,43 +570,41 @@
|
||||
"ExpectedInstructionCount": 2,
|
||||
"Comment": "GROUP1 0x81 /4",
|
||||
"ExpectedArm64ASM": [
|
||||
"ands w4, w4, #0xffffff00",
|
||||
"mov x26, x4"
|
||||
"ands w26, w4, #0xffffff00",
|
||||
"mov x4, x26"
|
||||
]
|
||||
},
|
||||
"and rax, -256": {
|
||||
"ExpectedInstructionCount": 2,
|
||||
"Comment": "GROUP1 0x81 /4",
|
||||
"ExpectedArm64ASM": [
|
||||
"ands x4, x4, #0xffffffffffffff00",
|
||||
"mov x26, x4"
|
||||
"ands x26, x4, #0xffffffffffffff00",
|
||||
"mov x4, x26"
|
||||
]
|
||||
},
|
||||
"sub eax, -256": {
|
||||
"ExpectedInstructionCount": 8,
|
||||
"ExpectedInstructionCount": 7,
|
||||
"Comment": "GROUP1 0x81 /5",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0xffffff00",
|
||||
"mov x27, x4",
|
||||
"sub w4, w27, w20",
|
||||
"mov x26, x4",
|
||||
"cmp w27, w20",
|
||||
"subs w26, w27, w20",
|
||||
"mrs x20, nzcv",
|
||||
"eor w20, w20, #0x20000000",
|
||||
"mov x4, x26",
|
||||
"msr nzcv, x20"
|
||||
]
|
||||
},
|
||||
"sub rax, -256": {
|
||||
"ExpectedInstructionCount": 8,
|
||||
"ExpectedInstructionCount": 7,
|
||||
"Comment": "GROUP1 0x81 /5",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x20, #0xffffffffffffff00",
|
||||
"mov x27, x4",
|
||||
"sub x4, x27, x20",
|
||||
"mov x26, x4",
|
||||
"cmp x27, x20",
|
||||
"subs x26, x27, x20",
|
||||
"mrs x20, nzcv",
|
||||
"eor w20, w20, #0x20000000",
|
||||
"mov x4, x26",
|
||||
"msr nzcv, x20"
|
||||
]
|
||||
},
|
||||
@ -641,26 +627,24 @@
|
||||
]
|
||||
},
|
||||
"cmp eax, -256": {
|
||||
"ExpectedInstructionCount": 7,
|
||||
"ExpectedInstructionCount": 6,
|
||||
"Comment": "GROUP1 0x81 /7",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0xffffff00",
|
||||
"mov x27, x4",
|
||||
"sub w26, w27, w20",
|
||||
"cmp w27, w20",
|
||||
"subs w26, w27, w20",
|
||||
"mrs x20, nzcv",
|
||||
"eor w20, w20, #0x20000000",
|
||||
"msr nzcv, x20"
|
||||
]
|
||||
},
|
||||
"cmp rax, -256": {
|
||||
"ExpectedInstructionCount": 7,
|
||||
"ExpectedInstructionCount": 6,
|
||||
"Comment": "GROUP1 0x81 /7",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x20, #0xffffffffffffff00",
|
||||
"mov x27, x4",
|
||||
"sub x26, x27, x20",
|
||||
"cmp x27, x20",
|
||||
"subs x26, x27, x20",
|
||||
"mrs x20, nzcv",
|
||||
"eor w20, w20, #0x20000000",
|
||||
"msr nzcv, x20"
|
||||
@ -672,31 +656,29 @@
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0x1",
|
||||
"mov x27, x4",
|
||||
"lsl w0, w27, #16",
|
||||
"cmn w0, w20, lsl #16",
|
||||
"add w26, w27, #0x1 (1)",
|
||||
"mov x4, x27",
|
||||
"bfxil x4, x26, #0, #16",
|
||||
"lsl w0, w27, #16",
|
||||
"cmn w0, w20, lsl #16"
|
||||
"bfxil x4, x26, #0, #16"
|
||||
]
|
||||
},
|
||||
"add eax, 1": {
|
||||
"ExpectedInstructionCount": 4,
|
||||
"ExpectedInstructionCount": 3,
|
||||
"Comment": "GROUP1 0x83 /0",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x27, x4",
|
||||
"add w4, w27, #0x1 (1)",
|
||||
"mov x26, x4",
|
||||
"cmn w27, #0x1 (1)"
|
||||
"adds w26, w27, #0x1 (1)",
|
||||
"mov x4, x26"
|
||||
]
|
||||
},
|
||||
"add rax, 1": {
|
||||
"ExpectedInstructionCount": 4,
|
||||
"ExpectedInstructionCount": 3,
|
||||
"Comment": "GROUP1 0x83 /0",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x27, x4",
|
||||
"add x4, x27, #0x1 (1)",
|
||||
"mov x26, x4",
|
||||
"cmn x27, #0x1 (1)"
|
||||
"adds x26, x27, #0x1 (1)",
|
||||
"mov x4, x26"
|
||||
]
|
||||
},
|
||||
"or eax, 1": {
|
||||
@ -785,41 +767,39 @@
|
||||
"ExpectedInstructionCount": 2,
|
||||
"Comment": "GROUP1 0x83 /4",
|
||||
"ExpectedArm64ASM": [
|
||||
"ands w4, w4, #0x1",
|
||||
"mov x26, x4"
|
||||
"ands w26, w4, #0x1",
|
||||
"mov x4, x26"
|
||||
]
|
||||
},
|
||||
"and rax, 1": {
|
||||
"ExpectedInstructionCount": 2,
|
||||
"Comment": "GROUP1 0x83 /4",
|
||||
"ExpectedArm64ASM": [
|
||||
"ands x4, x4, #0x1",
|
||||
"mov x26, x4"
|
||||
"ands x26, x4, #0x1",
|
||||
"mov x4, x26"
|
||||
]
|
||||
},
|
||||
"sub eax, 1": {
|
||||
"ExpectedInstructionCount": 7,
|
||||
"ExpectedInstructionCount": 6,
|
||||
"Comment": "GROUP1 0x83 /5",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x27, x4",
|
||||
"sub w4, w27, #0x1 (1)",
|
||||
"mov x26, x4",
|
||||
"cmp w27, #0x1 (1)",
|
||||
"subs w26, w27, #0x1 (1)",
|
||||
"mrs x20, nzcv",
|
||||
"eor w20, w20, #0x20000000",
|
||||
"mov x4, x26",
|
||||
"msr nzcv, x20"
|
||||
]
|
||||
},
|
||||
"sub rax, 1": {
|
||||
"ExpectedInstructionCount": 7,
|
||||
"ExpectedInstructionCount": 6,
|
||||
"Comment": "GROUP1 0x83 /5",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x27, x4",
|
||||
"sub x4, x27, #0x1 (1)",
|
||||
"mov x26, x4",
|
||||
"cmp x27, #0x1 (1)",
|
||||
"subs x26, x27, #0x1 (1)",
|
||||
"mrs x20, nzcv",
|
||||
"eor w20, w20, #0x20000000",
|
||||
"mov x4, x26",
|
||||
"msr nzcv, x20"
|
||||
]
|
||||
},
|
||||
@ -842,65 +822,57 @@
|
||||
]
|
||||
},
|
||||
"cmp eax, 1": {
|
||||
"ExpectedInstructionCount": 6,
|
||||
"ExpectedInstructionCount": 5,
|
||||
"Comment": "GROUP1 0x83 /7",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x27, x4",
|
||||
"sub w26, w27, #0x1 (1)",
|
||||
"cmp w27, #0x1 (1)",
|
||||
"subs w26, w27, #0x1 (1)",
|
||||
"mrs x20, nzcv",
|
||||
"eor w20, w20, #0x20000000",
|
||||
"msr nzcv, x20"
|
||||
]
|
||||
},
|
||||
"cmp rax, 1": {
|
||||
"ExpectedInstructionCount": 6,
|
||||
"ExpectedInstructionCount": 5,
|
||||
"Comment": "GROUP1 0x83 /7",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x27, x4",
|
||||
"sub x26, x27, #0x1 (1)",
|
||||
"cmp x27, #0x1 (1)",
|
||||
"subs x26, x27, #0x1 (1)",
|
||||
"mrs x20, nzcv",
|
||||
"eor w20, w20, #0x20000000",
|
||||
"msr nzcv, x20"
|
||||
]
|
||||
},
|
||||
"add ax, -1": {
|
||||
"ExpectedInstructionCount": 8,
|
||||
"ExpectedInstructionCount": 6,
|
||||
"Comment": "GROUP1 0x83 /0",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0xffff",
|
||||
"mov x21, x4",
|
||||
"add w26, w21, w20",
|
||||
"mov x4, x21",
|
||||
"bfxil x4, x26, #0, #16",
|
||||
"eor w27, w21, #0xffff",
|
||||
"lsl w0, w21, #16",
|
||||
"cmn w0, w20, lsl #16"
|
||||
"eor w27, w4, #0xffff",
|
||||
"lsl w0, w4, #16",
|
||||
"cmn w0, w20, lsl #16",
|
||||
"add w26, w4, w20",
|
||||
"bfxil x4, x26, #0, #16"
|
||||
]
|
||||
},
|
||||
"add eax, -1": {
|
||||
"ExpectedInstructionCount": 6,
|
||||
"ExpectedInstructionCount": 4,
|
||||
"Comment": "GROUP1 0x83 /0",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0xffffffff",
|
||||
"mov x21, x4",
|
||||
"add w4, w21, w20",
|
||||
"eor w27, w21, w20",
|
||||
"mov x26, x4",
|
||||
"cmn w21, w20"
|
||||
"eor w27, w4, w20",
|
||||
"adds w26, w4, w20",
|
||||
"mov x4, x26"
|
||||
]
|
||||
},
|
||||
"add rax, -1": {
|
||||
"ExpectedInstructionCount": 6,
|
||||
"ExpectedInstructionCount": 4,
|
||||
"Comment": "GROUP1 0x83 /0",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x20, #0xffffffffffffffff",
|
||||
"mov x21, x4",
|
||||
"sub x4, x21, #0x1 (1)",
|
||||
"eor w27, w21, w20",
|
||||
"mov x26, x4",
|
||||
"cmn x21, x20"
|
||||
"eor w27, w4, w20",
|
||||
"adds x26, x4, x20",
|
||||
"mov x4, x26"
|
||||
]
|
||||
},
|
||||
"or eax, -1": {
|
||||
@ -996,8 +968,8 @@
|
||||
"Comment": "GROUP1 0x83 /4",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0xffffffff",
|
||||
"ands w4, w4, w20",
|
||||
"mov x26, x4"
|
||||
"ands w26, w4, w20",
|
||||
"mov x4, x26"
|
||||
]
|
||||
},
|
||||
"and rax, -1": {
|
||||
@ -1005,37 +977,33 @@
|
||||
"Comment": "GROUP1 0x83 /4",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x20, #0xffffffffffffffff",
|
||||
"ands x4, x4, x20",
|
||||
"mov x26, x4"
|
||||
"ands x26, x4, x20",
|
||||
"mov x4, x26"
|
||||
]
|
||||
},
|
||||
"sub eax, -1": {
|
||||
"ExpectedInstructionCount": 9,
|
||||
"ExpectedInstructionCount": 7,
|
||||
"Comment": "GROUP1 0x83 /5",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0xffffffff",
|
||||
"mov x21, x4",
|
||||
"sub w4, w21, w20",
|
||||
"eor w27, w21, w20",
|
||||
"mov x26, x4",
|
||||
"cmp w21, w20",
|
||||
"eor w27, w4, w20",
|
||||
"subs w26, w4, w20",
|
||||
"mrs x20, nzcv",
|
||||
"eor w20, w20, #0x20000000",
|
||||
"mov x4, x26",
|
||||
"msr nzcv, x20"
|
||||
]
|
||||
},
|
||||
"sub rax, -1": {
|
||||
"ExpectedInstructionCount": 9,
|
||||
"ExpectedInstructionCount": 7,
|
||||
"Comment": "GROUP1 0x83 /5",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x20, #0xffffffffffffffff",
|
||||
"mov x21, x4",
|
||||
"sub x4, x21, x20",
|
||||
"eor w27, w21, w20",
|
||||
"mov x26, x4",
|
||||
"cmp x21, x20",
|
||||
"eor w27, w4, w20",
|
||||
"subs x26, x4, x20",
|
||||
"mrs x20, nzcv",
|
||||
"eor w20, w20, #0x20000000",
|
||||
"mov x4, x26",
|
||||
"msr nzcv, x20"
|
||||
]
|
||||
},
|
||||
@ -1060,26 +1028,24 @@
|
||||
]
|
||||
},
|
||||
"cmp eax, -1": {
|
||||
"ExpectedInstructionCount": 7,
|
||||
"ExpectedInstructionCount": 6,
|
||||
"Comment": "GROUP1 0x83 /7",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0xffffffff",
|
||||
"sub w26, w4, w20",
|
||||
"eor w27, w4, w20",
|
||||
"cmp w4, w20",
|
||||
"subs w26, w4, w20",
|
||||
"mrs x20, nzcv",
|
||||
"eor w20, w20, #0x20000000",
|
||||
"msr nzcv, x20"
|
||||
]
|
||||
},
|
||||
"cmp rax, -1": {
|
||||
"ExpectedInstructionCount": 7,
|
||||
"ExpectedInstructionCount": 6,
|
||||
"Comment": "GROUP1 0x83 /7",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x20, #0xffffffffffffffff",
|
||||
"sub x26, x4, x20",
|
||||
"eor w27, w4, w20",
|
||||
"cmp x4, x20",
|
||||
"subs x26, x4, x20",
|
||||
"mrs x20, nzcv",
|
||||
"eor w20, w20, #0x20000000",
|
||||
"msr nzcv, x20"
|
||||
@ -2697,11 +2663,11 @@
|
||||
"Comment": "GROUP2 0xf6 /3",
|
||||
"ExpectedArm64ASM": [
|
||||
"uxtb w27, w7",
|
||||
"neg w26, w27",
|
||||
"bfxil x7, x26, #0, #8",
|
||||
"cmp wzr, w27, lsl #24",
|
||||
"neg w26, w27",
|
||||
"mrs x20, nzcv",
|
||||
"eor w20, w20, #0x20000000",
|
||||
"bfxil x7, x26, #0, #8",
|
||||
"msr nzcv, x20"
|
||||
]
|
||||
},
|
||||
@ -2838,37 +2804,35 @@
|
||||
"Comment": "GROUP2 0xf7 /2",
|
||||
"ExpectedArm64ASM": [
|
||||
"uxth w27, w7",
|
||||
"neg w26, w27",
|
||||
"bfxil x7, x26, #0, #16",
|
||||
"cmp wzr, w27, lsl #16",
|
||||
"neg w26, w27",
|
||||
"mrs x20, nzcv",
|
||||
"eor w20, w20, #0x20000000",
|
||||
"bfxil x7, x26, #0, #16",
|
||||
"msr nzcv, x20"
|
||||
]
|
||||
},
|
||||
"neg ebx": {
|
||||
"ExpectedInstructionCount": 7,
|
||||
"ExpectedInstructionCount": 6,
|
||||
"Comment": "GROUP2 0xf7 /2",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w27, w7",
|
||||
"neg w7, w27",
|
||||
"mov x26, x7",
|
||||
"cmp wzr, w27",
|
||||
"negs w26, w27",
|
||||
"mrs x20, nzcv",
|
||||
"eor w20, w20, #0x20000000",
|
||||
"mov x7, x26",
|
||||
"msr nzcv, x20"
|
||||
]
|
||||
},
|
||||
"neg rbx": {
|
||||
"ExpectedInstructionCount": 7,
|
||||
"ExpectedInstructionCount": 6,
|
||||
"Comment": "GROUP2 0xf7 /2",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x27, x7",
|
||||
"neg x7, x27",
|
||||
"mov x26, x7",
|
||||
"cmp xzr, x27",
|
||||
"negs x26, x27",
|
||||
"mrs x20, nzcv",
|
||||
"eor w20, w20, #0x20000000",
|
||||
"mov x7, x26",
|
||||
"msr nzcv, x20"
|
||||
]
|
||||
},
|
||||
@ -3098,13 +3062,13 @@
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0x1",
|
||||
"uxtb w27, w4",
|
||||
"add w26, w27, #0x1 (1)",
|
||||
"bfxil x4, x26, #0, #8",
|
||||
"cset w21, hs",
|
||||
"lsl w0, w27, #24",
|
||||
"cmn w0, w20, lsl #24",
|
||||
"add w26, w27, #0x1 (1)",
|
||||
"mrs x20, nzcv",
|
||||
"bfi w20, w21, #29, #1",
|
||||
"bfxil x4, x26, #0, #8",
|
||||
"msr nzcv, x20"
|
||||
]
|
||||
},
|
||||
@ -3114,13 +3078,13 @@
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0x1",
|
||||
"uxtb w27, w4",
|
||||
"sub w26, w27, #0x1 (1)",
|
||||
"bfxil x4, x26, #0, #8",
|
||||
"cset w21, hs",
|
||||
"lsl w0, w27, #24",
|
||||
"cmp w0, w20, lsl #24",
|
||||
"sub w26, w27, #0x1 (1)",
|
||||
"mrs x20, nzcv",
|
||||
"bfi w20, w21, #29, #1",
|
||||
"bfxil x4, x26, #0, #8",
|
||||
"msr nzcv, x20"
|
||||
]
|
||||
},
|
||||
@ -3130,45 +3094,43 @@
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0x1",
|
||||
"uxth w27, w4",
|
||||
"add w26, w27, #0x1 (1)",
|
||||
"bfxil x4, x26, #0, #16",
|
||||
"cset w21, hs",
|
||||
"lsl w0, w27, #16",
|
||||
"cmn w0, w20, lsl #16",
|
||||
"add w26, w27, #0x1 (1)",
|
||||
"mrs x20, nzcv",
|
||||
"bfi w20, w21, #29, #1",
|
||||
"bfxil x4, x26, #0, #16",
|
||||
"msr nzcv, x20"
|
||||
]
|
||||
},
|
||||
"inc eax": {
|
||||
"ExpectedInstructionCount": 10,
|
||||
"ExpectedInstructionCount": 9,
|
||||
"Comment": "GROUP4 0xfe /0",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x27, x4",
|
||||
"add w4, w27, #0x1 (1)",
|
||||
"mov x26, x4",
|
||||
"cset w20, hs",
|
||||
"cmn w27, #0x1 (1)",
|
||||
"adds w26, w27, #0x1 (1)",
|
||||
"mrs x21, nzcv",
|
||||
"mov w0, w21",
|
||||
"bfi w0, w20, #29, #1",
|
||||
"mov w20, w0",
|
||||
"mov x4, x26",
|
||||
"msr nzcv, x20"
|
||||
]
|
||||
},
|
||||
"inc rax": {
|
||||
"ExpectedInstructionCount": 10,
|
||||
"ExpectedInstructionCount": 9,
|
||||
"Comment": "GROUP4 0xfe /0",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x27, x4",
|
||||
"add x4, x27, #0x1 (1)",
|
||||
"mov x26, x4",
|
||||
"cset w20, hs",
|
||||
"cmn x27, #0x1 (1)",
|
||||
"adds x26, x27, #0x1 (1)",
|
||||
"mrs x21, nzcv",
|
||||
"mov w0, w21",
|
||||
"bfi w0, w20, #29, #1",
|
||||
"mov w20, w0",
|
||||
"mov x4, x26",
|
||||
"msr nzcv, x20"
|
||||
]
|
||||
},
|
||||
@ -3178,45 +3140,43 @@
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0x1",
|
||||
"uxth w27, w4",
|
||||
"sub w26, w27, #0x1 (1)",
|
||||
"bfxil x4, x26, #0, #16",
|
||||
"cset w21, hs",
|
||||
"lsl w0, w27, #16",
|
||||
"cmp w0, w20, lsl #16",
|
||||
"sub w26, w27, #0x1 (1)",
|
||||
"mrs x20, nzcv",
|
||||
"bfi w20, w21, #29, #1",
|
||||
"bfxil x4, x26, #0, #16",
|
||||
"msr nzcv, x20"
|
||||
]
|
||||
},
|
||||
"dec eax": {
|
||||
"ExpectedInstructionCount": 10,
|
||||
"ExpectedInstructionCount": 9,
|
||||
"Comment": "GROUP4 0xfe /1",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x27, x4",
|
||||
"sub w4, w27, #0x1 (1)",
|
||||
"mov x26, x4",
|
||||
"cset w20, hs",
|
||||
"cmp w27, #0x1 (1)",
|
||||
"subs w26, w27, #0x1 (1)",
|
||||
"mrs x21, nzcv",
|
||||
"mov w0, w21",
|
||||
"bfi w0, w20, #29, #1",
|
||||
"mov w20, w0",
|
||||
"mov x4, x26",
|
||||
"msr nzcv, x20"
|
||||
]
|
||||
},
|
||||
"dec rax": {
|
||||
"ExpectedInstructionCount": 10,
|
||||
"ExpectedInstructionCount": 9,
|
||||
"Comment": "GROUP4 0xfe /1",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x27, x4",
|
||||
"sub x4, x27, #0x1 (1)",
|
||||
"mov x26, x4",
|
||||
"cset w20, hs",
|
||||
"cmp x27, #0x1 (1)",
|
||||
"subs x26, x27, #0x1 (1)",
|
||||
"mrs x21, nzcv",
|
||||
"mov w0, w21",
|
||||
"bfi w0, w20, #29, #1",
|
||||
"mov w20, w0",
|
||||
"mov x4, x26",
|
||||
"msr nzcv, x20"
|
||||
]
|
||||
},
|
||||
|
||||
@ -272,29 +272,28 @@
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0x1",
|
||||
"uxth w27, w4",
|
||||
"add w26, w27, #0x1 (1)",
|
||||
"bfxil w4, w26, #0, #16",
|
||||
"cset w21, hs",
|
||||
"lsl w0, w27, #16",
|
||||
"cmn w0, w20, lsl #16",
|
||||
"add w26, w27, #0x1 (1)",
|
||||
"mrs x20, nzcv",
|
||||
"bfi w20, w21, #29, #1",
|
||||
"bfxil w4, w26, #0, #16",
|
||||
"msr nzcv, x20"
|
||||
]
|
||||
},
|
||||
"inc eax": {
|
||||
"ExpectedInstructionCount": 10,
|
||||
"ExpectedInstructionCount": 9,
|
||||
"Comment": "0x40",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w27, w4",
|
||||
"add w4, w27, #0x1 (1)",
|
||||
"mov w26, w4",
|
||||
"cset w20, hs",
|
||||
"cmn w27, #0x1 (1)",
|
||||
"adds w26, w27, #0x1 (1)",
|
||||
"mrs x21, nzcv",
|
||||
"mov w0, w21",
|
||||
"bfi w0, w20, #29, #1",
|
||||
"mov w20, w0",
|
||||
"mov w4, w26",
|
||||
"msr nzcv, x20"
|
||||
]
|
||||
},
|
||||
@ -304,13 +303,13 @@
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0x1",
|
||||
"uxth w27, w4",
|
||||
"sub w26, w27, #0x1 (1)",
|
||||
"bfxil w4, w26, #0, #16",
|
||||
"cset w21, hs",
|
||||
"lsl w0, w27, #16",
|
||||
"cmp w0, w20, lsl #16",
|
||||
"sub w26, w27, #0x1 (1)",
|
||||
"mrs x20, nzcv",
|
||||
"bfi w20, w21, #29, #1",
|
||||
"bfxil w4, w26, #0, #16",
|
||||
"msr nzcv, x20"
|
||||
]
|
||||
},
|
||||
@ -329,18 +328,17 @@
|
||||
]
|
||||
},
|
||||
"dec eax": {
|
||||
"ExpectedInstructionCount": 10,
|
||||
"ExpectedInstructionCount": 9,
|
||||
"Comment": "0x48",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w27, w4",
|
||||
"sub w4, w27, #0x1 (1)",
|
||||
"mov w26, w4",
|
||||
"cset w20, hs",
|
||||
"cmp w27, #0x1 (1)",
|
||||
"subs w26, w27, #0x1 (1)",
|
||||
"mrs x21, nzcv",
|
||||
"mov w0, w21",
|
||||
"bfi w0, w20, #29, #1",
|
||||
"mov w20, w0",
|
||||
"mov w4, w26",
|
||||
"msr nzcv, x20"
|
||||
]
|
||||
},
|
||||
|
||||
@ -1888,10 +1888,10 @@
|
||||
"uxtb w20, w7",
|
||||
"uxtb w21, w4",
|
||||
"uxtb x22, w4",
|
||||
"sub x26, x22, x21",
|
||||
"eor w27, w22, w21",
|
||||
"lsl w0, w22, #24",
|
||||
"cmp w0, w21, lsl #24",
|
||||
"sub w26, w22, w21",
|
||||
"mrs x21, nzcv",
|
||||
"eor w21, w21, #0x20000000",
|
||||
"msr nzcv, x21",
|
||||
@ -1908,10 +1908,10 @@
|
||||
"casalb w1, w20, [x4]",
|
||||
"mov w20, w1",
|
||||
"bfxil x4, x20, #0, #8",
|
||||
"sub w26, w21, w20",
|
||||
"eor w27, w21, w20",
|
||||
"lsl w0, w21, #24",
|
||||
"cmp w0, w20, lsl #24",
|
||||
"sub w26, w21, w20",
|
||||
"mrs x20, nzcv",
|
||||
"eor w20, w20, #0x20000000",
|
||||
"msr nzcv, x20"
|
||||
@ -1924,10 +1924,10 @@
|
||||
"uxth w20, w7",
|
||||
"uxth w21, w4",
|
||||
"uxth x22, w4",
|
||||
"sub x26, x22, x21",
|
||||
"eor w27, w22, w21",
|
||||
"lsl w0, w22, #16",
|
||||
"cmp w0, w21, lsl #16",
|
||||
"sub w26, w22, w21",
|
||||
"mrs x21, nzcv",
|
||||
"eor w21, w21, #0x20000000",
|
||||
"msr nzcv, x21",
|
||||
@ -1944,25 +1944,24 @@
|
||||
"casalh w1, w20, [x4]",
|
||||
"mov w20, w1",
|
||||
"bfxil x4, x20, #0, #16",
|
||||
"sub w26, w21, w20",
|
||||
"eor w27, w21, w20",
|
||||
"lsl w0, w21, #16",
|
||||
"cmp w0, w20, lsl #16",
|
||||
"sub w26, w21, w20",
|
||||
"mrs x20, nzcv",
|
||||
"eor w20, w20, #0x20000000",
|
||||
"msr nzcv, x20"
|
||||
]
|
||||
},
|
||||
"cmpxchg eax, ebx": {
|
||||
"ExpectedInstructionCount": 10,
|
||||
"ExpectedInstructionCount": 9,
|
||||
"Comment": "0x0f 0xb1",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, w7",
|
||||
"mov w21, w4",
|
||||
"mov w22, w4",
|
||||
"sub x26, x22, x21",
|
||||
"eor w27, w22, w21",
|
||||
"cmp w22, w21",
|
||||
"subs w26, w22, w21",
|
||||
"mrs x21, nzcv",
|
||||
"eor w21, w21, #0x20000000",
|
||||
"msr nzcv, x21",
|
||||
@ -1970,7 +1969,7 @@
|
||||
]
|
||||
},
|
||||
"cmpxchg [rax], ebx": {
|
||||
"ExpectedInstructionCount": 13,
|
||||
"ExpectedInstructionCount": 12,
|
||||
"Comment": "0x0f 0xb1",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, w7",
|
||||
@ -1980,22 +1979,20 @@
|
||||
"mov w20, w1",
|
||||
"cmp w20, w21",
|
||||
"csel x4, x4, x20, eq",
|
||||
"sub w26, w21, w20",
|
||||
"eor w27, w21, w20",
|
||||
"cmp w21, w20",
|
||||
"subs w26, w21, w20",
|
||||
"mrs x20, nzcv",
|
||||
"eor w20, w20, #0x20000000",
|
||||
"msr nzcv, x20"
|
||||
]
|
||||
},
|
||||
"cmpxchg rax, rbx": {
|
||||
"ExpectedInstructionCount": 8,
|
||||
"ExpectedInstructionCount": 7,
|
||||
"Comment": "0x0f 0xb1",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x20, x7",
|
||||
"sub x26, x4, x4",
|
||||
"mov w27, #0x0",
|
||||
"cmp x4, x4",
|
||||
"subs x26, x4, x4",
|
||||
"mrs x21, nzcv",
|
||||
"eor w21, w21, #0x20000000",
|
||||
"msr nzcv, x21",
|
||||
@ -2003,16 +2000,15 @@
|
||||
]
|
||||
},
|
||||
"cmpxchg [rax], rbx": {
|
||||
"ExpectedInstructionCount": 10,
|
||||
"ExpectedInstructionCount": 9,
|
||||
"Comment": "0x0f 0xb1",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x20, x4",
|
||||
"mov x1, x20",
|
||||
"casal x1, x7, [x20]",
|
||||
"mov x4, x1",
|
||||
"sub x26, x20, x4",
|
||||
"eor w27, w20, w4",
|
||||
"cmp x20, x4",
|
||||
"subs x26, x20, x4",
|
||||
"mrs x20, nzcv",
|
||||
"eor w20, w20, #0x20000000",
|
||||
"msr nzcv, x20"
|
||||
@ -2543,12 +2539,12 @@
|
||||
"ExpectedArm64ASM": [
|
||||
"uxtb w20, w4",
|
||||
"uxtb w21, w7",
|
||||
"add w26, w20, w21",
|
||||
"bfxil x7, x20, #0, #8",
|
||||
"bfxil x4, x26, #0, #8",
|
||||
"eor w27, w20, w21",
|
||||
"lsl w0, w20, #24",
|
||||
"cmn w0, w21, lsl #24"
|
||||
"cmn w0, w21, lsl #24",
|
||||
"add w26, w20, w21",
|
||||
"bfxil x7, x20, #0, #8",
|
||||
"bfxil x4, x26, #0, #8"
|
||||
]
|
||||
},
|
||||
"xadd [rax], bl": {
|
||||
@ -2558,10 +2554,10 @@
|
||||
"uxtb w20, w7",
|
||||
"ldaddalb w20, w21, [x4]",
|
||||
"bfxil x7, x21, #0, #8",
|
||||
"add w26, w21, w20",
|
||||
"eor w27, w21, w20",
|
||||
"lsl w0, w21, #24",
|
||||
"cmn w0, w20, lsl #24"
|
||||
"cmn w0, w20, lsl #24",
|
||||
"add w26, w21, w20"
|
||||
]
|
||||
},
|
||||
"xadd ax, bx": {
|
||||
@ -2570,12 +2566,12 @@
|
||||
"ExpectedArm64ASM": [
|
||||
"uxth w20, w4",
|
||||
"uxth w21, w7",
|
||||
"add w26, w20, w21",
|
||||
"bfxil x7, x20, #0, #16",
|
||||
"bfxil x4, x26, #0, #16",
|
||||
"eor w27, w20, w21",
|
||||
"lsl w0, w20, #16",
|
||||
"cmn w0, w21, lsl #16"
|
||||
"cmn w0, w21, lsl #16",
|
||||
"add w26, w20, w21",
|
||||
"bfxil x7, x20, #0, #16",
|
||||
"bfxil x4, x26, #0, #16"
|
||||
]
|
||||
},
|
||||
"xadd [rax], bx": {
|
||||
@ -2585,58 +2581,53 @@
|
||||
"uxth w20, w7",
|
||||
"ldaddalh w20, w21, [x4]",
|
||||
"bfxil x7, x21, #0, #16",
|
||||
"add w26, w21, w20",
|
||||
"eor w27, w21, w20",
|
||||
"lsl w0, w21, #16",
|
||||
"cmn w0, w20, lsl #16"
|
||||
"cmn w0, w20, lsl #16",
|
||||
"add w26, w21, w20"
|
||||
]
|
||||
},
|
||||
"xadd eax, ebx": {
|
||||
"ExpectedInstructionCount": 7,
|
||||
"ExpectedInstructionCount": 6,
|
||||
"Comment": "0x0f 0xc1",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, w4",
|
||||
"mov w21, w7",
|
||||
"add w4, w20, w21",
|
||||
"mov x7, x20",
|
||||
"eor w27, w20, w21",
|
||||
"mov x26, x4",
|
||||
"cmn w20, w21"
|
||||
"adds w26, w20, w21",
|
||||
"mov x7, x20",
|
||||
"mov x4, x26"
|
||||
]
|
||||
},
|
||||
"xadd [rax], ebx": {
|
||||
"ExpectedInstructionCount": 5,
|
||||
"ExpectedInstructionCount": 4,
|
||||
"Comment": "0x0f 0xc1",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, w7",
|
||||
"ldaddal w20, w7, [x4]",
|
||||
"add w26, w7, w20",
|
||||
"eor w27, w7, w20",
|
||||
"cmn w7, w20"
|
||||
"adds w26, w7, w20"
|
||||
]
|
||||
},
|
||||
"xadd rax, rbx": {
|
||||
"ExpectedInstructionCount": 7,
|
||||
"ExpectedInstructionCount": 5,
|
||||
"Comment": "0x0f 0xc1",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x20, x4",
|
||||
"mov x21, x7",
|
||||
"add x4, x20, x21",
|
||||
"eor w27, w20, w7",
|
||||
"adds x26, x20, x7",
|
||||
"mov x7, x20",
|
||||
"eor w27, w20, w21",
|
||||
"mov x26, x4",
|
||||
"cmn x20, x21"
|
||||
"mov x4, x26"
|
||||
]
|
||||
},
|
||||
"xadd [rax], rbx": {
|
||||
"ExpectedInstructionCount": 5,
|
||||
"ExpectedInstructionCount": 4,
|
||||
"Comment": "0x0f 0xc1",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov x20, x7",
|
||||
"ldaddal x20, x7, [x4]",
|
||||
"add x26, x7, x20",
|
||||
"eor w27, w7, w20",
|
||||
"cmn x7, x20"
|
||||
"adds x26, x7, x20"
|
||||
]
|
||||
},
|
||||
"cmpps xmm0, xmm1, 0": {
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user