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https://github.com/FEX-Emu/FEX.git
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Merge pull request #3736 from Sonicadvance1/avx_9
AVX128: Some pun pickles, moves and conversions
This commit is contained in:
Ryan Houdek
GitHub
commit
7bbbd95775
@ -36,7 +36,6 @@ namespace CodeSerialize {
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namespace CPU {
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struct CPUBackendFeatures {
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bool SupportsFlags = false;
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bool SupportsSaturatingRoundingShifts = false;
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bool SupportsVTBL2 = false;
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};
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@ -887,7 +887,6 @@ fextl::unique_ptr<CPUBackend> CreateArm64JITCore(FEXCore::Context::ContextImpl*
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CPUBackendFeatures GetArm64JITBackendFeatures() {
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return CPUBackendFeatures {
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.SupportsFlags = true,
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.SupportsSaturatingRoundingShifts = true,
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.SupportsVTBL2 = true,
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};
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}
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@ -1012,6 +1012,23 @@ public:
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void AVX128_VMOVSHDUP(OpcodeArgs);
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template<size_t ElementSize>
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void AVX128_VBROADCAST(OpcodeArgs);
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template<size_t ElementSize>
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void AVX128_VPUNPCKL(OpcodeArgs);
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template<size_t ElementSize>
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void AVX128_VPUNPCKH(OpcodeArgs);
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void AVX128_MOVVectorUnaligned(OpcodeArgs);
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template<size_t DstElementSize>
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void AVX128_InsertCVTGPR_To_FPR(OpcodeArgs);
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template<size_t SrcElementSize, bool HostRoundingMode>
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void AVX128_CVTFPR_To_GPR(OpcodeArgs);
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void AVX128_VANDN(OpcodeArgs);
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template<size_t ElementSize>
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void AVX128_VPACKSS(OpcodeArgs);
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template<size_t ElementSize>
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void AVX128_VPACKUS(OpcodeArgs);
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Ref AVX128_PSIGNImpl(size_t ElementSize, Ref Src1, Ref Src2);
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template<size_t ElementSize>
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void AVX128_VPSIGN(OpcodeArgs);
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// End of AVX 128-bit implementation
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@ -40,11 +40,11 @@ void OpDispatchBuilder::InstallAVX128Handlers() {
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{OPD(1, 0b00, 0x13), 1, &OpDispatchBuilder::AVX128_VMOVLP},
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{OPD(1, 0b01, 0x13), 1, &OpDispatchBuilder::AVX128_VMOVLP},
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// TODO: {OPD(1, 0b00, 0x14), 1, &OpDispatchBuilder::VPUNPCKLOp<4>},
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// TODO: {OPD(1, 0b01, 0x14), 1, &OpDispatchBuilder::VPUNPCKLOp<8>},
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{OPD(1, 0b00, 0x14), 1, &OpDispatchBuilder::AVX128_VPUNPCKL<4>},
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{OPD(1, 0b01, 0x14), 1, &OpDispatchBuilder::AVX128_VPUNPCKL<8>},
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// TODO: {OPD(1, 0b00, 0x15), 1, &OpDispatchBuilder::VPUNPCKHOp<4>},
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// TODO: {OPD(1, 0b01, 0x15), 1, &OpDispatchBuilder::VPUNPCKHOp<8>},
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{OPD(1, 0b00, 0x15), 1, &OpDispatchBuilder::AVX128_VPUNPCKH<4>},
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{OPD(1, 0b01, 0x15), 1, &OpDispatchBuilder::AVX128_VPUNPCKH<8>},
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{OPD(1, 0b00, 0x16), 1, &OpDispatchBuilder::AVX128_VMOVHP},
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{OPD(1, 0b01, 0x16), 1, &OpDispatchBuilder::AVX128_VMOVHP},
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@ -57,17 +57,17 @@ void OpDispatchBuilder::InstallAVX128Handlers() {
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{OPD(1, 0b00, 0x29), 1, &OpDispatchBuilder::AVX128_VMOVAPS},
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{OPD(1, 0b01, 0x29), 1, &OpDispatchBuilder::AVX128_VMOVAPS},
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// TODO: {OPD(1, 0b10, 0x2A), 1, &OpDispatchBuilder::AVXInsertCVTGPR_To_FPR<4>},
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// TODO: {OPD(1, 0b11, 0x2A), 1, &OpDispatchBuilder::AVXInsertCVTGPR_To_FPR<8>},
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{OPD(1, 0b10, 0x2A), 1, &OpDispatchBuilder::AVX128_InsertCVTGPR_To_FPR<4>},
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{OPD(1, 0b11, 0x2A), 1, &OpDispatchBuilder::AVX128_InsertCVTGPR_To_FPR<8>},
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{OPD(1, 0b00, 0x2B), 1, &OpDispatchBuilder::AVX128_MOVVectorNT},
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{OPD(1, 0b01, 0x2B), 1, &OpDispatchBuilder::AVX128_MOVVectorNT},
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// TODO: {OPD(1, 0b10, 0x2C), 1, &OpDispatchBuilder::CVTFPR_To_GPR<4, false>},
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// TODO: {OPD(1, 0b11, 0x2C), 1, &OpDispatchBuilder::CVTFPR_To_GPR<8, false>},
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{OPD(1, 0b10, 0x2C), 1, &OpDispatchBuilder::AVX128_CVTFPR_To_GPR<4, false>},
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{OPD(1, 0b11, 0x2C), 1, &OpDispatchBuilder::AVX128_CVTFPR_To_GPR<8, false>},
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// TODO: {OPD(1, 0b10, 0x2D), 1, &OpDispatchBuilder::CVTFPR_To_GPR<4, true>},
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// TODO: {OPD(1, 0b11, 0x2D), 1, &OpDispatchBuilder::CVTFPR_To_GPR<8, true>},
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{OPD(1, 0b10, 0x2D), 1, &OpDispatchBuilder::AVX128_CVTFPR_To_GPR<4, true>},
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{OPD(1, 0b11, 0x2D), 1, &OpDispatchBuilder::AVX128_CVTFPR_To_GPR<8, true>},
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// TODO: {OPD(1, 0b00, 0x2E), 1, &OpDispatchBuilder::UCOMISxOp<4>},
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// TODO: {OPD(1, 0b01, 0x2E), 1, &OpDispatchBuilder::UCOMISxOp<8>},
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@ -91,8 +91,8 @@ void OpDispatchBuilder::InstallAVX128Handlers() {
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{OPD(1, 0b00, 0x54), 1, &OpDispatchBuilder::AVX128_VectorALU<IR::OP_VAND, 16>},
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{OPD(1, 0b01, 0x54), 1, &OpDispatchBuilder::AVX128_VectorALU<IR::OP_VAND, 16>},
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// TODO: {OPD(1, 0b00, 0x55), 1, &OpDispatchBuilder::VANDNOp},
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// TODO: {OPD(1, 0b01, 0x55), 1, &OpDispatchBuilder::VANDNOp},
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{OPD(1, 0b00, 0x55), 1, &OpDispatchBuilder::AVX128_VANDN},
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{OPD(1, 0b01, 0x55), 1, &OpDispatchBuilder::AVX128_VANDN},
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{OPD(1, 0b00, 0x56), 1, &OpDispatchBuilder::AVX128_VectorALU<IR::OP_VOR, 16>},
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{OPD(1, 0b01, 0x56), 1, &OpDispatchBuilder::AVX128_VectorALU<IR::OP_VOR, 16>},
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@ -139,20 +139,20 @@ void OpDispatchBuilder::InstallAVX128Handlers() {
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// TODO: {OPD(1, 0b10, 0x5F), 1, &OpDispatchBuilder::AVXVectorScalarInsertALUOp<IR::OP_VFMAXSCALARINSERT, 4>},
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// TODO: {OPD(1, 0b11, 0x5F), 1, &OpDispatchBuilder::AVXVectorScalarInsertALUOp<IR::OP_VFMAXSCALARINSERT, 8>},
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// TODO: {OPD(1, 0b01, 0x60), 1, &OpDispatchBuilder::VPUNPCKLOp<1>},
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// TODO: {OPD(1, 0b01, 0x61), 1, &OpDispatchBuilder::VPUNPCKLOp<2>},
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// TODO: {OPD(1, 0b01, 0x62), 1, &OpDispatchBuilder::VPUNPCKLOp<4>},
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// TODO: {OPD(1, 0b01, 0x63), 1, &OpDispatchBuilder::VPACKSSOp<2>},
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{OPD(1, 0b01, 0x60), 1, &OpDispatchBuilder::AVX128_VPUNPCKL<1>},
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{OPD(1, 0b01, 0x61), 1, &OpDispatchBuilder::AVX128_VPUNPCKL<2>},
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{OPD(1, 0b01, 0x62), 1, &OpDispatchBuilder::AVX128_VPUNPCKL<4>},
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{OPD(1, 0b01, 0x63), 1, &OpDispatchBuilder::AVX128_VPACKSS<2>},
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{OPD(1, 0b01, 0x64), 1, &OpDispatchBuilder::AVX128_VectorALU<IR::OP_VCMPGT, 1>},
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{OPD(1, 0b01, 0x65), 1, &OpDispatchBuilder::AVX128_VectorALU<IR::OP_VCMPGT, 2>},
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{OPD(1, 0b01, 0x66), 1, &OpDispatchBuilder::AVX128_VectorALU<IR::OP_VCMPGT, 4>},
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// TODO: {OPD(1, 0b01, 0x67), 1, &OpDispatchBuilder::VPACKUSOp<2>},
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// TODO: {OPD(1, 0b01, 0x68), 1, &OpDispatchBuilder::VPUNPCKHOp<1>},
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// TODO: {OPD(1, 0b01, 0x69), 1, &OpDispatchBuilder::VPUNPCKHOp<2>},
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// TODO: {OPD(1, 0b01, 0x6A), 1, &OpDispatchBuilder::VPUNPCKHOp<4>},
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// TODO: {OPD(1, 0b01, 0x6B), 1, &OpDispatchBuilder::VPACKSSOp<4>},
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// TODO: {OPD(1, 0b01, 0x6C), 1, &OpDispatchBuilder::VPUNPCKLOp<8>},
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// TODO: {OPD(1, 0b01, 0x6D), 1, &OpDispatchBuilder::VPUNPCKHOp<8>},
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{OPD(1, 0b01, 0x67), 1, &OpDispatchBuilder::AVX128_VPACKUS<2>},
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{OPD(1, 0b01, 0x68), 1, &OpDispatchBuilder::AVX128_VPUNPCKH<1>},
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{OPD(1, 0b01, 0x69), 1, &OpDispatchBuilder::AVX128_VPUNPCKH<2>},
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{OPD(1, 0b01, 0x6A), 1, &OpDispatchBuilder::AVX128_VPUNPCKH<4>},
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{OPD(1, 0b01, 0x6B), 1, &OpDispatchBuilder::AVX128_VPACKSS<4>},
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{OPD(1, 0b01, 0x6C), 1, &OpDispatchBuilder::AVX128_VPUNPCKL<8>},
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{OPD(1, 0b01, 0x6D), 1, &OpDispatchBuilder::AVX128_VPUNPCKH<8>},
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// TODO: {OPD(1, 0b01, 0x6E), 1, &OpDispatchBuilder::MOVBetweenGPR_FPR},
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{OPD(1, 0b01, 0x6F), 1, &OpDispatchBuilder::AVX128_VMOVAPS},
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@ -208,7 +208,7 @@ void OpDispatchBuilder::InstallAVX128Handlers() {
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{OPD(1, 0b01, 0xDC), 1, &OpDispatchBuilder::AVX128_VectorALU<IR::OP_VUQADD, 1>},
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{OPD(1, 0b01, 0xDD), 1, &OpDispatchBuilder::AVX128_VectorALU<IR::OP_VUQADD, 2>},
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{OPD(1, 0b01, 0xDE), 1, &OpDispatchBuilder::AVX128_VectorALU<IR::OP_VUMAX, 1>},
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// TODO: {OPD(1, 0b01, 0xDF), 1, &OpDispatchBuilder::VANDNOp},
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{OPD(1, 0b01, 0xDF), 1, &OpDispatchBuilder::AVX128_VANDN},
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{OPD(1, 0b01, 0xE0), 1, &OpDispatchBuilder::AVX128_VectorALU<IR::OP_VURAVG, 1>},
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// TODO: {OPD(1, 0b01, 0xE1), 1, &OpDispatchBuilder::VPSRAOp<2>},
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@ -232,7 +232,7 @@ void OpDispatchBuilder::InstallAVX128Handlers() {
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{OPD(1, 0b01, 0xEE), 1, &OpDispatchBuilder::AVX128_VectorALU<IR::OP_VSMAX, 2>},
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{OPD(1, 0b01, 0xEF), 1, &OpDispatchBuilder::AVX128_VectorALU<IR::OP_VXOR, 16>},
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// TODO: {OPD(1, 0b11, 0xF0), 1, &OpDispatchBuilder::MOVVectorUnalignedOp},
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{OPD(1, 0b11, 0xF0), 1, &OpDispatchBuilder::AVX128_MOVVectorUnaligned},
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// TODO: {OPD(1, 0b01, 0xF1), 1, &OpDispatchBuilder::VPSLLOp<2>},
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// TODO: {OPD(1, 0b01, 0xF2), 1, &OpDispatchBuilder::VPSLLOp<4>},
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// TODO: {OPD(1, 0b01, 0xF3), 1, &OpDispatchBuilder::VPSLLOp<8>},
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@ -259,9 +259,9 @@ void OpDispatchBuilder::InstallAVX128Handlers() {
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// TODO: {OPD(2, 0b01, 0x06), 1, &OpDispatchBuilder::VPHSUBOp<4>},
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// TODO: {OPD(2, 0b01, 0x07), 1, &OpDispatchBuilder::VPHSUBSWOp},
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// TODO: {OPD(2, 0b01, 0x08), 1, &OpDispatchBuilder::VPSIGN<1>},
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// TODO: {OPD(2, 0b01, 0x09), 1, &OpDispatchBuilder::VPSIGN<2>},
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// TODO: {OPD(2, 0b01, 0x0A), 1, &OpDispatchBuilder::VPSIGN<4>},
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{OPD(2, 0b01, 0x08), 1, &OpDispatchBuilder::AVX128_VPSIGN<1>},
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{OPD(2, 0b01, 0x09), 1, &OpDispatchBuilder::AVX128_VPSIGN<2>},
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{OPD(2, 0b01, 0x0A), 1, &OpDispatchBuilder::AVX128_VPSIGN<4>},
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// TODO: {OPD(2, 0b01, 0x0B), 1, &OpDispatchBuilder::VPMULHRSWOp},
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// TODO: {OPD(2, 0b01, 0x0C), 1, &OpDispatchBuilder::VPERMILRegOp<4>},
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// TODO: {OPD(2, 0b01, 0x0D), 1, &OpDispatchBuilder::VPERMILRegOp<8>},
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@ -287,7 +287,7 @@ void OpDispatchBuilder::InstallAVX128Handlers() {
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// TODO: {OPD(2, 0b01, 0x28), 1, &OpDispatchBuilder::VPMULLOp<4, true>},
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{OPD(2, 0b01, 0x29), 1, &OpDispatchBuilder::AVX128_VectorALU<IR::OP_VCMPEQ, 8>},
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{OPD(2, 0b01, 0x2A), 1, &OpDispatchBuilder::AVX128_MOVVectorNT},
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// TODO: {OPD(2, 0b01, 0x2B), 1, &OpDispatchBuilder::VPACKUSOp<4>},
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{OPD(2, 0b01, 0x2B), 1, &OpDispatchBuilder::AVX128_VPACKUS<4>},
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// TODO: {OPD(2, 0b01, 0x2C), 1, &OpDispatchBuilder::VMASKMOVOp<4, false>},
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// TODO: {OPD(2, 0b01, 0x2D), 1, &OpDispatchBuilder::VMASKMOVOp<8, false>},
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// TODO: {OPD(2, 0b01, 0x2E), 1, &OpDispatchBuilder::VMASKMOVOp<4, true>},
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@ -782,4 +782,123 @@ void OpDispatchBuilder::AVX128_VBROADCAST(OpcodeArgs) {
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AVX128_StoreResult_WithOpSize(Op, Op->Dest, Src);
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}
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template<size_t ElementSize>
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void OpDispatchBuilder::AVX128_VPUNPCKL(OpcodeArgs) {
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AVX128_VectorBinaryImpl(Op, GetSrcSize(Op), ElementSize,
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[this](size_t _ElementSize, Ref Src1, Ref Src2) { return _VZip(OpSize::i128Bit, _ElementSize, Src1, Src2); });
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}
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template<size_t ElementSize>
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void OpDispatchBuilder::AVX128_VPUNPCKH(OpcodeArgs) {
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AVX128_VectorBinaryImpl(Op, GetSrcSize(Op), ElementSize,
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[this](size_t _ElementSize, Ref Src1, Ref Src2) { return _VZip2(OpSize::i128Bit, _ElementSize, Src1, Src2); });
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}
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void OpDispatchBuilder::AVX128_MOVVectorUnaligned(OpcodeArgs) {
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const auto SrcSize = GetSrcSize(Op);
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const auto Is128Bit = SrcSize == Core::CPUState::XMM_SSE_REG_SIZE;
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if (!Is128Bit && Op->Dest.IsGPR() && Op->Src[0].IsGPR() && Op->Dest.Data.GPR.GPR == Op->Src[0].Data.GPR.GPR) {
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// Nop
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return;
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}
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auto Src = AVX128_LoadSource_WithOpSize(Op, Op->Src[0], Op->Flags, !Is128Bit);
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if (Is128Bit) {
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Src.High = LoadZeroVector(OpSize::i128Bit);
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}
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AVX128_StoreResult_WithOpSize(Op, Op->Dest, Src);
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}
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template<size_t DstElementSize>
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void OpDispatchBuilder::AVX128_InsertCVTGPR_To_FPR(OpcodeArgs) {
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const auto SrcSize = GetSrcSize(Op);
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const auto DstSize = GetDstSize(Op);
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const auto Is128Bit = DstSize == Core::CPUState::XMM_SSE_REG_SIZE;
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auto Src1 = AVX128_LoadSource_WithOpSize(Op, Op->Src[0], Op->Flags, false);
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RefPair Result {};
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if (Op->Src[1].IsGPR()) {
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// If the source is a GPR then convert directly from the GPR.
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auto Src2 = LoadSource_WithOpSize(GPRClass, Op, Op->Src[1], CTX->GetGPRSize(), Op->Flags);
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Result.Low = _VSToFGPRInsert(OpSize::i128Bit, DstElementSize, SrcSize, Src1.Low, Src2, false);
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} else if (SrcSize != DstElementSize) {
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// If the source is from memory but the Source size and destination size aren't the same,
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// then it is more optimal to load in to a GPR and convert between GPR->FPR.
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// ARM GPR->FPR conversion supports different size source and destinations while FPR->FPR doesn't.
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auto Src2 = LoadSource(GPRClass, Op, Op->Src[1], Op->Flags);
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Result.Low = _VSToFGPRInsert(IR::SizeToOpSize(DstSize), DstElementSize, SrcSize, Src1.Low, Src2, false);
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} else {
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// In the case of cvtsi2s{s,d} where the source and destination are the same size,
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// then it is more optimal to load in to the FPR register directly and convert there.
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auto Src2 = AVX128_LoadSource_WithOpSize(Op, Op->Src[1], Op->Flags, false);
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// Always signed
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Result.Low = _VSToFVectorInsert(IR::SizeToOpSize(DstSize), DstElementSize, DstElementSize, Src1.Low, Src2.Low, false, false);
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}
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Result.High = LoadZeroVector(OpSize::i128Bit);
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LOGMAN_THROW_A_FMT(Is128Bit, "Programming Error: This should never occur!");
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AVX128_StoreResult_WithOpSize(Op, Op->Dest, Result);
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}
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template<size_t SrcElementSize, bool HostRoundingMode>
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void OpDispatchBuilder::AVX128_CVTFPR_To_GPR(OpcodeArgs) {
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// If loading a vector, use the full size, so we don't
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// unnecessarily zero extend the vector. Otherwise, if
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// memory, then we want to load the element size exactly.
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RefPair Src {};
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if (Op->Src[0].IsGPR()) {
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Src = AVX128_LoadSource_WithOpSize(Op, Op->Src[0], Op->Flags, false);
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} else {
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Src.Low = LoadSource_WithOpSize(FPRClass, Op, Op->Src[0], GetSrcSize(Op), Op->Flags);
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}
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// GPR size is determined by REX.W
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// Source Element size is determined by instruction
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size_t GPRSize = GetDstSize(Op);
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Ref Result {};
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if constexpr (HostRoundingMode) {
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Result = _Float_ToGPR_S(GPRSize, SrcElementSize, Src.Low);
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} else {
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Result = _Float_ToGPR_ZS(GPRSize, SrcElementSize, Src.Low);
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}
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StoreResult_WithOpSize(GPRClass, Op, Op->Dest, Result, GPRSize, -1);
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}
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void OpDispatchBuilder::AVX128_VANDN(OpcodeArgs) {
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AVX128_VectorBinaryImpl(Op, GetSrcSize(Op), OpSize::i128Bit,
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[this](size_t _ElementSize, Ref Src1, Ref Src2) { return _VAndn(OpSize::i128Bit, _ElementSize, Src2, Src1); });
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}
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template<size_t ElementSize>
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void OpDispatchBuilder::AVX128_VPACKSS(OpcodeArgs) {
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AVX128_VectorBinaryImpl(Op, GetSrcSize(Op), ElementSize,
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[this](size_t _ElementSize, Ref Src1, Ref Src2) { return _VSQXTNPair(OpSize::i128Bit, _ElementSize, Src1, Src2); });
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}
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template<size_t ElementSize>
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void OpDispatchBuilder::AVX128_VPACKUS(OpcodeArgs) {
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AVX128_VectorBinaryImpl(Op, GetSrcSize(Op), ElementSize,
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[this](size_t _ElementSize, Ref Src1, Ref Src2) { return _VSQXTUNPair(OpSize::i128Bit, _ElementSize, Src1, Src2); });
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}
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Ref OpDispatchBuilder::AVX128_PSIGNImpl(size_t ElementSize, Ref Src1, Ref Src2) {
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Ref Control = _VSQSHL(OpSize::i128Bit, ElementSize, Src2, (ElementSize * 8) - 1);
|
||||
Control = _VSRSHR(OpSize::i128Bit, ElementSize, Control, (ElementSize * 8) - 1);
|
||||
return _VMul(OpSize::i128Bit, ElementSize, Src1, Control);
|
||||
}
|
||||
|
||||
template<size_t ElementSize>
|
||||
void OpDispatchBuilder::AVX128_VPSIGN(OpcodeArgs) {
|
||||
AVX128_VectorBinaryImpl(Op, GetSrcSize(Op), ElementSize,
|
||||
[this](size_t _ElementSize, Ref Src1, Ref Src2) { return AVX128_PSIGNImpl(_ElementSize, Src1, Src2); });
|
||||
}
|
||||
|
||||
} // namespace FEXCore::IR
|
||||
|
||||
@ -1723,17 +1723,9 @@ void OpDispatchBuilder::VEXTRACT128Op(OpcodeArgs) {
|
||||
Ref OpDispatchBuilder::PSIGNImpl(OpcodeArgs, size_t ElementSize, Ref Src1, Ref Src2) {
|
||||
const auto Size = GetSrcSize(Op);
|
||||
|
||||
if (CTX->BackendFeatures.SupportsSaturatingRoundingShifts) {
|
||||
Ref Control = _VSQSHL(Size, ElementSize, Src2, (ElementSize * 8) - 1);
|
||||
Control = _VSRSHR(Size, ElementSize, Control, (ElementSize * 8) - 1);
|
||||
return _VMul(Size, ElementSize, Src1, Control);
|
||||
} else {
|
||||
auto NegVec = _VNeg(Size, ElementSize, Src1);
|
||||
Ref CmpLT = _VCMPLTZ(Size, ElementSize, Src2);
|
||||
Ref CmpEQ = _VCMPEQZ(Size, ElementSize, Src2);
|
||||
auto BSLResult = _VBSL(Size, CmpLT, NegVec, Src1);
|
||||
return _VAndn(Size, Size, BSLResult, CmpEQ);
|
||||
}
|
||||
Ref Control = _VSQSHL(Size, ElementSize, Src2, (ElementSize * 8) - 1);
|
||||
Control = _VSRSHR(Size, ElementSize, Control, (ElementSize * 8) - 1);
|
||||
return _VMul(Size, ElementSize, Src1, Control);
|
||||
}
|
||||
|
||||
template<size_t ElementSize>
|
||||
|
||||
Loading…
Reference in New Issue
Block a user