Fix FPREM flags calculation in F64

This commit is contained in:
CallumDev 2023-01-09 22:21:23 +10:30
parent c2325e1772
commit 806587d6ae
5 changed files with 140 additions and 2 deletions

View File

@ -822,8 +822,8 @@ void OpDispatchBuilder::X87BinaryOpF64(OpcodeArgs) {
// Overwrite the op
result.first->Header.Op = IROp;
if constexpr (IROp == IR::OP_F80FPREM ||
IROp == IR::OP_F80FPREM1) {
if constexpr (IROp == IR::OP_F64FPREM ||
IROp == IR::OP_F64FPREM1) {
//TODO: Set C0 to Q2, C3 to Q1, C1 to Q0
SetRFLAG<FEXCore::X86State::X87FLAG_C2_LOC>(_Constant(0));
}

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@ -0,0 +1,34 @@
%ifdef CONFIG
{
"RegData": {
"RAX": "0"
}
}
%endif
mov rbx, 0xe0000000
o32 fstenv [rbx]
mov dword [rbx+4], 0xFFFFFFFF ; set status word to all one
o32 fldenv [rbx]
lea rdx, [rel data]
fld tword [rdx + 8 * 0]
lea rdx, [rel data2]
fld tword [rdx + 8 * 0]
fprem1
xor rax, rax
fstsw ax
and rax, 0x400 ; C2 should be set to zero
hlt
align 8
data:
dt 3.0
dq 0
data2:
dt 5.1
dq 0

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@ -0,0 +1,34 @@
%ifdef CONFIG
{
"RegData": {
"RAX": "0"
}
}
%endif
mov rbx, 0xe0000000
o32 fstenv [rbx]
mov dword [rbx+4], 0xFFFFFFFF ; set status word to all one
o32 fldenv [rbx]
lea rdx, [rel data]
fld tword [rdx + 8 * 0]
lea rdx, [rel data2]
fld tword [rdx + 8 * 0]
fprem
xor rax, rax
fstsw ax
and rax, 0x400 ; C2 should be set to zero
hlt
align 8
data:
dt 3.0
dq 0
data2:
dt 5.1
dq 0

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@ -0,0 +1,35 @@
%ifdef CONFIG
{
"Env": { "FEX_X87REDUCEDPRECISION" : "1" },
"RegData": {
"RAX": "0"
}
}
%endif
mov rbx, 0xe0000000
o32 fstenv [rbx]
mov dword [rbx+4], 0xFFFFFFFF ; set status word to all one
o32 fldenv [rbx]
lea rdx, [rel data]
fld tword [rdx + 8 * 0]
lea rdx, [rel data2]
fld tword [rdx + 8 * 0]
fprem1
xor rax, rax
fstsw ax
and rax, 0x400 ; C2 should be set to zero
hlt
align 8
data:
dt 3.0
dq 0
data2:
dt 5.1
dq 0

View File

@ -0,0 +1,35 @@
%ifdef CONFIG
{
"Env": { "FEX_X87REDUCEDPRECISION" : "1" },
"RegData": {
"RAX": "0"
}
}
%endif
mov rbx, 0xe0000000
o32 fstenv [rbx]
mov dword [rbx+4], 0xFFFFFFFF ; set status word to all one
o32 fldenv [rbx]
lea rdx, [rel data]
fld tword [rdx + 8 * 0]
lea rdx, [rel data2]
fld tword [rdx + 8 * 0]
fprem
xor rax, rax
fstsw ax
and rax, 0x400 ; C2 should be set to zero
hlt
align 8
data:
dt 3.0
dq 0
data2:
dt 5.1
dq 0