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IR: add AddWithFlags
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
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@ -85,6 +85,21 @@ DEF_OP(Add) {
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}
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}
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DEF_OP(AddWithFlags) {
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auto Op = IROp->C<IR::IROp_AddWithFlags>();
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const uint8_t OpSize = IROp->Size;
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LOGMAN_THROW_AA_FMT(OpSize == 4 || OpSize == 8, "Unsupported {} size: {}", __func__, OpSize);
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const auto EmitSize = OpSize == IR::i64Bit ? ARMEmitter::Size::i64Bit : ARMEmitter::Size::i32Bit;
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uint64_t Const;
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if (IsInlineConstant(Op->Src2, &Const)) {
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adds(EmitSize, GetReg(Node), GetReg(Op->Src1.ID()), Const);
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} else {
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adds(EmitSize, GetReg(Node), GetReg(Op->Src1.ID()), GetReg(Op->Src2.ID()));
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}
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}
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DEF_OP(AddShift) {
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auto Op = IROp->C<IR::IROp_AddShift>();
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const uint8_t OpSize = IROp->Size;
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@ -961,6 +961,14 @@
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"_Shift != ShiftType::ROR"
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]
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},
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"GPR = AddWithFlags OpSize:#Size, GPR:$Src1, GPR:$Src2": {
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"Desc": [ "Integer add. Truncates and sets NZCV per AddNZCV"],
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"DestSize": "Size",
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"HasSideEffects": true,
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"EmitValidation": [
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"Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
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]
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},
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"AddNZCV OpSize:#Size, GPR:$Src1, GPR:$Src2": {
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"Desc": ["Set NZCV for the sum of two GPRs"],
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"HasSideEffects": true,
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@ -965,6 +965,7 @@ bool ConstProp::ConstantInlining(IREmitter *IREmit, const IRListView& CurrentIR)
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case OP_SUB:
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case OP_ADDNZCV:
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case OP_SUBNZCV:
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case OP_ADDWITHFLAGS:
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case OP_SUBWITHFLAGS:
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{
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auto Op = IROp->C<IR::IROp_Add>();
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@ -128,6 +128,13 @@ DeadFlagCalculationEliminination::Classify(IROp_Header *IROp)
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.Replacement = OP_AND,
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};
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case OP_ADDWITHFLAGS:
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return {
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.Write = FLAG_NZCV,
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.CanReplace = true,
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.Replacement = OP_ADD,
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};
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case OP_SUBWITHFLAGS:
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return {
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.Write = FLAG_NZCV,
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