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CodeEmitter: Adds support for BF16 conversion instructions.

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Ryan Houdek committed 2026-10-20 16:04:15 -07:00
1 parent eeb99027c7
commit c77f476bfe
2 files changed
+13
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CodeEmitter/CodeEmitter/ASIMDOps.inl
+10
View File
@@ -768,6 +768,16 @@ public:
ASIMD2RegMisc(0, size, 0b11101, rd, rn);
}
}
///< size is the destination size.
///< source size is the next size up.
void bfcvtn(QRegister rd, QRegister rn) {
ASIMD2RegMisc(0, SubRegSize::i32Bit, 0b10110, rd.D(), rn.D());
}
///< size is the destination size.
///< source size is the next size up.
void bfcvtn2(QRegister rd, QRegister rn) {
ASIMD2RegMisc(0, SubRegSize::i32Bit, 0b10110, rd, rn);
}
template<IsQOrDRegister T>
void rev32(SubRegSize size, T rd, T rn) {
FEXCore/unittests/Emitter/ASIMD_Tests.cpp
+3
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@@ -644,6 +644,9 @@ TEST_CASE_METHOD(TestDisassembler, "Emitter: ASIMD: Advanced SIMD two-register m
TEST_SINGLE(frecpe(SubRegSize::i32Bit, DReg::d30, DReg::d29), "frecpe v30.2s, v29.2s");
// TEST_SINGLE(frecpe(SubRegSize::i64Bit, DReg::d30, DReg::d29), "frecpe v30.1d, v29.1d");
TEST_SINGLE(bfcvtn(QReg::q30, QReg::q29), "bfcvtn v30.4h, v29.4s");
TEST_SINGLE(bfcvtn2(QReg::q30, QReg::q29), "bfcvtn2 v30.8h, v29.4s");
TEST_SINGLE(rev32(SubRegSize::i8Bit, QReg::q30, QReg::q29), "rev32 v30.16b, v29.16b");
TEST_SINGLE(rev32(SubRegSize::i16Bit, QReg::q30, QReg::q29), "rev32 v30.8h, v29.8h");
// TEST_SINGLE(rev32(SubRegSize::i32Bit, QReg::q30, QReg::q29), "rev32 v30.4s, v29.4s");