FEX-Emu/FEX
1
0
Fork 0
mirror of https://github.com/FEX-Emu/FEX.git synced 2024-12-14 17:38:47 +00:00
Code Issues Actions 6 Packages Projects Releases Wiki Activity

OpcodeDispatcher: simplify RDRAND

Browse Source 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
This commit is contained in:
Alyssa Rosenzweig 2024-08-10 15:08:35 -04:00
parent 5631ff4fd5
commit d9c779289c
4 changed files with 13 additions and 26 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
FEXCore/Source/Interface/Core/JIT/Arm64/MiscOps.cpp
View File

@ -254,18 +254,7 @@ DEF_OP(ProcessorID) {
DEF_OP(RDRAND) {
auto Op = IROp->C<IR::IROp_RDRAND>();
// Results are in x0, x1
// Results want to be in a i64v2 vector
auto Dst = GetRegPair(Node);
if (Op->GetReseeded) {
mrs(Dst.first, ARMEmitter::SystemRegister::RNDRRS);
} else {
mrs(Dst.first, ARMEmitter::SystemRegister::RNDR);
}
// If the rng number is valid then NZCV is 0b0000, otherwise NZCV is 0b0100
cset(ARMEmitter::Size::i64Bit, Dst.second, ARMEmitter::Condition::CC_NE);
mrs(GetReg(Node), Op->GetReseeded ? ARMEmitter::SystemRegister::RNDRRS : ARMEmitter::SystemRegister::RNDR);
}
DEF_OP(Yield) {

13
FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
View File

@ -4922,20 +4922,17 @@ void OpDispatchBuilder::CRC32(OpcodeArgs) {
template<bool Reseed>
void OpDispatchBuilder::RDRANDOp(OpcodeArgs) {
auto Res = _RDRAND(Reseed);
auto [Result_Lower, Result_Upper] = ExtractPair(OpSize::i64Bit, Res);
StoreResult(GPRClass, Op, _RDRAND(Reseed), -1);
StoreResult(GPRClass, Op, Result_Lower, -1);
// If the rng number is valid then NZCV is 0b0000, otherwise NZCV is 0b0100
auto Invalid = GetRFLAG(X86State::RFLAG_ZF_RAW_LOC);
// OF, SF, ZF, AF, PF all zero
// OF, SF, ZF, AF, PF all zero. CF indicates if valid.
ZeroNZCV();
ZeroPF_AF();
// CF is set to the incoming source
SetCFDirect(Result_Upper);
SetCFInverted(Invalid);
}
void OpDispatchBuilder::BreakOp(OpcodeArgs, FEXCore::IR::BreakDefinition BreakDefinition) {
const uint8_t GPRSize = CTX->GetGPRSize();

11
FEXCore/Source/Interface/IR/IR.json
View File

@ -252,17 +252,16 @@
"WalkFindRegClass($Value) != GPRPairClass"
]
},
"GPRPair = RDRAND i1:$GetReseeded": {
"GPR = RDRAND i1:$GetReseeded": {
"Desc": ["Uses the hardware random number generator to generate a 64bit number",
"The boolean argument asks if we should be reading the reseeded number or not",
"Reseeded RNG calculation is more expensive and will be heavier to use",
"The first GPR pair element is the 64-bit number",
"The second GPR pair element is a bool if the number is valid",
"Returns the 64-bit number",
"Sets the Z flag if the number is valid.",
"RNG hardware is allowed to fail early and return. Software must always check this"
],
"ImplicitFlagClobber": true,
"DestSize": "16",
"NumElements": "2"
"HasSideEffects": true,
"DestSize": "8"
},
"Yield": {
"HasSideEffects": true,

2
FEXCore/Source/Interface/IR/Passes/RedundantFlagCalculationElimination.cpp
View File

@ -151,6 +151,8 @@ FlagInfo DeadFlagCalculationEliminination::Classify(IROp_Header* IROp) {
.CanEliminate = true,
};
case OP_RDRAND: return {.Write = FLAG_NZCV};
case OP_ADDNZCV:
case OP_SUBNZCV:
case OP_TESTNZ: