Merge pull request #6105 from Sonicadvance1/309

DiskCache: Moves SVE/AVX from HostFeatureHash to ProcessHash

FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.cpp

@@ -665,11 +665,11 @@ void Arm64Emitter::FillSpecialRegs(ARMEmitter::Register TmpReg, ARMEmitter::Regi
     // We don't bother spilling these in SpillStaticRegs,
     // since all that matters is we restore them on a fill.
     // It's not a concern if they get trounced by something else.
-    if (EmitterCTX->HostFeatures.SupportsSVE256) {
+    if (EmitterCTX->HostFeatures.SupportsSVE256()) {
       ptrue(ARMEmitter::SubRegSize::i8Bit, PRED_TMP_32B, ARMEmitter::PredicatePattern::SVE_VL32);
     }
 
-    if (EmitterCTX->HostFeatures.SupportsSVE128) {
+    if (EmitterCTX->HostFeatures.SupportsSVE128()) {
       ptrue(ARMEmitter::SubRegSize::i8Bit, PRED_TMP_16B, ARMEmitter::PredicatePattern::SVE_VL16);
     }
 
@@ -739,7 +739,7 @@ void Arm64Emitter::SpillStaticRegs(ARMEmitter::Register TmpReg, SpillStaticRegOp
   }
 
   if (Options.FPRs) {
-    if (EmitterCTX->HostFeatures.SupportsAVX && EmitterCTX->HostFeatures.SupportsSVE256) {
+    if (EmitterCTX->HostFeatures.SupportsAVX() && EmitterCTX->HostFeatures.SupportsSVE256()) {
       for (size_t i = 0; i < StaticFPRegisters.size(); i++) {
         const auto Reg = StaticFPRegisters[i];
 
@@ -826,7 +826,7 @@ void Arm64Emitter::FillStaticRegs(FillStaticRegOptions Options) {
   FillSpecialRegs(TmpReg, TmpReg2, {.SetFIZ = true, .SetPredRegs = Options.FPRs});
 
   if (Options.FPRs) {
-    if (EmitterCTX->HostFeatures.SupportsAVX && EmitterCTX->HostFeatures.SupportsSVE256) {
+    if (EmitterCTX->HostFeatures.SupportsAVX() && EmitterCTX->HostFeatures.SupportsSVE256()) {
       for (size_t i = 0; i < StaticFPRegisters.size(); i++) {
         const auto Reg = StaticFPRegisters[i];
         if (((1U << Reg.Idx()) & Options.FPRFillMask) != 0) {
@@ -990,7 +990,7 @@ void Arm64Emitter::PopGeneralRegisters(std::span<const ARMEmitter::Register> Reg
 }
 
 size_t Arm64Emitter::PushDynamicRegs(ARMEmitter::Register TmpReg) {
-  const auto CanUseSVE256 = EmitterCTX->HostFeatures.SupportsSVE256;
+  const auto CanUseSVE256 = EmitterCTX->HostFeatures.SupportsSVE256();
   const auto GPRSize = GeneralRegistersNotPreserved.size() * Core::CPUState::GPR_REG_SIZE;
   const auto FPRRegSize = CanUseSVE256 ? 32 : 16;
   const auto FPRSize = GeneralFPRegisters.size() * FPRRegSize;
@@ -1013,7 +1013,7 @@ size_t Arm64Emitter::PushDynamicRegs(ARMEmitter::Register TmpReg) {
 }
 
 void Arm64Emitter::PopDynamicRegs() {
-  const auto CanUseSVE256 = EmitterCTX->HostFeatures.SupportsSVE256;
+  const auto CanUseSVE256 = EmitterCTX->HostFeatures.SupportsSVE256();
 
   // Pop vectors first
   PopVectorRegisters(CanUseSVE256, GeneralFPRegisters);
@@ -1023,7 +1023,7 @@ void Arm64Emitter::PopDynamicRegs() {
 }
 
 size_t Arm64Emitter::SpillForPreserveAllABICall(ARMEmitter::Register TmpReg, bool FPRs) {
-  const auto CanUseSVE256 = EmitterCTX->HostFeatures.SupportsSVE256;
+  const auto CanUseSVE256 = EmitterCTX->HostFeatures.SupportsSVE256();
   const auto FPRRegSize = CanUseSVE256 ? 32 : 16;
 
   std::span<const ARMEmitter::Register> DynamicGPRs {};
@@ -1078,7 +1078,7 @@ size_t Arm64Emitter::SpillForPreserveAllABICall(ARMEmitter::Register TmpReg, boo
 }
 
 void Arm64Emitter::FillForPreserveAllABICall(bool FPRs) {
-  const auto CanUseSVE256 = EmitterCTX->HostFeatures.SupportsSVE256;
+  const auto CanUseSVE256 = EmitterCTX->HostFeatures.SupportsSVE256();
 
   std::span<const ARMEmitter::Register> DynamicGPRs {};
   std::span<const ARMEmitter::VRegister> DynamicFPRs {};

FEXCore/Source/Interface/Core/CPUID.cpp

@@ -443,7 +443,7 @@ void CPUIDEmu::SetupHostHybridFlag() {}
 
 
 void CPUIDEmu::SetupFeatures() {
-  if (CTX->HostFeatures.SupportsAVX) {
+  if (CTX->HostFeatures.SupportsAVX()) {
     XCR0 |= XCR0_AVX;
   }
 

FEXCore/Source/Interface/Core/Core.cpp

@@ -264,8 +264,8 @@ uint32_t ContextImpl::ReconstructCompactedEFLAGS(FEXCore::Core::InternalThreadSt
 void ContextImpl::ReconstructXMMRegisters(const FEXCore::Core::InternalThreadState* Thread, __uint128_t* XMM_Low, __uint128_t* YMM_High) {
   const size_t MaximumRegisters = Config.Is64BitMode ? FEXCore::Core::CPUState::NUM_XMMS : 8;
 
-  if (YMM_High != nullptr && HostFeatures.SupportsAVX) {
-    const bool SupportsConvergedRegisters = HostFeatures.SupportsSVE256;
+  if (YMM_High != nullptr && HostFeatures.SupportsAVX()) {
+    const bool SupportsConvergedRegisters = HostFeatures.SupportsSVE256();
 
     if (SupportsConvergedRegisters) {
       ///< Output wants to de-interleave
@@ -288,8 +288,8 @@ void ContextImpl::ReconstructXMMRegisters(const FEXCore::Core::InternalThreadSta
 
 void ContextImpl::SetXMMRegistersFromState(FEXCore::Core::InternalThreadState* Thread, const __uint128_t* XMM_Low, const __uint128_t* YMM_High) {
   const size_t MaximumRegisters = Config.Is64BitMode ? FEXCore::Core::CPUState::NUM_XMMS : 8;
-  if (YMM_High != nullptr && HostFeatures.SupportsAVX) {
-    const bool SupportsConvergedRegisters = HostFeatures.SupportsSVE256;
+  if (YMM_High != nullptr && HostFeatures.SupportsAVX()) {
+    const bool SupportsConvergedRegisters = HostFeatures.SupportsSVE256();
 
     if (SupportsConvergedRegisters) {
       ///< Output wants to de-interleave

FEXCore/Source/Interface/Core/DiskCache.cpp

@@ -409,6 +409,12 @@ namespace DiskCache {
       uint64_t HostFeaturesHash;
     } MachineBucketData = {FormatVersion, HostFeatureHash.HostFeaturesHash};
 
+    uint8_t ProcessFeaturesHash {};
+    memcpy(&ProcessFeaturesHash, &HostFeatureHash.ProcessFeaturesHash, sizeof(ProcessFeaturesHash));
+    LogMan::Msg::IFmt("Disk Cache features:");
+    LogMan::Msg::IFmt("HostFeatures Hash: 0x{:016x}", HostFeatureHash.HostFeaturesHash);
+    LogMan::Msg::IFmt("ProcessFeaturesHash: 0x{:02x}", ProcessFeaturesHash);
+
     fextl::vector<uint8_t> BucketBytes(sizeof(MachineBucketData) + sizeof(HostFeatureHash.ProcessFeaturesHash) + SerializedConfig.size());
     memcpy(BucketBytes.data(), &MachineBucketData, sizeof(MachineBucketData));
 

FEXCore/Source/Interface/Core/DiskCache.h

@@ -249,7 +249,7 @@ namespace DiskCache {
   // The current version of the diskcache.
   // This must be changed any time codegen changes occur!
   // Be aware of the impact of changing this frequently!
-  static constexpr uint16_t FormatVersion = 42;
+  static constexpr uint16_t FormatVersion = 43;
 
   static constexpr uint32_t LOOKUP_KEY_MAX_BUCKET_DEPTH = 500;
 

FEXCore/Source/Interface/Core/Frontend.cpp

@@ -79,10 +79,10 @@ Decoder::Decoder(FEXCore::Core::InternalThreadState* Thread)
     X87Table = &FEXCore::X86Tables::X87F80Ops;
   }
 
-  if (CTX->HostFeatures.SupportsAVX && CTX->HostFeatures.SupportsSVE256) {
+  if (CTX->HostFeatures.SupportsAVX() && CTX->HostFeatures.SupportsSVE256()) {
     VEXTable = &FEXCore::X86Tables::VEXTableOps;
     VEXTableGroup = &FEXCore::X86Tables::VEXTableGroupOps;
-  } else if (CTX->HostFeatures.SupportsAVX) {
+  } else if (CTX->HostFeatures.SupportsAVX()) {
     VEXTable = &FEXCore::X86Tables::VEXTableOps_AVX128;
     VEXTableGroup = &FEXCore::X86Tables::VEXTableGroupOps_AVX128;
   }

FEXCore/Source/Interface/Core/JIT/JIT.cpp

@@ -625,9 +625,9 @@ void Arm64JITCore::Op_NoOp(const IR::IROp_Header* IROp, IR::Ref Node) {}
 Arm64JITCore::Arm64JITCore(FEXCore::Context::ContextImpl* ctx, FEXCore::Core::InternalThreadState* Thread)
   : CPUBackend(*ctx, Thread)
   , Arm64Emitter(ctx)
-  , HostSupportsSVE128 {ctx->HostFeatures.SupportsSVE128 != 0}
-  , HostSupportsSVE256 {ctx->HostFeatures.SupportsSVE256 != 0}
-  , HostSupportsAVX256 {ctx->HostFeatures.SupportsAVX && ctx->HostFeatures.SupportsSVE256}
+  , HostSupportsSVE128 {ctx->HostFeatures.SupportsSVE128()}
+  , HostSupportsSVE256 {ctx->HostFeatures.SupportsSVE256()}
+  , HostSupportsAVX256 {ctx->HostFeatures.SupportsAVX() && ctx->HostFeatures.SupportsSVE256()}
   , HostSupportsRPRES {ctx->HostFeatures.SupportsRPRES != 0}
   , HostSupportsAFP {ctx->HostFeatures.SupportsAFP != 0}
   , CTX {ctx}

FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp

@@ -4752,11 +4752,11 @@ OpDispatchBuilder::OpDispatchBuilder(FEXCore::Context::ContextImpl* ctx, FEXCore
   : IREmitter {ctx->OpDispatcherAllocator, ctx->HostFeatures.SupportsTSOImm9 != 0}
   , CTX {ctx}
   , Thread {Thread} {
-  if (CTX->HostFeatures.SupportsAVX && CTX->HostFeatures.SupportsSVE256) {
+  if (CTX->HostFeatures.SupportsAVX() && CTX->HostFeatures.SupportsSVE256()) {
     SaveAVXStateFunc = &OpDispatchBuilder::SaveAVXState;
     RestoreAVXStateFunc = &OpDispatchBuilder::RestoreAVXState;
     DefaultAVXStateFunc = &OpDispatchBuilder::DefaultAVXState;
-  } else if (CTX->HostFeatures.SupportsAVX) {
+  } else if (CTX->HostFeatures.SupportsAVX()) {
     SaveAVXStateFunc = &OpDispatchBuilder::AVX128_SaveAVXState;
     RestoreAVXStateFunc = &OpDispatchBuilder::AVX128_RestoreAVXState;
     DefaultAVXStateFunc = &OpDispatchBuilder::AVX128_DefaultAVXState;

FEXCore/Source/Interface/Core/OpcodeDispatcher.h

@@ -1330,7 +1330,7 @@ protected:
       /* On ASIMD platforms, the emulation happens to preserve NZCV, unlike the
        * more optimal SVE implementation that clobbers.
        */
-      if (!CTX->HostFeatures.SupportsSVE128 && !CTX->HostFeatures.SupportsSVE256) {
+      if (!CTX->HostFeatures.SupportsSVE()) {
         return;
       }
 
@@ -1677,7 +1677,7 @@ private:
   }
 
   constexpr OpSize GetGuestVectorLength() const {
-    return (CTX->HostFeatures.SupportsSVE256 && CTX->HostFeatures.SupportsAVX) ? OpSize::i256Bit : OpSize::i128Bit;
+    return (CTX->HostFeatures.SupportsSVE256() && CTX->HostFeatures.SupportsAVX()) ? OpSize::i256Bit : OpSize::i128Bit;
   }
 
   [[nodiscard]]

FEXCore/Source/Interface/Core/OpcodeDispatcher/AVX_128.cpp

@@ -2067,7 +2067,7 @@ OpDispatchBuilder::RefPair OpDispatchBuilder::AVX128_VPGatherImpl(OpcodeArgs, Op
     BaseAddr = Invalid();
   }
 
-  if (CTX->HostFeatures.SupportsSVE128) {
+  if (CTX->HostFeatures.SupportsSVE128()) {
     if (ElementLoadSize == OpSize::i64Bit && AddrElementSize == OpSize::i32Bit) {
       // In the case that FEX is loading double the amount of data than the number of address bits then we can optimize this case.
       // For 256-bits of data we need to sign extend all four 32-bit address elements to be 64-bit.
@@ -2170,7 +2170,7 @@ OpDispatchBuilder::RefPair OpDispatchBuilder::AVX128_VPGatherQPSImpl(OpcodeArgs,
 
   bool NeedsSVEScale = (VSIB.Scale == 2 || VSIB.Scale == 8) || (BaseAddr == Invalid() && VSIB.Scale != 1);
 
-  if (CTX->HostFeatures.SupportsSVE128 && NeedsSVEScale) {
+  if (CTX->HostFeatures.SupportsSVE128() && NeedsSVEScale) {
     // SVE gather instructions don't support scaling their vector elements by anything other than 1 or the address element size.
     // Pre-scale 64-bit addresses in the case that scale doesn't match in-order to hit SVE code paths more frequently.
     // Only hit this path if the host supports SVE. Otherwise it's a degradation for the ASIMD codepath.
@@ -2236,7 +2236,7 @@ void OpDispatchBuilder::AVX128_VPGATHER(OpcodeArgs, OpSize AddrElementSize) {
   bool NeedsSVEScale = (VSIB.Scale == 2 || VSIB.Scale == 8) || (VSIB.BaseAddr == Invalid() && VSIB.Scale != 1);
 
   const bool NeedsExplicitSVEPath =
-    CTX->HostFeatures.SupportsSVE128 && AddrElementSize == OpSize::i32Bit && ElementLoadSize == OpSize::i32Bit && NeedsSVEScale;
+    CTX->HostFeatures.SupportsSVE128() && AddrElementSize == OpSize::i32Bit && ElementLoadSize == OpSize::i32Bit && NeedsSVEScale;
 
   RefPair Result {};
   if (NeedsExplicitSVEPath) {

FEXCore/Source/Interface/Core/OpcodeDispatcher/Crypto.cpp

@@ -27,7 +27,7 @@ void OpDispatchBuilder::SHA1NEXTEOp(OpcodeArgs) {
   Ref Src = LoadSourceFPR(Op, Op->Src[0], Op->Flags);
 
   Ref Result {};
-  if (CTX->HostFeatures.SupportsSVE128) {
+  if (CTX->HostFeatures.SupportsSVE128()) {
     auto ZeroVec = LoadZeroVector(OpSize::i128Bit);
     auto Tmp = _VInsElement(OpSize::i128Bit, OpSize::i32Bit, 3, 3, ZeroVec, Dest);
     auto Xar = _VXar(OpSize::i128Bit, OpSize::i32Bit, ZeroVec, Tmp, 2);

FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp

@@ -3025,7 +3025,7 @@ void OpDispatchBuilder::XSaveOpImpl(OpcodeArgs) {
     StoreIfFlagSet(1, [this, Op] { SaveSSEState(XSaveBase(Op)); });
   }
   // AVX
-  if (CTX->HostFeatures.SupportsAVX) {
+  if (CTX->HostFeatures.SupportsAVX()) {
     StoreIfFlagSet(2, [this, Op] { std::invoke(SaveAVXStateFunc, this, XSaveBase(Op)); });
   }
 
@@ -3232,7 +3232,7 @@ void OpDispatchBuilder::XRstorOpImpl(OpcodeArgs) {
     RestoreIfFlagSetOrDefault(1, [this, Op] { RestoreSSEState(XSaveBase(Op)); }, [this] { DefaultSSEState(); });
   }
   // AVX
-  if (CTX->HostFeatures.SupportsAVX) {
+  if (CTX->HostFeatures.SupportsAVX()) {
     RestoreIfFlagSetOrDefault(
       2, [this, Op] { std::invoke(RestoreAVXStateFunc, this, XSaveBase(Op)); }, [this] { std::invoke(DefaultAVXStateFunc, this); });
   }

FEXCore/include/FEXCore/Core/HostFeatures.h

@@ -24,7 +24,22 @@ struct HostFeatures {
   // Whether or not the host supports any kind of SVE implementation.
   [[nodiscard]]
   bool SupportsSVE() const {
-    return SupportsSVE128 || SupportsSVE256;
+    return ProcessFeatures.SupportsSVE128 || ProcessFeatures.SupportsSVE256;
+  }
+
+  [[nodiscard]]
+  bool SupportsSVE128() const {
+    return ProcessFeatures.SupportsSVE128;
+  }
+
+  [[nodiscard]]
+  bool SupportsSVE256() const {
+    return ProcessFeatures.SupportsSVE256;
+  }
+
+  [[nodiscard]]
+  bool SupportsAVX() const {
+    return ProcessFeatures.SupportsAVX;
   }
 
   [[nodiscard]]
@@ -42,7 +57,13 @@ struct HostFeatures {
     // This only determines the starting mode a process started in.
     // The process can technically long jump to-from the other modes.
     uint8_t Is64BitMode : 1 {};
-    uint8_t pad         : 4 {};
+
+    // These are technically HostFeatures, but they differ between Linux, wow64, arm64.
+    uint8_t SupportsAVX    : 1 {};
+    uint8_t SupportsSVE128 : 1 {};
+    uint8_t SupportsSVE256 : 1 {};
+
+    uint8_t pad : 1 {};
   };
   static_assert(sizeof(ProcessFeaturesHash) == 1);
 
@@ -76,35 +97,32 @@ struct HostFeatures {
   uint32_t SupportsRCPC                : 1 {}; // [9]
   uint32_t SupportsTSOImm9             : 1 {}; // [10]
   uint32_t SupportsRAND                : 1 {}; // [11]
-  uint32_t SupportsAVX                 : 1 {}; // [12] // Not enabled on wine?
-  uint32_t SupportsSVE128              : 1 {}; // [13]
-  uint32_t SupportsSVE256              : 1 {}; // [14]
-  uint32_t SupportsSHA                 : 1 {}; // [15]
-  uint32_t SupportsPMULL_128Bit        : 1 {}; // [16]
-  uint32_t SupportsCSSC                : 1 {}; // [17]
-  uint32_t SupportsFCMA                : 1 {}; // [18]
-  uint32_t SupportsFlagM               : 1 {}; // [19]
-  uint32_t SupportsFlagM2              : 1 {}; // [20]
-  uint32_t SupportsRPRES               : 1 {}; // [21]
-  uint32_t SupportsPreserveAllABI      : 1 {}; // [22] // Not enabled on wine
-  uint32_t SupportsAES256              : 1 {}; // [23]
-  uint32_t SupportsSVEBitPerm          : 1 {}; // [24]
-  uint32_t SupportsCPUIndexInTPIDRRO   : 1 {}; // [25]
-  uint32_t SupportsFRINTTS             : 1 {}; // [26]
-  uint32_t SupportsECV                 : 1 {}; // [27]
-  uint32_t SupportsWFXT                : 1 {}; // [28]
-  uint32_t Supports3DNow               : 1 {}; // [29]
-  uint32_t SupportsSSE4a               : 1 {}; // [30]
-  uint32_t SupportsMOPS                : 1 {}; // [31]
-  uint32_t SupportsI8MM                : 1 {}; // [32]
-  uint32_t SupportsDotProd             : 1 {}; // [33]
-  uint32_t PreferZVAForVZero           : 1 {}; // [34]
-  uint32_t SupportsAFP                 : 1 {}; // [35]
-  uint32_t SupportsFloatExceptions     : 1 {}; // [36]
-  uint32_t SupportsBF16                : 1 {}; // [37]
+  uint32_t SupportsSHA                 : 1 {}; // [12]
+  uint32_t SupportsPMULL_128Bit        : 1 {}; // [13]
+  uint32_t SupportsCSSC                : 1 {}; // [14]
+  uint32_t SupportsFCMA                : 1 {}; // [15]
+  uint32_t SupportsFlagM               : 1 {}; // [16]
+  uint32_t SupportsFlagM2              : 1 {}; // [17]
+  uint32_t SupportsRPRES               : 1 {}; // [18]
+  uint32_t SupportsPreserveAllABI      : 1 {}; // [19]
+  uint32_t SupportsAES256              : 1 {}; // [20]
+  uint32_t SupportsSVEBitPerm          : 1 {}; // [21]
+  uint32_t SupportsCPUIndexInTPIDRRO   : 1 {}; // [22]
+  uint32_t SupportsFRINTTS             : 1 {}; // [23]
+  uint32_t SupportsECV                 : 1 {}; // [24]
+  uint32_t SupportsWFXT                : 1 {}; // [25]
+  uint32_t Supports3DNow               : 1 {}; // [26]
+  uint32_t SupportsSSE4a               : 1 {}; // [27]
+  uint32_t SupportsMOPS                : 1 {}; // [28]
+  uint32_t SupportsI8MM                : 1 {}; // [29]
+  uint32_t SupportsDotProd             : 1 {}; // [30]
+  uint32_t PreferZVAForVZero           : 1 {}; // [31]
+  uint32_t SupportsAFP                 : 1 {}; // [32]
+  uint32_t SupportsFloatExceptions     : 1 {}; // [33]
+  uint32_t SupportsBF16                : 1 {}; // [34]
   // Flag if this is InstCountCI
   uint32_t IsInstCountCI : 1 {};  // [38]
-  uint32_t pad           : 25 {}; // [63:39]
+  uint32_t pad           : 28 {}; // [63:35]
 
   // This affects codegen, but it isn't machine state
   ProcessFeaturesHash ProcessFeatures {};

Source/Common/HostFeatures.cpp

@@ -354,8 +354,8 @@ static void OverrideFeatures(FEXCore::HostFeatures* Features, uint64_t ForceSVEW
   const bool Enable##name = (HostFeatures() & FEXCore::Config::HostFeatures::ENABLE##enum_name) != 0;   \
   LogMan::Throw::AFmt(!(Disable##name && Enable##name), "Disabling and Enabling CPU feature (" #name ") is mutually exclusive");
 
-  ENABLE_DISABLE_OPTION(SupportsAVX, AVX, AVX);
-  ENABLE_DISABLE_OPTION(SupportsSVE128, SVE, SVE);
+  ENABLE_DISABLE_OPTION(ProcessFeatures.SupportsAVX, AVX, AVX);
+  ENABLE_DISABLE_OPTION(ProcessFeatures.SupportsSVE128, SVE, SVE);
   ENABLE_DISABLE_OPTION(SupportsAFP, AFP, AFP);
   ENABLE_DISABLE_OPTION(SupportsRCPC, LRCPC, LRCPC);
   ENABLE_DISABLE_OPTION(SupportsTSOImm9, LRCPC2, LRCPC2);
@@ -399,7 +399,7 @@ static void OverrideFeatures(FEXCore::HostFeatures* Features, uint64_t ForceSVEW
   }
 
   ///< Only force enable SVE256 if SVE is already enabled and ForceSVEWidth is set to >= 256.
-  Features->SupportsSVE256 = ForceSVEWidth && ForceSVEWidth >= 256;
+  Features->ProcessFeatures.SupportsSVE256 = ForceSVEWidth && ForceSVEWidth >= 256;
 }
 
 static void HandleErrata(FEXCore::HostFeatures* HostFeatures, uint64_t MIDR) {
@@ -515,15 +515,15 @@ void FetchHostFeatures(FEX::CPUFeatures& Features, FEXCore::HostFeatures& HostFe
 
 #ifdef VIXL_SIMULATOR
   // Hardcode enable SVE with 256-bit wide registers.
-  HostFeatures.SupportsSVE128 = ForceSVEWidth() ? ForceSVEWidth() >= 128 : true;
-  HostFeatures.SupportsSVE256 = ForceSVEWidth() ? ForceSVEWidth() >= 256 : true;
+  HostFeatures.ProcessFeatures.SupportsSVE128 = ForceSVEWidth() ? ForceSVEWidth() >= 128 : true;
+  HostFeatures.ProcessFeatures.SupportsSVE256 = ForceSVEWidth() ? ForceSVEWidth() >= 256 : true;
   HostFeatures.SupportsMOPS = true;
 
   // Simulator has a hardcoded ZVA size of 64-bytes.
   HostFeatures.SupportsCLZERO = true;
   HostFeatures.SupportsAES = true;
   HostFeatures.SupportsCRC = true;
-  HostFeatures.SupportsAVX = true;
+  HostFeatures.ProcessFeatures.SupportsAVX = true;
   HostFeatures.SupportsSHA = true;
   HostFeatures.SupportsPMULL_128Bit = true;
   HostFeatures.SupportsAES256 = true;
@@ -532,8 +532,8 @@ void FetchHostFeatures(FEX::CPUFeatures& Features, FEXCore::HostFeatures& HostFe
   HostFeatures.SupportsRPRES = false;
   HostFeatures.SupportsAFP = false;
 #else
-  HostFeatures.SupportsSVE128 = Features.Supports(CPUFeatures::Feature::SVE2);
-  HostFeatures.SupportsSVE256 = Features.Supports(CPUFeatures::Feature::SVE2) && Features.GetSVEVectorLengthInBits() >= 256;
+  HostFeatures.ProcessFeatures.SupportsSVE128 = Features.Supports(CPUFeatures::Feature::SVE2);
+  HostFeatures.ProcessFeatures.SupportsSVE256 = Features.Supports(CPUFeatures::Feature::SVE2) && Features.GetSVEVectorLengthInBits() >= 256;
   HostFeatures.SupportsMOPS = Features.Supports(CPUFeatures::Feature::MOPS);
 
   // Check if we can support cacheline clears
@@ -546,8 +546,8 @@ void FetchHostFeatures(FEX::CPUFeatures& Features, FEXCore::HostFeatures& HostFe
 #endif
 
   HostFeatures.Supports3DNow = true;
-  HostFeatures.SupportsAVX = true;
-  HostFeatures.SupportsAES256 = HostFeatures.SupportsAVX && HostFeatures.SupportsAES;
+  HostFeatures.ProcessFeatures.SupportsAVX = true;
+  HostFeatures.SupportsAES256 = HostFeatures.SupportsAVX() && HostFeatures.SupportsAES;
   HostFeatures.SupportsPreserveAllABI = FEX_HAS_PRESERVE_ALL_ATTR;
   HostFeatures.PreferZVAForVZero = false;
 
@@ -589,7 +589,7 @@ void FetchHostFeatures(FEX::CPUFeatures& Features, FEXCore::HostFeatures& HostFe
   HostFeatures.SupportsRAND = Feature.Feat_rand;
   HostFeatures.SupportsRCPC = true;
   HostFeatures.SupportsTSOImm9 = true;
-  HostFeatures.SupportsAVX = Feature.Feat_avx;
+  HostFeatures.ProcessFeatures.SupportsAVX = Feature.Feat_avx;
   HostFeatures.SupportsSHA = Feature.Feat_sha;
   HostFeatures.SupportsPMULL_128Bit = Feature.Feat_pclmulqdq;
   HostFeatures.SupportsAES256 = Feature.Feat_aes;

Source/Tools/FEXInterpreter/FEXInterpreter.cpp

@@ -552,8 +552,8 @@ int main(int argc, char** argv, char** const envp) {
   {
     auto HostFeatures = FEX::FetchHostFeatures(Loader.Is64BitMode());
     CTX = FEXCore::Context::Context::CreateNewContext(HostFeatures);
-    SupportsAVX = HostFeatures.SupportsAVX;
-    SupportsSVE256 = HostFeatures.SupportsSVE256;
+    SupportsAVX = HostFeatures.SupportsAVX();
+    SupportsSVE256 = HostFeatures.SupportsSVE256();
   }
 
   FEX::Kernel::Init(Loader.Is64BitMode(), CTX.get());

Source/Tools/TestHarnessRunner/TestHarnessRunner.cpp

@@ -247,7 +247,7 @@ int main(int argc, char** argv, char** const envp) {
   auto CTX = FEXCore::Context::Context::CreateNewContext(HostFeatures);
 
 #ifndef _WIN32
-  auto SignalDelegation = FEX::HLE::CreateSignalDelegator(CTX.get(), {}, HostFeatures.SupportsAVX, HostFeatures.SupportsSVE256);
+  auto SignalDelegation = FEX::HLE::CreateSignalDelegator(CTX.get(), {}, HostFeatures.SupportsAVX(), HostFeatures.SupportsSVE256());
 #else
   // Enable exit on HLT while Wine's longjump is broken.
   //
@@ -257,7 +257,7 @@ int main(int argc, char** argv, char** const envp) {
 #endif
 
   // Skip any tests that the host doesn't support features for
-  SupportsAVX = HostFeatures.SupportsAVX;
+  SupportsAVX = HostFeatures.SupportsAVX();
 
   bool TestUnsupported = (!SupportsAVX && Loader.RequiresAVX()) || (!HostFeatures.SupportsRAND && Loader.RequiresRAND()) ||
                          (!HostFeatures.SupportsSHA && Loader.RequiresSHA()) || (!HostFeatures.SupportsCLZERO && Loader.RequiresCLZERO()) ||

Source/Windows/Common/CPUFeatures.cpp

@@ -79,15 +79,15 @@ FEXCore::HostFeatures CPUFeatures::FetchHostFeatures(bool IsWine, FEXCore::HostF
   FEX::FetchHostFeatures(Features, HostFeatures, IsWine, CTR, MIDR);
 
   // Force-disable SVE until wine/windows gain support for SVE context save/restore
-  HostFeatures.SupportsSVE128 = false;
-  HostFeatures.SupportsSVE256 = false;
+  HostFeatures.ProcessFeatures.SupportsSVE128 = false;
+  HostFeatures.ProcessFeatures.SupportsSVE256 = false;
 
   HostFeatures.SupportsCPUIndexInTPIDRRO = !IsWine || FEX::Windows::UnixLib::SupportsTPIDRRO_CPU();
 
   HostFeatures.ProcessPID = ProcessPID;
 
   // AVX is unsupported for WOW64
-  HostFeatures.SupportsAVX = HostType == FEXCore::HostFeatures::HostTypeEnum::Arm64ec;
+  HostFeatures.ProcessFeatures.SupportsAVX = HostType == FEXCore::HostFeatures::HostTypeEnum::Arm64ec;
 
   HostFeatures.ProcessFeatures.HostType = HostType;
   HostFeatures.ProcessFeatures.Is64BitMode = HostType == FEXCore::HostFeatures::HostTypeEnum::Arm64ec;

unittests/InstructionCountCI/AFP/H0F3A.json

@@ -8,7 +8,7 @@
       "SVE128",
       "SVE256"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "roundss xmm0, xmm1, 00000000b": {

unittests/InstructionCountCI/AFP/SVE256/Secondary.json

@@ -7,7 +7,7 @@
       "AFP"
     ],
     "DisabledHostFeatures": [],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "cvtpi2ps xmm0, [rax]": {

unittests/InstructionCountCI/AFP/SVE256/Secondary_REP.json

@@ -9,7 +9,7 @@
     "DisabledHostFeatures": [
       "RPRES"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "cvtsi2ss xmm0, eax": {

unittests/InstructionCountCI/AFP/SVE256/Secondary_REPNE.json

@@ -7,7 +7,7 @@
       "AFP"
     ],
     "DisabledHostFeatures": [],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "cvtsi2sd xmm0, eax": {

unittests/InstructionCountCI/AFP/Secondary.json

@@ -8,7 +8,7 @@
       "SVE128",
       "SVE256"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "cvtpi2ps xmm0, [rax]": {

unittests/InstructionCountCI/AFP/Secondary_REP.json

@@ -9,7 +9,7 @@
       "SVE256",
       "RPRES"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "cvtsi2ss xmm0, eax": {

unittests/InstructionCountCI/AFP/Secondary_REPNE.json

@@ -8,7 +8,7 @@
       "SVE128",
       "SVE256"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "cvtsi2sd xmm0, eax": {

unittests/InstructionCountCI/AFP/VEX_map1.json

@@ -9,7 +9,7 @@
     "DisabledHostFeatures": [
       "RPRES"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "vsqrtss xmm0, xmm1, xmm2": {

unittests/InstructionCountCI/AFP/VEX_map3.json

@@ -7,7 +7,7 @@
       "AFP"
     ],
     "DisabledHostFeatures": [],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "vroundss xmm0, xmm1, 00000000b": {

unittests/InstructionCountCI/AVX128/FMA4.json

@@ -7,7 +7,7 @@
       "SVE256",
       "SVE128"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "vfmaddsubps xmm0, xmm1, xmm2, xmm3": {

unittests/InstructionCountCI/AVX128/VEX_map1.json

@@ -13,7 +13,7 @@
       "SVE256",
       "SVE128"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "vmovups xmm0, xmm0": {

unittests/InstructionCountCI/AVX128/VEX_map1_FCMA.json

@@ -9,7 +9,7 @@
       "SVE256",
       "SVE128"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "vaddsubpd xmm0, xmm1, xmm2": {

unittests/InstructionCountCI/AVX128/VEX_map1_SVE128.json

@@ -10,7 +10,7 @@
       "FLAGM2",
       "SVE256"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "vmovntps [rax], xmm0": {

unittests/InstructionCountCI/AVX128/VEX_map1_flagm.json

@@ -10,7 +10,7 @@
       "SVE128",
       "SVE256"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "vucomiss xmm0, xmm1": {

unittests/InstructionCountCI/AVX128/VEX_map2.json

@@ -13,7 +13,7 @@
       "I8MM",
       "DOTPROD"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "vpshufb xmm0, xmm1, xmm2": {

unittests/InstructionCountCI/AVX128/VEX_map2_AFP.json

@@ -8,7 +8,7 @@
       "SVE256",
       "SVE128"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "vfmadd132ss xmm0, xmm1, xmm2": {

unittests/InstructionCountCI/AVX128/VEX_map2_DOTPROD.json

@@ -12,7 +12,7 @@
       "SVE256",
       "I8MM"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "vpdpbusd xmm0, xmm1, xmm2": {

unittests/InstructionCountCI/AVX128/VEX_map2_I8MM.json

@@ -11,7 +11,7 @@
       "SVE128",
       "SVE256"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "vpdpbusd xmm0, xmm1, xmm2": {

unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json

@@ -10,7 +10,7 @@
       "FLAGM2",
       "SVE256"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "vmovntdqa xmm0, [rax]": {

unittests/InstructionCountCI/AVX128/VEX_map2_flagm.json

@@ -11,7 +11,7 @@
       "SVE256",
       "SVEBITPERM"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "vtestps xmm0, xmm1": {

unittests/InstructionCountCI/AVX128/VEX_map3.json

@@ -7,7 +7,7 @@
       "SVE256",
       "SVE128"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "vpermq ymm0, ymm1, 1": {

unittests/InstructionCountCI/AVX128/VEX_map3_SVE128.json

@@ -8,7 +8,7 @@
       "AFP",
       "SVE256"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "vblendvps xmm0, xmm1, xmm2, xmm3": {

unittests/InstructionCountCI/AVX128/VEX_map_group.json

@@ -9,7 +9,7 @@
       "SVE256",
       "SVE128"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "vpsrlw xmm0, xmm1, 0": {

unittests/InstructionCountCI/Atomics.json

@@ -9,7 +9,7 @@
       "FLAGM",
       "FLAGM2"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "lock add byte [rax], cl": {

unittests/InstructionCountCI/Crypto/H0F38.json

@@ -9,7 +9,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "sha1nexte xmm0, xmm1": {

unittests/InstructionCountCI/Crypto/H0F38_SVE128.json

@@ -9,7 +9,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "sha1nexte xmm0, xmm1": {

unittests/InstructionCountCI/Crypto/H0F3A.json

@@ -9,7 +9,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "pclmulqdq xmm0, xmm1, 00000b": {

unittests/InstructionCountCI/DDD.json

@@ -10,7 +10,7 @@
       "AFP",
       "RPRES"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Comment": [
     "These 3DNow! instructions are optimal assuming that FEX doesn't SRA MMX registers",

unittests/InstructionCountCI/FEXOpt/AddressingLimitations.json

@@ -8,7 +8,7 @@
       "RPRES",
       "AFP"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Comment": [
     "Instructions that explicitly push against the limits of ARM's loadstore instructions"

unittests/InstructionCountCI/FEXOpt/AddressingLimitations_32Bit.json

@@ -8,7 +8,7 @@
       "RPRES",
       "AFP"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Comment": [
     "Instructions that explicitly push against the limits of ARM's loadstore instructions"

unittests/InstructionCountCI/FEXOpt/MultiInst.json

@@ -13,7 +13,7 @@
       "RPRES",
       "AFP"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Comment": [
     "These are instruction combinations that could be more optimal if FEX optimized for them"

unittests/InstructionCountCI/FEXOpt/MultiInst_32bit.json

@@ -11,7 +11,7 @@
       "RPRES",
       "AFP"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Comment": [
     "These are instruction combinations that could be more optimal if FEX optimized for them"

unittests/InstructionCountCI/FEXOpt/MultiInst_AFP.json

@@ -9,7 +9,7 @@
       "SVE256",
       "RPRES"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Comment": [
     "These are instruction combinations that could be more optimal if FEX optimized for them"

unittests/InstructionCountCI/FEXOpt/MultiInst_TSO.json

@@ -14,7 +14,7 @@
       "RPRES",
       "AFP"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Comment": [
     "These are instruction combinations that could be more optimal if FEX optimized for them"

unittests/InstructionCountCI/FEXOpt/MultiInst_TSO_32bit.json

@@ -14,7 +14,7 @@
       "RPRES",
       "AFP"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Comment": [
     "These are instruction combinations that could be more optimal if FEX optimized for them"

unittests/InstructionCountCI/FEXOpt/Peephole.json

@@ -13,7 +13,7 @@
       "I8MM",
       "DOTPROD"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Comment": [
     "This file tracks the translations for the 'peephole' optimizations in FEX.",

unittests/InstructionCountCI/FEXOpt/Peephole_SVE128.json

@@ -10,7 +10,7 @@
       "FLAGM2",
       "SVE256"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Comment": [
     "This file tracks the translations for the 'peephole' optimizations in FEX.",

unittests/InstructionCountCI/FEXOpt/libnss.json

@@ -12,7 +12,7 @@
       "RPRES",
       "AFP"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Comment": [],
   "Instructions": {

unittests/InstructionCountCI/FlagM/Atomics.json

@@ -10,7 +10,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "lock add byte [rax], cl": {

unittests/InstructionCountCI/FlagM/FlagOpts.json

@@ -9,7 +9,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "Chained add": {

unittests/InstructionCountCI/FlagM/H0F38.json

@@ -10,7 +10,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "ptest xmm0, xmm1": {

unittests/InstructionCountCI/FlagM/HotBlocks.json

@@ -10,7 +10,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "The Witcher 3": {

unittests/InstructionCountCI/FlagM/HotBlocks_32Bit.json

@@ -10,7 +10,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "Sonic Mania movie player": {

unittests/InstructionCountCI/FlagM/HotBlocks_AFP.json

@@ -10,7 +10,7 @@
       "SVE128",
       "SVE256"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "FMOD scalar loop": {

unittests/InstructionCountCI/FlagM/HotBlocks_TSO_32Bit.json

@@ -13,7 +13,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "The Sims 1 hot block": {

unittests/InstructionCountCI/FlagM/Primary.json

@@ -10,7 +10,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "add bl, cl": {

unittests/InstructionCountCI/FlagM/PrimaryGroup.json

@@ -10,7 +10,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "add al, 1": {

unittests/InstructionCountCI/FlagM/Primary_32Bit.json

@@ -10,7 +10,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "push es": {

unittests/InstructionCountCI/FlagM/Secondary.json

@@ -11,7 +11,7 @@
       "RPRES",
       "AFP"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "ucomiss xmm0, xmm1": {

unittests/InstructionCountCI/FlagM/SecondaryGroup.json

@@ -11,7 +11,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "sgdt [rax]": {

unittests/InstructionCountCI/FlagM/SecondaryModRM.json

@@ -11,7 +11,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "xgetbv": {

unittests/InstructionCountCI/FlagM/Secondary_OpSize.json

@@ -11,7 +11,7 @@
       "AFP",
       "FCMA"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "ucomisd xmm0, xmm1": {

unittests/InstructionCountCI/FlagM/Secondary_REP.json

@@ -12,7 +12,7 @@
       "AFP",
       "CSSC"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "popcnt ax, bx": {

unittests/InstructionCountCI/FlagM/Secondary_REP_CSSC.json

@@ -12,7 +12,7 @@
       "RPRES",
       "AFP"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "popcnt ax, bx": {

unittests/InstructionCountCI/FlagM/VEX_map1.json

@@ -12,7 +12,7 @@
       "RPRES",
       "AFP"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "vucomiss xmm0, xmm1": {

unittests/InstructionCountCI/FlagM/VEX_map2.json

@@ -10,7 +10,7 @@
       "AFP",
       "SVEBITPERM"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "vtestps xmm0, xmm1": {

unittests/InstructionCountCI/FlagM/VEX_map_group.json

@@ -9,7 +9,7 @@
     "DisabledHostFeatures": [
       "AFP"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "blsr eax, ebx": {

unittests/InstructionCountCI/FlagM/x87-Crysis2Max-fmodel.json

@@ -10,7 +10,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "Block1": {

unittests/InstructionCountCI/FlagM/x87-HalfLife.json

@@ -10,7 +10,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "Block1": {

unittests/InstructionCountCI/FlagM/x87-Oblivion.json

@@ -10,7 +10,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "Block1": {

unittests/InstructionCountCI/FlagM/x87-Psychonauts.json

@@ -10,7 +10,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "Block1": {

unittests/InstructionCountCI/FlagM/x87.json

@@ -11,7 +11,7 @@
       "CSSC",
       "AFP"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "fadd dword [rax]": {

unittests/InstructionCountCI/FlagM/x87_f64-Crysis2Max-fmodel.json

@@ -13,7 +13,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "Block1": {

unittests/InstructionCountCI/FlagM/x87_f64-HalfLife.json

@@ -13,7 +13,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "Block1": {

unittests/InstructionCountCI/FlagM/x87_f64-Oblivion.json

@@ -13,7 +13,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "Block1": {

unittests/InstructionCountCI/FlagM/x87_f64-Psychonauts.json

@@ -13,7 +13,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "Block1": {

unittests/InstructionCountCI/FlagM/x87_f64.json

@@ -13,7 +13,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "fadd dword [rax]": {

unittests/InstructionCountCI/H0F38.json

@@ -10,7 +10,7 @@
       "FLAGM2",
       "CRYPTO"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "pshufb mm0, mm1": {

unittests/InstructionCountCI/H0F3A.json

@@ -8,7 +8,7 @@
       "AFP",
       "CRYPTO"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Comment": [
     "SSE4.2 string instructions are skipped here.",

unittests/InstructionCountCI/H0F3A_SVE128.json

@@ -8,7 +8,7 @@
       "SVE256",
       "AFP"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "dpps xmm0, xmm1, 00000000b": {

unittests/InstructionCountCI/MOPS/Primary.json

@@ -11,7 +11,7 @@
       "FLAGM",
       "FLAGM2"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "rep movsb": {

unittests/InstructionCountCI/Primary.json

@@ -10,7 +10,7 @@
       "FLAGM2",
       "MOPS"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "add bl, cl": {

unittests/InstructionCountCI/PrimaryGroup.json

@@ -9,7 +9,7 @@
       "FLAGM",
       "FLAGM2"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Comment": [
     "Instructions in this table that are marked optimal don't have their flag calculation part of this assumption",

unittests/InstructionCountCI/Primary_32Bit.json

@@ -9,7 +9,7 @@
       "FlagM",
       "FlagM2"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "push es": {

unittests/InstructionCountCI/RPRES/DDD.json

@@ -9,7 +9,7 @@
       "SVE128",
       "SVE256"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "pfrcpv mm0, mm1": {

unittests/InstructionCountCI/RPRES/Secondary.json

@@ -9,7 +9,7 @@
       "SVE128",
       "SVE256"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "rsqrtps xmm0, xmm1": {

unittests/InstructionCountCI/RPRES/Secondary_REP_AFP.json

@@ -9,7 +9,7 @@
       "SVE128",
       "SVE256"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "rsqrtss xmm0, xmm1": {

unittests/InstructionCountCI/RPRES/VEX_map1_AFP.json

@@ -8,7 +8,7 @@
       "AFP"
     ],
     "DisabledHostFeatures": [],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "vrsqrtps xmm0, xmm1": {

unittests/InstructionCountCI/Repeat.json

@@ -6,7 +6,7 @@
       "SVE128",
       "SVE256"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {}
 }

unittests/InstructionCountCI/SSE42_Strings.json

@@ -33,7 +33,7 @@
       "      - 1b: ECX = MSB",
       "[7]   - Reserved"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "pcmpestrm xmm0, xmm1, 0_0_00_00_00b": {

unittests/InstructionCountCI/Secondary.json

@@ -12,7 +12,7 @@
       "FLAGM",
       "FLAGM2"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Comment": [
     "MMX instructions are defined as optimal without SRA being used for these instructions.",

unittests/InstructionCountCI/SecondaryGroup.json

@@ -12,7 +12,7 @@
       "FLAGM2",
       "TPIDRRO"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "sgdt [rax]": {

unittests/InstructionCountCI/SecondaryModRM.json

@@ -11,7 +11,7 @@
       "FLAGM",
       "FLAGM2"
     ],
-    "BinaryCacheVersion": 42
+    "BinaryCacheVersion": 43
   },
   "Instructions": {
     "xgetbv": {