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1357 Commits

Author SHA1 Message Date
Lioncache
9e54ec2724 OpcodeDispatcher: Improve {V}PSRLDQ shift by 0 
While it would be bizarre if this actually occurred frequently
in practice, we can still tune it so there's no subpar assembly
output in the cases it actually does happen.
 2023-08-17 19:33:09 -04:00
Ryan Houdek
461ca6fe7c
Merge pull request #2921 from lioncash/shift 
OpcodeDispatcher: Remove unnecessary conditionals in {V}PSLLIOp
 2023-08-17 16:03:16 -07:00
Lioncache
5a1f32c339 OpcodeDispatcher: Remove unnecessary conditionals in {V}PSLLIOp 
PSLLIImpl already checks for and handles a shift value of zero.
 2023-08-17 18:47:50 -04:00
Lioncache
01515cea2c OpcodeDispatcher: Improve VMOVDDUP output 
We can make use of TRN1 here to collapse a bunch of these moves.
 2023-08-17 18:30:44 -04:00
Lioncache
764c844225 OpcodeDispatcher: Improve output of {V}MOVSHDUP 2023-08-17 17:01:50 -04:00
Lioncache
31719aac6a OpcodeDispatcher: Improve output of {V}MOVSLDUP 2023-08-17 17:01:46 -04:00
Alyssa Rosenzweig
af21b8f3c7 Move External/FEXCore/ to FEXCore/ 
It is not an external component, and it makes paths needlessly long.
Ryan seemed amenable to this when we discussed on IRC earlier.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2023-08-17 16:32:16 -04:00