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1357 Commits

Author SHA1 Message Date
Ryan Houdek
13ebfb1a49
Merge pull request #3711 from Sonicadvance1/avx128_2 
FEXCore: Disentangle the SVE256 feature from AVX
 2024-06-17 17:35:15 -07:00
Ryan Houdek
f863b30951
Merge pull request #3716 from alyssarosenzweig/ir-dump/unrecoverable 
json_ir_generator: don't print unrecoverable temps
 2024-06-17 17:25:27 -07:00
Ryan Houdek
1ce27a5e6b
FEXCore: Disentangle the SVE256 feature from AVX 
In quite a few locations we are mixing the case that SVE256 == AVX or
that AVX means the guest register size is 256-bit.

While this is true today, this is entanglement is going to change very
quickly and cause confusion in follow-up PRs.

Now we have SVE128, SVE256, and SVE2 HostFeatures to disambiguate the
different features which mean different things.

This PR keeps the alias that `SupportsAVX` = `SupportsSVE256 && SupportsSVE2`
but that alias is going to very quickly change its definition.
 2024-06-17 17:20:32 -07:00
Ryan Houdek
933d622860
Merge pull request #3710 from Sonicadvance1/avx128_1 
CoreState: Move `InlineJITBlockHeader` to the start of the struct
 2024-06-17 17:17:56 -07:00
Alyssa Rosenzweig
29390b439a json_ir_generator: don't print unrecoverable temps 
this makes the print more noisy for no benefit, don't do it.

before:

    %9(GPRFixed16) i32 = Add OpSize:Tmp:Size, %6(GPRFixed0) i64, %17(Invalid)
    %10(GPR0) i64 = Bfi OpSize:Tmp:Size, #0x10, #0x0, %6(GPRFixed0) i64, %9(GPRFixed16) i32
    (%11 i64) StoreRegister %6(GPRFixed0) i64, #0x11, GPR, u8:Tmp:Size
    (%12 i64) StoreRegister %9(GPRFixed16) i32, #0x10, GPR, u8:Tmp:Size
    (%13 i64) StoreRegister %10(GPR0) i64, #0x0, GPR, u8:Tmp:Size

after:

    %9(GPRFixed16) i32 = Add %6(GPRFixed0) i64, %17(Invalid)
    %10(GPR0) i64 = Bfi #0x10, #0x0, %6(GPRFixed0) i64, %9(GPRFixed16) i32
    (%11 i64) StoreRegister %6(GPRFixed0) i64, #0x11, GPR
    (%12 i64) StoreRegister %9(GPRFixed16) i32, #0x10, GPR
    (%13 i64) StoreRegister %10(GPR0) i64, #0x0, GPR

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-06-17 14:58:56 -04:00
Alyssa Rosenzweig
799c17eb90 Arm64Emitter: drop out of date comment 
I fixed this when we landed the new RA

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-06-17 14:58:08 -04:00
Alyssa Rosenzweig
5fb84866e0 json_ir_generator: rework argument printing 
for next commit

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-06-17 14:40:29 -04:00
Alyssa Rosenzweig
4965344ef5
Merge pull request #3705 from alyssarosenzweig/pre-rclse 
Clean ups from my RCLSE branch
 2024-06-17 14:22:01 -04:00
Alyssa Rosenzweig
46ca53ad0d
Merge pull request #3704 from alyssarosenzweig/ra/spill-better 
RA: priorize remat over spilling
 2024-06-17 09:01:50 -04:00
Alyssa Rosenzweig
61ff1b3584
Merge pull request #3712 from alyssarosenzweig/jit/silly-assert 
JIT: delete silly assert
 2024-06-17 08:59:00 -04:00
Alyssa Rosenzweig
7c0c5de4bd JIT: delete silly assert 
noticed in the area.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-06-17 08:51:22 -04:00
Ryan Houdek
a9bacc1b6b
CoreState: Move InlineJITBlockHeader to the start of the struct 
This currently doesn't do much but soon this will be very important to
ensure the data prefetcher of Cortex keeps the cachelines following this
variable in L1.
 2024-06-17 02:59:56 -07:00
Alyssa Rosenzweig
9443b18076 RegisterAllocationPass: optimize spill loop 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-06-16 08:15:15 -04:00
Alyssa Rosenzweig
4bd84eb523 OpcodeDispatcher: extract PF/AF invalidate helpers 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-06-15 20:23:47 -04:00
Alyssa Rosenzweig
e2073dcd30 OpcodeDispatcher: extract safe Thunk 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-06-15 20:23:47 -04:00
Alyssa Rosenzweig
fd72669c7e OpcodeDispatcher: extract safe Break 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-06-15 20:23:47 -04:00
Alyssa Rosenzweig
81c144697b OpcodeDispatcher: extract safe ExitFunction 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-06-15 20:23:47 -04:00
Alyssa Rosenzweig
aecf180dfe OpcodeDispatcher: extract FlushRegisterCache 
The "end the clause" signal. for now just flushes flags.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-06-15 20:23:47 -04:00
Alyssa Rosenzweig
10fa4a4f20 OpcodeDispatcher: remove never-gonna-be-done todo 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-06-15 20:23:47 -04:00
Alyssa Rosenzweig
534732564b OpcodeDispatcher: drop pointless thunks for packss 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-06-15 20:23:46 -04:00
Alyssa Rosenzweig
6a314bc9cd RegisterAllocationPass: prioritize remat over spilling 
No instcountci changes yet, since nothing currently spills in instcountci. This
mitigates spilling later seen with #3703, and should help for certain
pathological blocks even without those changes (maybe we should try to get some
of those blocks in instcountci?).

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-06-15 20:21:57 -04:00
Ryan Houdek
1d1ed012d8
FEXCore: Fixes Call with 32-bit displacement and address size override 
FEX had a bug with this instruction where it was incorrectly using both
the address size override and operand size override to truncate the
immediate offset. This isn't how the instruction should behave as it
should actually ignore the address size override.

This now puts it correctly inline with how the jump instruction works
and adds a unit test to ensure it doesn't break again.

This fixes a crash from the Arch rootfs from the glibc dynamic linker
being compiling in a way where a call instruction was getting aligned
using this prefix (Since the compiler knew it does nothing).
 2024-06-14 14:00:35 -07:00
Lioncache
d133fa6dc1 ASIMD Tests: Remove erroneous disassembly tests 
The vixl disassembler has gotten more strict about certain instruction types, so these tests
aren't really needed.

Alternatively, we could mark them as unallocated, but we can opt to remove them here.
 2024-06-14 16:12:21 -04:00
Ryan Houdek
184c9d21bb
Revert "OpcodeDispatcher: optimize logical flags" 
This reverts commit bb8336fcad9cf5619215e5a9f765ca48c7d48970.
 2024-06-13 19:28:16 -07:00
Alyssa Rosenzweig
a8bf3859ea ConstProp: rm pointless constant folding 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-06-04 10:09:51 -04:00
Alyssa Rosenzweig
aa7dcffcea ConstProp: drop const pool heuristic 
slightly worse for compile time, slightly better output, honestly I'll take the
win because this is easier to reason about.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-06-04 10:09:51 -04:00
Alyssa Rosenzweig
be1a5cea8e ConstProp: drop addressgen const pool stuff 
I don't get the point, it should be handled by a combination of existing
passes/techniques just fine. no instcountci changes.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-06-04 10:09:51 -04:00
Alyssa Rosenzweig
402ea84aa0 RedundantFlagCalculationElimination: cleanup DCE 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-06-04 10:09:51 -04:00
Alyssa Rosenzweig
19a7b06b91 ConstProp: swallow up LongDivideElimination 
as usual.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-06-04 10:09:51 -04:00
Alyssa Rosenzweig
96bd643e5b ConstProp: always inline constants 
x86/interpreter leftover, I think.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-06-04 10:09:51 -04:00
Alyssa Rosenzweig
6b9293979c ConstProp: swallow up InlineCallOptimization 
No reason to have a separate pass for this, merging should be a bit faster since
it eliminates an IR walk.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-06-04 10:09:51 -04:00
Alyssa Rosenzweig
7d5cee4384 InlineCallOptimization: rm x86 leftover 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-06-04 10:09:51 -04:00
Alyssa Rosenzweig
32f5a28433 IR: use Ref instead of OrderedNode 
find-and-replace across the tree, excluding IR.h itself.

also excluded IRValidation because its treatment of blocks blows up and will be
reformed in the new IR anyway.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-06-03 12:19:34 -04:00
Alyssa Rosenzweig
ce30179ed1 IR: add Ref typedef 
To put new IR lipstick on the old IR pig.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-06-03 12:19:34 -04:00
Alyssa Rosenzweig
a515b707f3
Merge pull request #3679 from Sonicadvance1/memory_model_emulation_programmer_documentation 
FEXCore/docs: Adds programmer documentation about memory model emulation
 2024-06-03 09:24:37 -04:00
Alyssa Rosenzweig
951fee361f OpcodeDispatcher: optimize shld 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-06-01 14:44:24 -04:00
Alyssa Rosenzweig
abfd974d70 OpcodeDispatcher: select hardware addressing modes 
Now that we have a framework to do this in.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-06-01 09:42:50 -04:00
Alyssa Rosenzweig
97966930e9 OpcodeDispatcher/x87f64: fuse addr calc 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-06-01 09:42:33 -04:00
Alyssa Rosenzweig
a52a2e3ae4 OpcodeDispatcher/x87: fuse addr 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-06-01 09:42:33 -04:00
Alyssa Rosenzweig
c49b30f105 OpcodeDispatcher/Vector: fuse addr calc 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-06-01 09:42:33 -04:00
Alyssa Rosenzweig
b0b4ad2083 OpcodeDispatcher: fuse xlat address 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-06-01 09:42:33 -04:00
Alyssa Rosenzweig
ee4bee4fef OpcodeDispatcher: fuse BT address 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-06-01 09:42:33 -04:00
Alyssa Rosenzweig
c3a0f5a2f6 OpcodeDispatcher: fuse sgdt 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-06-01 09:42:33 -04:00
Alyssa Rosenzweig
0413a6bf68 OpcodeDispatcher: improve bmi2 shift 
allow upper garbage, use simpler clean.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-06-01 09:42:33 -04:00
Alyssa Rosenzweig
7bd036d1ae OpcodeDispatcher: refactor address modes 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-06-01 09:42:32 -04:00
Alyssa Rosenzweig
112c49a348 ConstProp: fix inlining shifted imm to mem instructions 
hit by sse4_1-pmaxuw.c.gcc-target-test-64.jit.gcc-target-64

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-05-31 17:42:48 -04:00
Alyssa Rosenzweig
80878ae611 ConstProp: rework mem immediate inlining 
deduplicate all the things.

functional change:
hit by sse4_1-pmaxuw.c.gcc-target-test-64.jit.gcc-target-64

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-05-31 17:42:48 -04:00
Alyssa Rosenzweig
85a69be5b6 ConstProp: drop address fusion 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-05-31 17:38:03 -04:00
Ryan Houdek
8dbfd1635a
FEXCore/docs: Adds programmer documentation about memory model emulation 
I keep needing to look these up to remember the limitations. Add a doc
file so I can more easily point to the information.
 2024-05-31 10:36:48 -07:00
Alyssa Rosenzweig
8b5ca303e3 JIT: add asserts for invalid TSO load/store 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-05-31 12:12:36 -04:00