12 Commits

Author SHA1 Message Date
Stefanos Kornilios Mitsis Poiitidis
8b025d4c26 IRLoader: Actually set EntryRIP if the IR was parsed 2021-01-21 22:19:16 +02:00
Stefanos Kornilios Mitsis Poiitidis
278e156a8a Tests: Move timeout to ctest from python + timeout 2021-01-09 19:26:15 +02:00
Stefanos Kornilios Mitsis Poiitidis
7cc2404c63 Tests: Correctly match test cases 2021-01-09 19:08:46 +02:00
Stefanos Kornilios Mitsis Poiitidis
1073d4053d IR Tests: Update LoadMem to use extended syntax 2020-11-17 16:23:50 +02:00
Ryan Houdek
7c14619346 Support disabling ASM and IR tests per runner type
Allows us to disable specific tests for interpreter, jit, or host.
No architecture specific disabling yet
2020-09-25 21:17:54 -07:00
Scott Mansell
6dadf81001 x64jit: FPR 8/16bit Load Context/Mem should zext
Fixes OpenGL corruption issue in FTL with previous commits

Also includes an ir test
2020-08-26 00:47:40 +12:00
Scott Mansell
69703af624 Add some ir tests to formalize ALU truncation 2020-08-26 00:47:40 +12:00
Scott Mansell
cb6dcf62eb Add MemoryData to IR and ASM Tests 2020-08-21 01:29:37 +12:00
Ryan Houdek
e7058c8575 Removes LLVM from unit tests 2020-08-19 17:20:22 -07:00
Ryan Houdek
263ceb7086 Cleans up ASM unit test file generation
This allows the generated files to maintain the same folder structure as
how they exist in the source folder.
Resolves the issue that a file in a different folder could potentially
conflict with another in a different folder but have the same name.
This is an easier mental model when pulling unit tests in to a
disassembler for verifying codegen.
2020-06-10 19:44:27 -07:00
Ryan Houdek
2474ca1437 Adds support for disabled tests in the IR and ASM runners 2020-05-28 15:09:51 -07:00
Ryan Houdek
6cdd3916c0 Adds IR based unit test support.
Now that everything is punched through that is necessary, we can now
have IR based unit tests that will be used to ensure the IR is working
correctly.
Specifically this is necessary for quick iterating on RA testing.
2020-05-09 12:19:36 -07:00