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am33xx updates via Paul Walmsley <paul@pwsan.com>:

Browse Source 
Fixes and IP block support for the TI AM33xx family of SoCs.  These
 are prerequisites for power management and some PWM driver changes.
 
 Basic test logs are available from:
 
    http://www.pwsan.com/omap/testlogs/am33xx_fixes_a_3.9/20130208084835/
 
 although it must be noted that I am unable to test these patches on
 AM33xx due to an unknown problem with v3.8-rc kernels:
 
    http://www.mail-archive.com/linux-omap@vger.kernel.org/msg83525.html
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Merge tag 'omap-for-v3.9/am33xx-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into late/omap

From Tony Lindgren:
am33xx updates via Paul Walmsley <paul@pwsan.com>:

Fixes and IP block support for the TI AM33xx family of SoCs.  These
are prerequisites for power management and some PWM driver changes.

Basic test logs are available from:

   http://www.pwsan.com/omap/testlogs/am33xx_fixes_a_3.9/20130208084835/

although it must be noted that I am unable to test these patches on
AM33xx due to an unknown problem with v3.8-rc kernels:

   http://www.mail-archive.com/linux-omap@vger.kernel.org/msg83525.html

* tag 'omap-for-v3.9/am33xx-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: OMAP2: am33xx-hwmod: Fix "register offset NULL check" bug
  ARM: OMAP2+: AM33xx: hwmod: add missing HWMOD_NO_IDLEST flags
  ARM: OMAP: AM33xx hwmod: Add parent-child relationship for PWM subsystem
  ARM: OMAP: AM33xx hwmod: Corrects PWM subsystem HWMOD entries
  ARM: DTS: AM33XX: Add nodes for OCMC RAM and WKUP-M3
  ARM: OMAP2+: AM33XX: Update the hardreset API
  ARM: OMAP2+: AM33XX: hwmod: Update the WKUP-M3 hwmod with reset status bit
  ARM: OMAP2+: AM33XX: hwmod: Fixup cpgmac0 hwmod entry
  ARM: OMAP2+: AM33XX: hwmod: Update TPTC0 hwmod with the right flags
  ARM: OMAP2+: AM33XX: hwmod: Register OCMC RAM hwmod
  ARM: OMAP2+: AM33XX: CM/PRM: Use __ASSEMBLER__ macros in header files
  ARM: OMAP2+: AM33XX: CM: Get rid of unnecessary header inclusions
This commit is contained in:
Olof Johansson 2013-02-12 15:32:31 -08:00
commit 0a0db4a1e4
7 changed files with 332 additions and 209 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
arch/arm/boot/dts/am33xx.dtsi
View File

@ -385,5 +385,19 @@
mac-address = [ 00 00 00 00 00 00 ]; mac-address = [ 00 00 00 00 00 00 ];
}; };
}; };
ocmcram: ocmcram@40300000 {
compatible = "ti,am3352-ocmcram";
reg = <0x40300000 0x10000>;
ti,hwmods = "ocmcram";
ti,no_idle_on_suspend;
};
wkup_m3: wkup_m3@44d00000 {
compatible = "ti,am3353-wkup-m3";
reg = <0x44d00000 0x4000 /* M3 UMEM */
0x44d80000 0x2000>; /* M3 DMEM */
ti,hwmods = "wkup_m3";
};
}; };
}; };

3
arch/arm/mach-omap2/cm33xx.c
View File

@ -241,9 +241,6 @@ int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs, u16 clkctrl_offs)
{ {
int i = 0; int i = 0;
if (!clkctrl_offs)
return 0;
omap_test_timeout(_is_module_ready(inst, cdoffs, clkctrl_offs), omap_test_timeout(_is_module_ready(inst, cdoffs, clkctrl_offs),
MAX_MODULE_READY_TIME, i); MAX_MODULE_READY_TIME, i);

9
arch/arm/mach-omap2/cm33xx.h
View File

@ -17,16 +17,11 @@
#ifndef __ARCH_ARM_MACH_OMAP2_CM_33XX_H #ifndef __ARCH_ARM_MACH_OMAP2_CM_33XX_H
#define __ARCH_ARM_MACH_OMAP2_CM_33XX_H #define __ARCH_ARM_MACH_OMAP2_CM_33XX_H
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/io.h>
#include "common.h" #include "common.h"
#include "cm.h" #include "cm.h"
#include "cm-regbits-33xx.h" #include "cm-regbits-33xx.h"
#include "cm33xx.h" #include "iomap.h"
/* CM base address */ /* CM base address */
#define AM33XX_CM_BASE 0x44e00000 #define AM33XX_CM_BASE 0x44e00000
@ -381,6 +376,7 @@
#define AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_CEFUSE_MOD, 0x0020) #define AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_CEFUSE_MOD, 0x0020)
#ifndef __ASSEMBLER__
extern bool am33xx_cm_is_clkdm_in_hwsup(s16 inst, u16 cdoffs); extern bool am33xx_cm_is_clkdm_in_hwsup(s16 inst, u16 cdoffs);
extern void am33xx_cm_clkdm_enable_hwsup(s16 inst, u16 cdoffs); extern void am33xx_cm_clkdm_enable_hwsup(s16 inst, u16 cdoffs);
extern void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs); extern void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs);
@ -417,4 +413,5 @@ static inline int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs,
} }
#endif #endif
#endif /* ASSEMBLER */
#endif #endif

5
arch/arm/mach-omap2/omap_hwmod.c
View File

@ -3041,11 +3041,8 @@ static int _am33xx_assert_hardreset(struct omap_hwmod *oh,
static int _am33xx_deassert_hardreset(struct omap_hwmod *oh, static int _am33xx_deassert_hardreset(struct omap_hwmod *oh,
struct omap_hwmod_rst_info *ohri) struct omap_hwmod_rst_info *ohri)
{ {
if (ohri->st_shift)
pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n",
oh->name, ohri->name);
return am33xx_prm_deassert_hardreset(ohri->rst_shift, return am33xx_prm_deassert_hardreset(ohri->rst_shift,
ohri->st_shift,
oh->clkdm->pwrdm.ptr->prcm_offs, oh->clkdm->pwrdm.ptr->prcm_offs,
oh->prcm.omap4.rstctrl_offs, oh->prcm.omap4.rstctrl_offs,
oh->prcm.omap4.rstst_offs); oh->prcm.omap4.rstst_offs);

491
arch/arm/mach-omap2/omap_hwmod_33xx_data.c
View File

@ -262,13 +262,15 @@ static struct omap_hwmod am33xx_wkup_m3_hwmod = {
.name = "wkup_m3", .name = "wkup_m3",
.class = &am33xx_wkup_m3_hwmod_class, .class = &am33xx_wkup_m3_hwmod_class,
.clkdm_name = "l4_wkup_aon_clkdm", .clkdm_name = "l4_wkup_aon_clkdm",
.flags = HWMOD_INIT_NO_RESET, /* Keep hardreset asserted */ /* Keep hardreset asserted */
.flags = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
.mpu_irqs = am33xx_wkup_m3_irqs, .mpu_irqs = am33xx_wkup_m3_irqs,
.main_clk = "dpll_core_m4_div2_ck", .main_clk = "dpll_core_m4_div2_ck",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
.clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET, .clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
.rstctrl_offs = AM33XX_RM_WKUP_RSTCTRL_OFFSET, .rstctrl_offs = AM33XX_RM_WKUP_RSTCTRL_OFFSET,
.rstst_offs = AM33XX_RM_WKUP_RSTST_OFFSET,
.modulemode = MODULEMODE_SWCTRL, .modulemode = MODULEMODE_SWCTRL,
}, },
}, },
@ -414,7 +416,6 @@ static struct omap_hwmod am33xx_adc_tsc_hwmod = {
* - cEFUSE (doesn't fall under any ocp_if) * - cEFUSE (doesn't fall under any ocp_if)
* - clkdiv32k * - clkdiv32k
* - debugss * - debugss
* - ocmc ram
* - ocp watch point * - ocp watch point
* - aes0 * - aes0
* - sha0 * - sha0
@ -481,25 +482,6 @@ static struct omap_hwmod am33xx_debugss_hwmod = {
}, },
}; };
/* ocmcram */
static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
.name = "ocmcram",
};
static struct omap_hwmod am33xx_ocmcram_hwmod = {
.name = "ocmcram",
.class = &am33xx_ocmcram_hwmod_class,
.clkdm_name = "l3_clkdm",
.flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
.main_clk = "l3_gclk",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* ocpwp */ /* ocpwp */
static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = { static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
.name = "ocpwp", .name = "ocpwp",
@ -570,6 +552,25 @@ static struct omap_hwmod am33xx_sha0_hwmod = {
#endif #endif
/* ocmcram */
static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
.name = "ocmcram",
};
static struct omap_hwmod am33xx_ocmcram_hwmod = {
.name = "ocmcram",
.class = &am33xx_ocmcram_hwmod_class,
.clkdm_name = "l3_clkdm",
.flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
.main_clk = "l3_gclk",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* 'smartreflex' class */ /* 'smartreflex' class */
static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = { static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
.name = "smartreflex", .name = "smartreflex",
@ -783,9 +784,7 @@ static struct omap_hwmod am33xx_elm_hwmod = {
}, },
}; };
/* /* pwmss */
* 'epwmss' class: ecap0,1,2, ehrpwm0,1,2
*/
static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = { static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
.rev_offs = 0x0, .rev_offs = 0x0,
.sysc_offs = 0x4, .sysc_offs = 0x4,
@ -801,18 +800,23 @@ static struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
.sysc = &am33xx_epwmss_sysc, .sysc = &am33xx_epwmss_sysc,
}; };
/* ehrpwm0 */ static struct omap_hwmod_class am33xx_ecap_hwmod_class = {
static struct omap_hwmod_irq_info am33xx_ehrpwm0_irqs[] = { .name = "ecap",
{ .name = "int", .irq = 86 + OMAP_INTC_START, },
{ .name = "tzint", .irq = 58 + OMAP_INTC_START, },
{ .irq = -1 },
}; };
static struct omap_hwmod am33xx_ehrpwm0_hwmod = { static struct omap_hwmod_class am33xx_eqep_hwmod_class = {
.name = "ehrpwm0", .name = "eqep",
};
static struct omap_hwmod_class am33xx_ehrpwm_hwmod_class = {
.name = "ehrpwm",
};
/* epwmss0 */
static struct omap_hwmod am33xx_epwmss0_hwmod = {
.name = "epwmss0",
.class = &am33xx_epwmss_hwmod_class, .class = &am33xx_epwmss_hwmod_class,
.clkdm_name = "l4ls_clkdm", .clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_ehrpwm0_irqs,
.main_clk = "l4ls_gclk", .main_clk = "l4ls_gclk",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
@ -822,48 +826,6 @@ static struct omap_hwmod am33xx_ehrpwm0_hwmod = {
}, },
}; };
/* ehrpwm1 */
static struct omap_hwmod_irq_info am33xx_ehrpwm1_irqs[] = {
{ .name = "int", .irq = 87 + OMAP_INTC_START, },
{ .name = "tzint", .irq = 59 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_ehrpwm1_hwmod = {
.name = "ehrpwm1",
.class = &am33xx_epwmss_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_ehrpwm1_irqs,
.main_clk = "l4ls_gclk",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* ehrpwm2 */
static struct omap_hwmod_irq_info am33xx_ehrpwm2_irqs[] = {
{ .name = "int", .irq = 39 + OMAP_INTC_START, },
{ .name = "tzint", .irq = 60 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_ehrpwm2_hwmod = {
.name = "ehrpwm2",
.class = &am33xx_epwmss_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_ehrpwm2_irqs,
.main_clk = "l4ls_gclk",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* ecap0 */ /* ecap0 */
static struct omap_hwmod_irq_info am33xx_ecap0_irqs[] = { static struct omap_hwmod_irq_info am33xx_ecap0_irqs[] = {
{ .irq = 31 + OMAP_INTC_START, }, { .irq = 31 + OMAP_INTC_START, },
@ -872,13 +834,50 @@ static struct omap_hwmod_irq_info am33xx_ecap0_irqs[] = {
static struct omap_hwmod am33xx_ecap0_hwmod = { static struct omap_hwmod am33xx_ecap0_hwmod = {
.name = "ecap0", .name = "ecap0",
.class = &am33xx_epwmss_hwmod_class, .class = &am33xx_ecap_hwmod_class,
.clkdm_name = "l4ls_clkdm", .clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_ecap0_irqs, .mpu_irqs = am33xx_ecap0_irqs,
.main_clk = "l4ls_gclk", .main_clk = "l4ls_gclk",
};
/* eqep0 */
static struct omap_hwmod_irq_info am33xx_eqep0_irqs[] = {
{ .irq = 79 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_eqep0_hwmod = {
.name = "eqep0",
.class = &am33xx_eqep_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_eqep0_irqs,
.main_clk = "l4ls_gclk",
};
/* ehrpwm0 */
static struct omap_hwmod_irq_info am33xx_ehrpwm0_irqs[] = {
{ .name = "int", .irq = 86 + OMAP_INTC_START, },
{ .name = "tzint", .irq = 58 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_ehrpwm0_hwmod = {
.name = "ehrpwm0",
.class = &am33xx_ehrpwm_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_ehrpwm0_irqs,
.main_clk = "l4ls_gclk",
};
/* epwmss1 */
static struct omap_hwmod am33xx_epwmss1_hwmod = {
.name = "epwmss1",
.class = &am33xx_epwmss_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.main_clk = "l4ls_gclk",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
.clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET, .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL, .modulemode = MODULEMODE_SWCTRL,
}, },
}, },
@ -892,13 +891,50 @@ static struct omap_hwmod_irq_info am33xx_ecap1_irqs[] = {
static struct omap_hwmod am33xx_ecap1_hwmod = { static struct omap_hwmod am33xx_ecap1_hwmod = {
.name = "ecap1", .name = "ecap1",
.class = &am33xx_epwmss_hwmod_class, .class = &am33xx_ecap_hwmod_class,
.clkdm_name = "l4ls_clkdm", .clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_ecap1_irqs, .mpu_irqs = am33xx_ecap1_irqs,
.main_clk = "l4ls_gclk", .main_clk = "l4ls_gclk",
};
/* eqep1 */
static struct omap_hwmod_irq_info am33xx_eqep1_irqs[] = {
{ .irq = 88 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_eqep1_hwmod = {
.name = "eqep1",
.class = &am33xx_eqep_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_eqep1_irqs,
.main_clk = "l4ls_gclk",
};
/* ehrpwm1 */
static struct omap_hwmod_irq_info am33xx_ehrpwm1_irqs[] = {
{ .name = "int", .irq = 87 + OMAP_INTC_START, },
{ .name = "tzint", .irq = 59 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_ehrpwm1_hwmod = {
.name = "ehrpwm1",
.class = &am33xx_ehrpwm_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_ehrpwm1_irqs,
.main_clk = "l4ls_gclk",
};
/* epwmss2 */
static struct omap_hwmod am33xx_epwmss2_hwmod = {
.name = "epwmss2",
.class = &am33xx_epwmss_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.main_clk = "l4ls_gclk",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
.clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET, .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL, .modulemode = MODULEMODE_SWCTRL,
}, },
}, },
@ -912,16 +948,39 @@ static struct omap_hwmod_irq_info am33xx_ecap2_irqs[] = {
static struct omap_hwmod am33xx_ecap2_hwmod = { static struct omap_hwmod am33xx_ecap2_hwmod = {
.name = "ecap2", .name = "ecap2",
.mpu_irqs = am33xx_ecap2_irqs, .class = &am33xx_ecap_hwmod_class,
.class = &am33xx_epwmss_hwmod_class,
.clkdm_name = "l4ls_clkdm", .clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_ecap2_irqs,
.main_clk = "l4ls_gclk",
};
/* eqep2 */
static struct omap_hwmod_irq_info am33xx_eqep2_irqs[] = {
{ .irq = 89 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_eqep2_hwmod = {
.name = "eqep2",
.class = &am33xx_eqep_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_eqep2_irqs,
.main_clk = "l4ls_gclk",
};
/* ehrpwm2 */
static struct omap_hwmod_irq_info am33xx_ehrpwm2_irqs[] = {
{ .name = "int", .irq = 39 + OMAP_INTC_START, },
{ .name = "tzint", .irq = 60 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_ehrpwm2_hwmod = {
.name = "ehrpwm2",
.class = &am33xx_ehrpwm_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_ehrpwm2_irqs,
.main_clk = "l4ls_gclk", .main_clk = "l4ls_gclk",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
}; };
/* /*
@ -1824,6 +1883,7 @@ static struct omap_hwmod am33xx_tptc0_hwmod = {
.class = &am33xx_tptc_hwmod_class, .class = &am33xx_tptc_hwmod_class,
.clkdm_name = "l3_clkdm", .clkdm_name = "l3_clkdm",
.mpu_irqs = am33xx_tptc0_irqs, .mpu_irqs = am33xx_tptc0_irqs,
.flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
.main_clk = "l3_gclk", .main_clk = "l3_gclk",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
@ -2496,7 +2556,6 @@ static struct omap_hwmod_addr_space am33xx_cpgmac0_addr_space[] = {
{ {
.pa_start = 0x4a100000, .pa_start = 0x4a100000,
.pa_end = 0x4a100000 + SZ_2K - 1, .pa_end = 0x4a100000 + SZ_2K - 1,
.flags = ADDR_TYPE_RT,
}, },
/* cpsw wr */ /* cpsw wr */
{ {
@ -2547,162 +2606,202 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__elm = {
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
/* static struct omap_hwmod_addr_space am33xx_epwmss0_addr_space[] = {
* Splitting the resources to handle access of PWMSS config space
* and module specific part independently
*/
static struct omap_hwmod_addr_space am33xx_ehrpwm0_addr_space[] = {
{ {
.pa_start = 0x48300000, .pa_start = 0x48300000,
.pa_end = 0x48300000 + SZ_16 - 1, .pa_end = 0x48300000 + SZ_16 - 1,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{
.pa_start = 0x48300200,
.pa_end = 0x48300200 + SZ_256 - 1,
.flags = ADDR_TYPE_RT
},
{ } { }
}; };
static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm0 = { static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0 = {
.master = &am33xx_l4_ls_hwmod, .master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_ehrpwm0_hwmod, .slave = &am33xx_epwmss0_hwmod,
.clk = "l4ls_gclk", .clk = "l4ls_gclk",
.addr = am33xx_ehrpwm0_addr_space, .addr = am33xx_epwmss0_addr_space,
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
/*
* Splitting the resources to handle access of PWMSS config space
* and module specific part independently
*/
static struct omap_hwmod_addr_space am33xx_ehrpwm1_addr_space[] = {
{
.pa_start = 0x48302000,
.pa_end = 0x48302000 + SZ_16 - 1,
.flags = ADDR_TYPE_RT
},
{
.pa_start = 0x48302200,
.pa_end = 0x48302200 + SZ_256 - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm1 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_ehrpwm1_hwmod,
.clk = "l4ls_gclk",
.addr = am33xx_ehrpwm1_addr_space,
.user = OCP_USER_MPU,
};
/*
* Splitting the resources to handle access of PWMSS config space
* and module specific part independently
*/
static struct omap_hwmod_addr_space am33xx_ehrpwm2_addr_space[] = {
{
.pa_start = 0x48304000,
.pa_end = 0x48304000 + SZ_16 - 1,
.flags = ADDR_TYPE_RT
},
{
.pa_start = 0x48304200,
.pa_end = 0x48304200 + SZ_256 - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm2 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_ehrpwm2_hwmod,
.clk = "l4ls_gclk",
.addr = am33xx_ehrpwm2_addr_space,
.user = OCP_USER_MPU,
};
/*
* Splitting the resources to handle access of PWMSS config space
* and module specific part independently
*/
static struct omap_hwmod_addr_space am33xx_ecap0_addr_space[] = { static struct omap_hwmod_addr_space am33xx_ecap0_addr_space[] = {
{
.pa_start = 0x48300000,
.pa_end = 0x48300000 + SZ_16 - 1,
.flags = ADDR_TYPE_RT
},
{ {
.pa_start = 0x48300100, .pa_start = 0x48300100,
.pa_end = 0x48300100 + SZ_256 - 1, .pa_end = 0x48300100 + SZ_128 - 1,
.flags = ADDR_TYPE_RT
}, },
{ } { }
}; };
static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap0 = { static struct omap_hwmod_ocp_if am33xx_epwmss0__ecap0 = {
.master = &am33xx_l4_ls_hwmod, .master = &am33xx_epwmss0_hwmod,
.slave = &am33xx_ecap0_hwmod, .slave = &am33xx_ecap0_hwmod,
.clk = "l4ls_gclk", .clk = "l4ls_gclk",
.addr = am33xx_ecap0_addr_space, .addr = am33xx_ecap0_addr_space,
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
/* static struct omap_hwmod_addr_space am33xx_eqep0_addr_space[] = {
* Splitting the resources to handle access of PWMSS config space {
* and module specific part independently .pa_start = 0x48300180,
*/ .pa_end = 0x48300180 + SZ_128 - 1,
static struct omap_hwmod_addr_space am33xx_ecap1_addr_space[] = { },
{ }
};
static struct omap_hwmod_ocp_if am33xx_epwmss0__eqep0 = {
.master = &am33xx_epwmss0_hwmod,
.slave = &am33xx_eqep0_hwmod,
.clk = "l4ls_gclk",
.addr = am33xx_eqep0_addr_space,
.user = OCP_USER_MPU,
};
static struct omap_hwmod_addr_space am33xx_ehrpwm0_addr_space[] = {
{
.pa_start = 0x48300200,
.pa_end = 0x48300200 + SZ_128 - 1,
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_epwmss0__ehrpwm0 = {
.master = &am33xx_epwmss0_hwmod,
.slave = &am33xx_ehrpwm0_hwmod,
.clk = "l4ls_gclk",
.addr = am33xx_ehrpwm0_addr_space,
.user = OCP_USER_MPU,
};
static struct omap_hwmod_addr_space am33xx_epwmss1_addr_space[] = {
{ {
.pa_start = 0x48302000, .pa_start = 0x48302000,
.pa_end = 0x48302000 + SZ_16 - 1, .pa_end = 0x48302000 + SZ_16 - 1,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_epwmss1_hwmod,
.clk = "l4ls_gclk",
.addr = am33xx_epwmss1_addr_space,
.user = OCP_USER_MPU,
};
static struct omap_hwmod_addr_space am33xx_ecap1_addr_space[] = {
{ {
.pa_start = 0x48302100, .pa_start = 0x48302100,
.pa_end = 0x48302100 + SZ_256 - 1, .pa_end = 0x48302100 + SZ_128 - 1,
.flags = ADDR_TYPE_RT
}, },
{ } { }
}; };
static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap1 = { static struct omap_hwmod_ocp_if am33xx_epwmss1__ecap1 = {
.master = &am33xx_l4_ls_hwmod, .master = &am33xx_epwmss1_hwmod,
.slave = &am33xx_ecap1_hwmod, .slave = &am33xx_ecap1_hwmod,
.clk = "l4ls_gclk", .clk = "l4ls_gclk",
.addr = am33xx_ecap1_addr_space, .addr = am33xx_ecap1_addr_space,
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
/* static struct omap_hwmod_addr_space am33xx_eqep1_addr_space[] = {
* Splitting the resources to handle access of PWMSS config space {
* and module specific part independently .pa_start = 0x48302180,
*/ .pa_end = 0x48302180 + SZ_128 - 1,
static struct omap_hwmod_addr_space am33xx_ecap2_addr_space[] = { },
{ }
};
static struct omap_hwmod_ocp_if am33xx_epwmss1__eqep1 = {
.master = &am33xx_epwmss1_hwmod,
.slave = &am33xx_eqep1_hwmod,
.clk = "l4ls_gclk",
.addr = am33xx_eqep1_addr_space,
.user = OCP_USER_MPU,
};
static struct omap_hwmod_addr_space am33xx_ehrpwm1_addr_space[] = {
{
.pa_start = 0x48302200,
.pa_end = 0x48302200 + SZ_128 - 1,
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_epwmss1__ehrpwm1 = {
.master = &am33xx_epwmss1_hwmod,
.slave = &am33xx_ehrpwm1_hwmod,
.clk = "l4ls_gclk",
.addr = am33xx_ehrpwm1_addr_space,
.user = OCP_USER_MPU,
};
static struct omap_hwmod_addr_space am33xx_epwmss2_addr_space[] = {
{ {
.pa_start = 0x48304000, .pa_start = 0x48304000,
.pa_end = 0x48304000 + SZ_16 - 1, .pa_end = 0x48304000 + SZ_16 - 1,
.flags = ADDR_TYPE_RT .flags = ADDR_TYPE_RT
}, },
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_epwmss2_hwmod,
.clk = "l4ls_gclk",
.addr = am33xx_epwmss2_addr_space,
.user = OCP_USER_MPU,
};
static struct omap_hwmod_addr_space am33xx_ecap2_addr_space[] = {
{ {
.pa_start = 0x48304100, .pa_start = 0x48304100,
.pa_end = 0x48304100 + SZ_256 - 1, .pa_end = 0x48304100 + SZ_128 - 1,
.flags = ADDR_TYPE_RT
}, },
{ } { }
}; };
static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap2 = { static struct omap_hwmod_ocp_if am33xx_epwmss2__ecap2 = {
.master = &am33xx_l4_ls_hwmod, .master = &am33xx_epwmss2_hwmod,
.slave = &am33xx_ecap2_hwmod, .slave = &am33xx_ecap2_hwmod,
.clk = "l4ls_gclk", .clk = "l4ls_gclk",
.addr = am33xx_ecap2_addr_space, .addr = am33xx_ecap2_addr_space,
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
static struct omap_hwmod_addr_space am33xx_eqep2_addr_space[] = {
{
.pa_start = 0x48304180,
.pa_end = 0x48304180 + SZ_128 - 1,
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_epwmss2__eqep2 = {
.master = &am33xx_epwmss2_hwmod,
.slave = &am33xx_eqep2_hwmod,
.clk = "l4ls_gclk",
.addr = am33xx_eqep2_addr_space,
.user = OCP_USER_MPU,
};
static struct omap_hwmod_addr_space am33xx_ehrpwm2_addr_space[] = {
{
.pa_start = 0x48304200,
.pa_end = 0x48304200 + SZ_128 - 1,
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_epwmss2__ehrpwm2 = {
.master = &am33xx_epwmss2_hwmod,
.slave = &am33xx_ehrpwm2_hwmod,
.clk = "l4ls_gclk",
.addr = am33xx_ehrpwm2_addr_space,
.user = OCP_USER_MPU,
};
/* l3s cfg -> gpmc */ /* l3s cfg -> gpmc */
static struct omap_hwmod_addr_space am33xx_gpmc_addr_space[] = { static struct omap_hwmod_addr_space am33xx_gpmc_addr_space[] = {
{ {
@ -3328,6 +3427,13 @@ static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = {
.flags = OCPIF_SWSUP_IDLE, .flags = OCPIF_SWSUP_IDLE,
}; };
/* l3 main -> ocmc */
static struct omap_hwmod_ocp_if am33xx_l3_main__ocmc = {
.master = &am33xx_l3_main_hwmod,
.slave = &am33xx_ocmcram_hwmod,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = { static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
&am33xx_l4_fw__emif_fw, &am33xx_l4_fw__emif_fw,
&am33xx_l3_main__emif, &am33xx_l3_main__emif,
@ -3385,12 +3491,18 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
&am33xx_l4_ls__uart6, &am33xx_l4_ls__uart6,
&am33xx_l4_ls__spinlock, &am33xx_l4_ls__spinlock,
&am33xx_l4_ls__elm, &am33xx_l4_ls__elm,
&am33xx_l4_ls__ehrpwm0, &am33xx_l4_ls__epwmss0,
&am33xx_l4_ls__ehrpwm1, &am33xx_epwmss0__ecap0,
&am33xx_l4_ls__ehrpwm2, &am33xx_epwmss0__eqep0,
&am33xx_l4_ls__ecap0, &am33xx_epwmss0__ehrpwm0,
&am33xx_l4_ls__ecap1, &am33xx_l4_ls__epwmss1,
&am33xx_l4_ls__ecap2, &am33xx_epwmss1__ecap1,
&am33xx_epwmss1__eqep1,
&am33xx_epwmss1__ehrpwm1,
&am33xx_l4_ls__epwmss2,
&am33xx_epwmss2__ecap2,
&am33xx_epwmss2__eqep2,
&am33xx_epwmss2__ehrpwm2,
&am33xx_l3_s__gpmc, &am33xx_l3_s__gpmc,
&am33xx_l3_main__lcdc, &am33xx_l3_main__lcdc,
&am33xx_l4_ls__mcspi0, &am33xx_l4_ls__mcspi0,
@ -3398,6 +3510,7 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
&am33xx_l3_main__tptc0, &am33xx_l3_main__tptc0,
&am33xx_l3_main__tptc1, &am33xx_l3_main__tptc1,
&am33xx_l3_main__tptc2, &am33xx_l3_main__tptc2,
&am33xx_l3_main__ocmc,
&am33xx_l3_s__usbss, &am33xx_l3_s__usbss,
&am33xx_l4_hs__cpgmac0, &am33xx_l4_hs__cpgmac0,
&am33xx_cpgmac0__mdio, &am33xx_cpgmac0__mdio,

15
arch/arm/mach-omap2/prm33xx.c
View File

@ -110,11 +110,11 @@ int am33xx_prm_assert_hardreset(u8 shift, s16 inst, u16 rstctrl_offs)
* -EINVAL upon an argument error, -EEXIST if the submodule was already out * -EINVAL upon an argument error, -EEXIST if the submodule was already out
* of reset, or -EBUSY if the submodule did not exit reset promptly. * of reset, or -EBUSY if the submodule did not exit reset promptly.
*/ */
int am33xx_prm_deassert_hardreset(u8 shift, s16 inst, int am33xx_prm_deassert_hardreset(u8 shift, u8 st_shift, s16 inst,
u16 rstctrl_offs, u16 rstst_offs) u16 rstctrl_offs, u16 rstst_offs)
{ {
int c; int c;
u32 mask = 1 << shift; u32 mask = 1 << st_shift;
/* Check the current status to avoid de-asserting the line twice */ /* Check the current status to avoid de-asserting the line twice */
if (am33xx_prm_is_hardreset_asserted(shift, inst, rstctrl_offs) == 0) if (am33xx_prm_is_hardreset_asserted(shift, inst, rstctrl_offs) == 0)
@ -122,11 +122,14 @@ int am33xx_prm_deassert_hardreset(u8 shift, s16 inst,
/* Clear the reset status by writing 1 to the status bit */ /* Clear the reset status by writing 1 to the status bit */
am33xx_prm_rmw_reg_bits(0xffffffff, mask, inst, rstst_offs); am33xx_prm_rmw_reg_bits(0xffffffff, mask, inst, rstst_offs);
/* de-assert the reset control line */
am33xx_prm_rmw_reg_bits(mask, 0, inst, rstctrl_offs);
/* wait the status to be set */
omap_test_timeout(am33xx_prm_is_hardreset_asserted(shift, inst, /* de-assert the reset control line */
mask = 1 << shift;
am33xx_prm_rmw_reg_bits(mask, 0, inst, rstctrl_offs);
/* wait the status to be set */
omap_test_timeout(am33xx_prm_is_hardreset_asserted(st_shift, inst,
rstst_offs), rstst_offs),
MAX_MODULE_HARDRESET_WAIT, c); MAX_MODULE_HARDRESET_WAIT, c);

4
arch/arm/mach-omap2/prm33xx.h
View File

@ -117,6 +117,7 @@
#define AM33XX_PM_CEFUSE_PWRSTST_OFFSET 0x0004 #define AM33XX_PM_CEFUSE_PWRSTST_OFFSET 0x0004
#define AM33XX_PM_CEFUSE_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_CEFUSE_MOD, 0x0004) #define AM33XX_PM_CEFUSE_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_CEFUSE_MOD, 0x0004)
#ifndef __ASSEMBLER__
extern u32 am33xx_prm_read_reg(s16 inst, u16 idx); extern u32 am33xx_prm_read_reg(s16 inst, u16 idx);
extern void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx); extern void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx);
extern u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx); extern u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
@ -124,6 +125,7 @@ extern void am33xx_prm_global_warm_sw_reset(void);
extern int am33xx_prm_is_hardreset_asserted(u8 shift, s16 inst, extern int am33xx_prm_is_hardreset_asserted(u8 shift, s16 inst,
u16 rstctrl_offs); u16 rstctrl_offs);
extern int am33xx_prm_assert_hardreset(u8 shift, s16 inst, u16 rstctrl_offs); extern int am33xx_prm_assert_hardreset(u8 shift, s16 inst, u16 rstctrl_offs);
extern int am33xx_prm_deassert_hardreset(u8 shift, s16 inst, extern int am33xx_prm_deassert_hardreset(u8 shift, u8 st_shift, s16 inst,
u16 rstctrl_offs, u16 rstst_offs); u16 rstctrl_offs, u16 rstst_offs);
#endif /* ASSEMBLER */
#endif #endif