- Support for the Audio PLL and child clocks
- Support for the A33 AHB gates
- New clk-multiplier generic driver
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Merge tag 'sunxi-clocks-for-4.4' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next
Pull Allwinner clock additions for 4.4 from Maxime Ripard:
- Support for the Audio PLL and child clocks
- Support for the A33 AHB gates
- New clk-multiplier generic driver
* tag 'sunxi-clocks-for-4.4' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux:
clk: sunxi: mod1 clock support
clk: sunxi: codec clock support
clk: sunxi: pll2: Add A13 support
clk: sunxi: Add a driver for the PLL2
clk: Add a basic multiplier clock
clk: sunxi: Add A33 gates support
for_each_compatible_node performs an of_node_get on each iteration, so a
break out of the loop requires an of_node_put.
The semantic patch that fixes this problem is as follows
(http://coccinelle.lip6.fr):
// <smpl>
@@
local idexpression n;
expression e;
@@
for_each_compatible_node(n,...) {
...
(
of_node_put(n);
|
e = n
|
+ of_node_put(n);
? break;
)
...
}
... when != n
// </smpl>
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
for_each_compatible_node performs an of_node_get on each iteration, so a
break out of the loop requires an of_node_put.
The semantic patch that fixes this problem is as follows
(http://coccinelle.lip6.fr):
// <smpl>
@@
local idexpression n;
expression e;
@@
for_each_compatible_node(n,...) {
...
(
of_node_put(n);
|
e = n
|
+ of_node_put(n);
? break;
)
...
}
... when != n
// </smpl>
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
for_each_child_of_node performs an of_node_get on each iteration, so
a break out of the loop requires an of_node_put.
A simplified version of the semantic patch that fixes this problem is as
follows (http://coccinelle.lip6.fr):
// <smpl>
@@
expression root,e;
local idexpression child;
@@
for_each_child_of_node(root, child) {
... when != of_node_put(child)
when != e = child
(
return child;
|
+ of_node_put(child);
? return ...;
)
...
}
// </smpl>
The resulting puts were manually moved to the end of the function for
conciseness.
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
for_each_matching_node_and_match performs an of_node_get on each iteration,
so a break out of the loop requires an of_node_put.
A simplified version of the semantic patch that fixes this problem is as
follows (http://coccinelle.lip6.fr):
// <smpl>
@@
expression e1,e2,e;
local idexpression np;
@@
for_each_matching_node_and_match(np, e1, e2) {
... when != of_node_put(np)
when != e = np
(
return np;
|
+ of_node_put(np);
? return ...;
)
...
}
// </smpl>
Besides the problem identified by the semantic patch, this patch adds an
of_node_get in front of saving np in a field of parent, to account for the
fact that this value will be put on going on to the next element in the
iteration, and then adds of_node_puts in the two loops where the parent
pointer can be freed.
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
LS2080A is the first implementation of the chassis 3 clockgen, which
has a different register layout than previous chips. It is also little
endian, unlike previous chips.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
The device tree should describe the chips (or chip-like subblocks) in
the system, but it generally does not describe individual registers --
it should identify, rather than describe, a programming interface.
This has not been the case with the QorIQ clockgen nodes. The
knowledge of what each bit setting of CLKCnCSR means is encoded in
three places (binding, pll node, and mux node), and the last also needs
to know which options are valid on a particular chip. All three of
these locations are considered stable ABI, making it difficult to fix
mistakes (of which I have found several), much less refactor the
abstraction to be able to address problems, limitations, or new chips.
Under the current binding, a pll clock specifier of 2 means that the
PLL is divided by 4 -- and the driver implements this, unless there
happen to be four clock-output-names rather than 3, in which case it
interprets it as PLL divided by 3. This does not appear in the binding
documentation at all. That hack is now considered stable ABI.
The current device tree nodes contain errors, such as saying that
T1040 can set a core clock to PLL/4 when only PLL and PLL/2 are options.
The current binding also ignores some restrictions on clock selection,
such as p5020's requirement that if a core uses the "wrong" PLL, that
PLL must be clocked lower than the "correct" PLL and be at most 80% of
the rated CPU frequency.
Possibly because of the lack of the ability to express such nuance in
the binding, some valid options are omitted from the device trees, such
as the ability on p4080 to run cores 0-3 from PLL3 and cores 4-7 from
PLL1 (again, only if they are at most 80% of rated CPU frequency).
This omission, combined with excessive caution in the cpufreq driver
(addressed in a subsequent patch), means that currently on a 1500 MHz
p4080 with typical PLL configuration, cpufreq can lower the frequency
to 1200 MHz on half the CPUs and do nothing on the others. With this
patchset, all CPUs can be lowered to 1200 MHz on a rev2 p4080, and on a
rev3 p4080 half can be lowered to 750 MHz and the other half to 600
MHz.
The current binding only deals with CPU clocks. To describe FMan in
the device tree, we need to describe its clock. Some chips have
additional muxes that work like the CPU muxes, but are not described in
the device tree. Others require inspecting the Reset Control Word to
determine which PLL is used. Rather than continue to extend this mess,
replace it. Have the driver bind to the chip-specific clockgen
compatible, and keep the detailed description of quirky chip variations
in the driver, where it can be easily fixed, refactored, and extended.
Older device trees will continue to work (including a workaround for
old ls1021a device trees that are missing compatible and reg in the
clockgen node, which even the old binding required). The pll/mux
details in old device trees will be ignored, but "clocks" properties
pointing at the old nodes will still work, and be directed at the
corresponding new clock.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
The module 1 type of clocks consist of a gate and a mux and are used on
the audio blocks to mux and gate the PLL2 outputs for AC97, IIS or
SPDIF. This commit adds support for them on the sunxi clock driver.
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
The codec clock on sun4i, sun5i and sun7i is a simple gate with PLL2 as
parent. Add a driver for such a clock.
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
The A13, unlike the A10 and A20, doesn't use a pass-through exception for
the 0 value in the pre and post dividers, but increments all the values
written in the register by one.
Add an exception for both these cases to handle them nicely.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
The PLL2 on the A10 and later SoCs is the clock used for all the audio
related operations.
This clock has a somewhat complex output tree, with three outputs (2X, 4X
and 8X) with a fixed divider from the base clock, and an output (1X) with a
post divider.
However, we can simplify things since the 1X divider can be fixed, and we
end up by having a base clock not exposed to any device (or at least
directly, since the 4X output doesn't have any divider), and 4 fixed
divider clocks that will be exposed.
This clock seems to have been introduced, at least in this form, in the
revision B of the A10, but we don't have any information on the clock used
on the revision A.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Some clocks are using a multiplier component, however, unlike their mux,
gate or divider counterpart, these factors don't have a basic clock
implementation.
This leads to code duplication across platforms that want to use that kind
of clocks, and the impossibility to use the composite clocks with such a
clock without defining your own rate operations.
Create such a driver in order to remove these issues, and hopefully factor
the implementations, reducing code size across platforms and consolidating
the various implementations.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
This patch affects the clocks that use fractional ndivider in their
PLL output frequency calculation. Instead of 2^20 divide factor, the
clock's ndiv integer shift was used. Fixed the bug by replacing ndiv
integer shift with 2^20 factor.
Signed-off-by: Simran Rai <ssimran@broadcom.com>
Signed-off-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Scott Branden <sbranden@broadcom.com>
Fixes: 5fe225c105 ("clk: iproc: add initial common clock support")
Cc: <stable@vger.kernel.org> # v4.1+
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
The clocks' properties have been already properly set, so there's no
need to set this flag for sdio0 and sdio1 clk any more.
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Since we have added the necessary two clks' properties in dts, we can
remove the "sdio" clk's CLK_IGNORE_UNUSED flag now.
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
clk_add_alias() was not correctly handling the case where alias_dev_name
was NULL: rather than producing an entry with a NULL dev_id pointer,
it would produce a device name of (null). Fix this.
Cc: <stable@vger.kernel.org>
Fixes: 2568999835 ("clkdev: add clkdev_create() helper")
Reported-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Tested-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This contains a patch that allows the DFLL to use clock rates higher
than 2^31-1 Hz by using the ->determine_rate() operation instead of the
->round_rate() operation. Other than that there's a couple of cleanups
in preparation for Tegra210 support.
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Merge tag 'tegra-for-4.4-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-next
clk: tegra: Changes for v4.4-rc1
This contains a patch that allows the DFLL to use clock rates higher
than 2^31-1 Hz by using the ->determine_rate() operation instead of the
->round_rate() operation. Other than that there's a couple of cleanups
in preparation for Tegra210 support.
tegra_audio_clk_init was written expecting a single PLL to be
passed in directly. Change this to accept an array which will
allow for supporting multiple plls and specifying specific data
about them, like their parent, which may change over time.
Reviewed-by: Benson Leung <bleung@chromium.org>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Benson Leung pointed out that the kerneldoc for this structure has
become stale. Update the field descriptions to match the structure
content.
Reported-by: Benson Leung <bleung@chromium.org>
Acked-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Benson Leung <bleung@chromium.org>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Some fields moved from the tegra_clk_pll struct to the tegra_pll_params
struct. Update the struct comments to reflect where the fields really
are.
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: Benson Leung <bleung@chromium.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The monitor code is used with DEBUG_FS only, so move it into the
corresponding #ifdef block to avoid potential compiler warnings.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The R8 is a new Allwinner SoC based on the A13. While both are very
similar, there's still a few differences. Introduce a new compatible to
deal with them.
In order to have a consistent naming, instead of mentioning the Allwinner
A series as the machine name, switch to sun4i/sun5i like what is done for
the other families.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
This reverts commit e79b202c63.
Now that we use of_clk_get() inside of_clk_get_parent_name() we
can safely use it here.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add rcg and branch clk structs for DSI1 and DSI2 blocks found in MSM8960
and APQ8064. Each DSI instance has 4 pairs of rcg and branch clocks.
Populate arrays mmcc_msm8960_clks and mmcc_apq8064_clks with these clocks.
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
DSI specific RCG clocks required customized clk_ops. There are
a total of 4 RCGs per DSI block: DSI, BYTE, ESC and PIXEL.
There are a total of 2 clocks coming from the DSI PLL, which serve as
inputs to these RCGs. The BYTE and ESC RCGs are fed by one of the
post dividers of DSI1 or DSI2 PLLs, and the DSI and PIXEL RCGs are fed by
another divider of the PLL.
In each of the 2 groups above, only one of the clocks sets its parent.
These are BYTE RCG and DSI RCG for each of the groups respectively, as
shown in the diagram below.
The DSI and BYTE RCGs serve as bypass clocks. We create a new set of ops
clk_rcg_bypass2_ops, which are like the regular bypass ops, but don't
take in a freq table, since the DSI driver using these clocks is
parent-able.
The PIXEL RCG needs to derive the required pixel clock using dsixpll.
It parses a m/n frac table to retrieve the correct clock.
The ESC RCG doesn't have a frac M/N block, it can just apply a pre-
divider. Its ops simply check if the required clock rate can be
achieved by the pre-divider.
+-------------------+
| |---dsixpllbyte---o---> To byte RCG
| | | (sets parent rate)
| | |
| | |
| DSI 1/2 PLL | |
| | o---> To esc RCG
| | (doesn't set parent rate)
| |
| |----dsixpll-----o---> To dsi RCG
+-------------------+ | (sets parent rate)
( x = 1, 2 ) |
|
o---> To pixel rcg
(doesn't set parent rate)
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
These drivers only have runtime but no build time dependencies so can be
built for testing purposes if the Kconfig COMPILE_TEST option is enabled.
This is useful to have more build coverage and make sure that drivers are
not affected by changes that could cause build regressions.
Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
Acked-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
When calling __clk_get_name() on a const clock:
warning: passing argument 1 of '__clk_get_name' discards 'const' qualifier from pointer target type
include/linux/clk-provider.h:613:13: note: expected 'struct clk *' but argument is of type 'const struct clk *'
__clk_get_name() does not modify the passed clock, hence make it const.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
r8a7778_rates[] and r8a7778_divs[] are only used in clk-r8a7778.c, and
never modified.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
- A couple of fixes on i.MX31 and i.MX35 clock initialization functions
which makes mxc_timer_init() currently be called twice for DT boot.
- Increase i.MX6UL AXI bus clock rate to 264MHz which is the optimal
design target.
- Add a few missing clocks, ADC clock for i.MX7D, OCOTP clock for
Vybrid, and SPDIF_GCLK for i.MX6.
- A series from Lucas to fix early debug UART clock setup. This is
currently a one-off fix for i.MX platform, and can be extended to
become a generic solution later.
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Merge tag 'imx-clk-4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-next
Pull i.MX updates from Shawn Guo:
"The i.MX clock updates for 4.4:
- A couple of fixes on i.MX31 and i.MX35 clock initialization functions
which makes mxc_timer_init() currently be called twice for DT boot.
- Increase i.MX6UL AXI bus clock rate to 264MHz which is the optimal
design target.
- Add a few missing clocks, ADC clock for i.MX7D, OCOTP clock for
Vybrid, and SPDIF_GCLK for i.MX6.
- A series from Lucas to fix early debug UART clock setup. This is
currently a one-off fix for i.MX platform, and can be extended to
become a generic solution later."
* tag 'imx-clk-4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
clk: imx6: Add SPDIF_GCLK clock in clock tree
clk: imx7d: add ADC root clock
clk: imx31: Do not call mxc_timer_init twice when booting with DT
clk: imx7d: retain early UART clocks during kernel init
clk: imx6: retain early UART clocks during kernel init
clk: imx5: retain early UART clocks during kernel init
clk: imx35: retain early UART clocks during kernel init
clk: imx31: retain early UART clocks during kernel init
clk: imx27: retain early UART clocks during kernel init
clk: imx25: retain early UART clocks during kernel init
clk: imx: add common logic to detect early UART usage
clk: imx35: Do not call mxc_timer_init twice when booting with DT
clk: clk-vf610: Add clock for Vybrid OCOTP controller
clk: imx: increase AXI clock rate to 264MHz for i.MX6UL
If a clock provider has #clock-cells = 1 and we call
of_clk_get_parent_name() on it we may end up returning the name
of the provider node if the provider doesn't have a
clock-output-names property. This doesn't make sense, especially
when you consider that calling of_clk_get_parent_name() on such a
node with different indices will return the same name each time.
Let's try getting the clock from the framework via of_clk_get()
instead, and only fallback to the node name if we have a provider
with #clock-cells = 0. This way, we can't hand out the same name
for different clocks when we don't actually know their names.
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add cpuclk in the Berlin BG2Q clock driver. This clk has a divider
fixed to 1.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
The email address listed in MODULE_AUTHOR() no longer exist so to prevent
people to send emails to the old address, replace it with my current one.
Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This partially reverts commit eca61c9ff2.
Thomas reports that it causes regressions on Armada XP devices.
This is because of_clk_get_parent_name() relies on the property
'clock-output-names' to resolve the name of a clock's parent,
without trying to get the clock from the framework and call
__clk_get_name(). Given that Armada XP devices don't have the
'clock-output-names' property, of_clk_get_parent_name() returns
the name of the node which doesn't match the actual parent
clock's name at all, causing CPU clocks to never link up with
their parents.
Reported-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
It adds support for the following features provided by SCP firmware
using different subsystems in Linux:
1. SCPI mailbox protocol driver which using mailbox framework
2. Clocks provided by SCP using clock framework
3. CPU DVFS(cpufreq) using existing arm-big-little driver
4. SCPI based sensors including temperature sensors
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Merge tag 'arm-scpi-for-v4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into next/drivers
Merge "ARM System Control and Power Interface(SCPI) support" from Sudeep Holla
It adds support for the following features provided by SCP firmware
using different subsystems in Linux:
1. SCPI mailbox protocol driver which using mailbox framework
2. Clocks provided by SCP using clock framework
3. CPU DVFS(cpufreq) using existing arm-big-little driver
4. SCPI based sensors including temperature sensors
* tag 'arm-scpi-for-v4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
hwmon: Support thermal zones registration for SCP temperature sensors
hwmon: Support sensors exported via ARM SCP interface
firmware: arm_scpi: Extend to support sensors
Documentation: add DT bindings for ARM SCPI sensors
cpufreq: arm_big_little: add SCPI interface driver
clk: scpi: add support for cpufreq virtual device
clk: add support for clocks provided by SCP(System Control Processor)
firmware: add support for ARM System Control and Power Interface(SCPI) protocol
Documentation: add DT binding for ARM System Control and Power Interface(SCPI) protocol
for_each_child_of_node performs an of_node_put on each iteration, so
putting an of_node_put before a continue results in a double put.
The semantic match that finds this problem is as follows
(http://coccinelle.lip6.fr):
// <smpl>
@@
expression root,e;
local idexpression child;
iterator name for_each_child_of_node;
@@
for_each_child_of_node(root, child) {
... when != of_node_get(child)
* of_node_put(child);
...
* continue;
}
// </smpl>
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk-bcm2835:
clk: bcm2835: Add support for programming the audio domain clocks
clk: bcm2835: Add binding docs for the new platform clock driver.
clk: bcm2835: Move under bcm/ with other Broadcom SoC clk drivers.
This adds support for enabling, disabling, and setting the rate of the
audio domain clocks. It will be necessary for setting the pixel clock
for HDMI in the VC4 driver and let us write a cpufreq driver. It will
also improve compatibility with user changes to the firmware's
config.txt, since our previous fixed clocks are unaware of it.
The firmware also has support for configuring the clocks through the
mailbox channel, but the pixel clock setup by the firmware doesn't
work, and it's Raspberry Pi specific anyway. The only conflicts we
should have with the firmware would be if we made firmware calls that
result in clock management (like opening firmware V3D or ISP access,
which we don't support in upstream), or on hardware over-thermal or
under-voltage (when the firmware would rewrite PLLB to take the ARM
out of overclock). If that happens, our cached .recalc_rate() results
would be incorrect, but that's no worse than our current state where
we used fixed clocks.
The existing fixed clocks in the code are left in place to provide
backwards compatibility with old device tree files.
Signed-off-by: Eric Anholt <eric@anholt.net>
Tested-by: Martin Sperl <kernel@martin.sperl.org>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Correct SPDIF clock setting issue in clock tree, the SPDIF_GCLK is also
one clock of SPDIF, which is missed before.
We found an issue that imx can't enter low power mode with spdif
if IMX6x_CLK_SPDIF is used as the core clock of spdif. Because
spdif driver will register IMX6x_CLK_SPDIF clock to regmap, regmap will do
clk_prepare in init function, then IMX6x_CLK_SPDIF clock is prepared in probe,
so its parent clock (PLL clock) is prepared, the prepare operation of
PLL clock is to enable the clock. But I.MX needs all PLL clock is disabled,
then it can enter low power mode.
So we can't use IMX6x_CLK_SPDIF as the core clock of spdif, the correct spdif
core clock is SPDIF_GCLK, which share same gate bit with IMX6x_CLK_SPDIF clock.
SPDIF_GCLK's parent clock is ipg clock.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
8960 family of devices have TSENS as part of GCC in hardware.
Hence DT would represent a GCC node with GCC properties as well
as TSENS. Create a virtual platform child device here for TSENS
so the driver can probe it and use the parent (GCC) to extract DT
properties.
Suggested-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
[sboyd@codeaurora.org: Massaged to work with devm friendly
qcom_cc_probe()]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Having this hidden config below the COMMON_CLK_QCOM config causes
menuconfig to stop indenting config items after it.
<*> Support for Qualcomm's clock controllers
{M} APQ8084 Global Clock Controller
<M> APQ8084 Multimedia Clock Controller
{M} IPQ806x Global Clock Controller
<M> IPQ806x LPASS Clock Controller
<M> MSM8660 Global Clock Controller
<M> MSM8916 Global Clock Controller
{M} APQ8064/MSM8960 Global Clock Controller
<M> APQ8064/MSM8960 LPASS Clock Controller
<M> MSM8960 Multimedia Clock Controller
{M} MSM8974 Global Clock Controller
<M> MSM8974 Multimedia Clock Controller
Move it up above anything else so that we don't get odd
indenting.
Cc: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Now that qcom_cc_remove() is a nop, drop calls to
qcom_cc_remove() and any empty driver remove functions.
Cc: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Some APIs in qcom_cc_probe() don't have a devm counterpart, so we
have to use the calling device's platform data to pass pointers
to the remove path. Let's use devm_add_action() instead, so that
the remove path doesn't need to do anything, allowing us to
remove qcom_cc_remove() entirely.
Cc: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add support for new PLL-type for stih418 A9-PLL.
Currently the 407_A9_PLL type being used, it is corrected with this patch
4600c28 PLL allows to reach higher frequencies
so its programming algorithm is extended.
Signed-off-by: Pankaj Dev <pankaj.dev@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Change A9 PLL rate, as per requirement from the cpufreq framework,
for DVFS. For rate change, the A9 clock needs to be temporarily sourced
from PLL external to A9 and then sourced back to A9-PLL
Signed-off-by: Pankaj Dev <pankaj.dev@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The patch adds support for enable/disable of the Clockgen PLLs.
clkgen_pll_enable/clkgen_pll_disable added as generic function for all PLLs.
Signed-off-by: Pankaj Dev <pankaj.dev@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The oxili_cx GDSC is inside the power domain of the oxili GDSC.
Add the dependency so that the CX domain can properly power up.
Reported-by: Rob Clark <robdclark@gmail.com>
Cc: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This patch adds the driver and devicetree documentation for the
Silicon Labs SI514 clock generator chip. This is an I2C controlled
oscillator capable of generating clock signals ranging from 100kHz
to 250MHz.
Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
[sboyd@codeaurora.org: Drop clk.h include, remove some casts]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* Consider "zb_clk" suitable for power management
This part of a multi-stage effort by Geert Uytterhoeven to add:
"Clock Domain support to the Clock Pulse Generator (CPG) Module Stop
(MSTP) Clocks driver using the generic PM Domain, to be used on shmobile
SoCs without device power domains (R-Car Gen1 and Gen2, RZ). This allows
to power-manage the module clocks of SoC devices that are part of the
CPG/MSTP Clock Domain using Runtime PM, or for system suspend/resume,
similar to SoCs with device power domains (SH-Mobile and R-Mobile)."
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Merge tag 'renesas-clk-for-v4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/drivers
Merge "Renesas ARM Based SoC Clk Updates for v4.4" from Simon Horman:
* Consider "zb_clk" suitable for power management
This part of a multi-stage effort by Geert Uytterhoeven to add:
"Clock Domain support to the Clock Pulse Generator (CPG) Module Stop
(MSTP) Clocks driver using the generic PM Domain, to be used on shmobile
SoCs without device power domains (R-Car Gen1 and Gen2, RZ). This allows
to power-manage the module clocks of SoC devices that are part of the
CPG/MSTP Clock Domain using Runtime PM, or for system suspend/resume,
similar to SoCs with device power domains (SH-Mobile and R-Mobile)."
* tag 'renesas-clk-for-v4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
clk: shmobile: mstp: Consider "zb_clk" suitable for power management
* ARM: shmobile: R-Mobile: Use CPG/MSTP Clock Domain attach/detach helpers
This part of a multi-stage effort by Geert Uytterhoeven to add:
"Clock Domain support to the Clock Pulse Generator (CPG) Module Stop
(MSTP) Clocks driver using the generic PM Domain, to be used on shmobile
SoCs without device power domains (R-Car Gen1 and Gen2, RZ). This allows
to power-manage the module clocks of SoC devices that are part of the
CPG/MSTP Clock Domain using Runtime PM, or for system suspend/resume,
similar to SoCs with device power domains (SH-Mobile and R-Mobile)."
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Merge tag 'renesas-soc-for-v4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc
Merge "Renesas ARM Based SoC Updates for v4.4" from Simon Horman:
* ARM: shmobile: R-Mobile: Use CPG/MSTP Clock Domain attach/detach helpers
This part of a multi-stage effort by Geert Uytterhoeven to add:
"Clock Domain support to the Clock Pulse Generator (CPG) Module Stop
(MSTP) Clocks driver using the generic PM Domain, to be used on shmobile
SoCs without device power domains (R-Car Gen1 and Gen2, RZ). This allows
to power-manage the module clocks of SoC devices that are part of the
CPG/MSTP Clock Domain using Runtime PM, or for system suspend/resume,
similar to SoCs with device power domains (SH-Mobile and R-Mobile)."
* tag 'renesas-soc-for-v4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: R-Mobile: Use CPG/MSTP Clock Domain attach/detach helpers
clk: shmobile: mstp: Consider "zb_clk" suitable for power management
Pull mediatek clock support and fixes from James Liao:
"This is a collection of new Mediatek clocks support and fixes.
These patches come from Joe and me, including clock support for
subsystems, GPT and some minor fixes."
* 'v4.3-rc3-clk' of https://github.com/jamesjjliao/linux:
clk: mediatek: Add USB clock support in MT8173 APMIXEDSYS
clk: mediatek: Add subsystem clocks of MT8173
dt-bindings: ARM: Mediatek: Document devicetree bindings for clock controllers
clk: mediatek: Fix rate and dependency of MT8173 clocks
clk: mediatek: Add fixed clocks support for Mediatek SoC.
clk: mediatek: Add __initdata and __init for data and functions
clk: mediatek: Remove unused code from MT8173.
clk: mediatek: Removed unused dpi_ck clock from MT8173
clk: mediatek: add 13mhz clock for MT8173
drivers/clk/samsung/clk-exynos7.c:896:33:
warning: symbol 'fixed_rate_clks_fsys0' was not declared. Should
it be static?
drivers/clk/samsung/clk-exynos7.c:1010:33:
warning: symbol 'fixed_rate_clks_fsys1' was not declared. Should
it be static?
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This patch converts the code to use rational best approximation algorithm which
is much more precise.
Suggested-by: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The ->mwidth and ->nwidth fields will be used by clk-fractional-divider when it
will be switched to rational base approximation algorithm.
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The patch adds mwidth and nwidth fields to the struct clk_fractional_divider
for further usage. While here, use GENMASK() instead of open coding this
functionality.
Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Rename function parameter to be more explicit what it is for. This also makes
it in align with struct clk_ops.
There is no functional change.
Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The default clock enabling functions for TI clocks -
omap2_dflt_clk_enable() and omap2_dflt_clk_disable() perform a
NULL check for the enable_reg field of the clk_hw_omap structure.
This enable_reg field however is merely a combination of the index
of the master IP module, and the offset from the master IP module's
base address. A value of 0 is perfectly valid, and the current error
checking will fail in these cases. The issue was found when trying
to enable the iva2_ck clock on OMAP3 platforms.
So, switch the check to use IS_ERR. This correction is similar to the
logic used in commit c807dbedb5 ("clk: ti: fix ti_clk_get_reg_addr
error handling").
Fixes: 9f37e90efa ("clk: ti: dflt: move support for default gate clock..")
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
On the OMAP AM3517 platform the uart4_ick gets registered
twice, causing any power management to /dev/ttyO3 to fail
when trying to wake the device up.
This solves the following oops:
[] Unhandled fault: external abort on non-linefetch (0x1028) at 0xfa09e008
[] PC is at serial_omap_pm+0x48/0x15c
[] LR is at _raw_spin_unlock_irqrestore+0x30/0x5c
Fixes: aafd900cab ("CLK: TI: add omap3 clock init file")
Cc: stable@vger.kernel.org
Cc: mturquette@baylibre.com
Cc: sboyd@codeaurora.org
Cc: linux-clk@vger.kernel.org
Cc: linux-omap@vger.kernel.org
Cc: linux-kernel@lists.codethink.co.uk
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
The ABE related clocks should be configured via DT and not have it wired
inside of the kernel.
Fixes: a74c52def9 ("clk: ti: clk-7xx: Correct ABE DPLL configuration")
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
clk-bcm2835.c predates the drivers under bcm/, but all the new BCM
drivers are going in there so let's follow them.
Signed-off-by: Eric Anholt <eric@anholt.net>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This simplifies the given function by getting rid of the manual
sign extension as well as saving an absolute value in an extra
variable.
Signed-off-by: Martin Kepplinger <martink@posteo.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
mmc host controller's IO input/output timing is unpredictable if
bootloader execute tuning for HS200 mode. It might make kernel failed
to initialize mmc card in identification mode. The root cause is
tuning phase and degree setting for HS200 mode in bootloader aren't
applicable to that of identification mode in kernel stage. Anyway, we
can't force all bootloaders to reset tuning phase and degree setting
before into kernel. Simply reset it in rockchip_clk_register_mmc.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
On drivers/clk/mxs/clk-frac.c, the function clk_frac_round_rate returned a bad
result. The division before multiplication computes a wrong value ; the
calculation is inverted to fix the problem. The second issue is that the exact
rate have decimals and they are truncate. The consequence is that the function
clk_frac_set_rate (which use the result of clk_frac_round_rate) computes a
wrong value for the register (the rate generated can be closer to the desired
rate). The correction is : if there is decimal to the result, it is rounded to
the next larger integer.
On drivers/clk/mxs/clk-frac.c, the function clk_frac_recalc_rate returned
a bad result. The multiplication is made before the division to compute a
correct value.
Signed-off-by: Victorien Vedrine <victorien.vedrine@ophrys.net>
Acked-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The function can return negative value.
The problem has been detected using proposed semantic patch
scripts/coccinelle/tests/assign_signed_to_unsigned.cocci [1].
[1]: http://permalink.gmane.org/gmane.linux.kernel/2046107
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Separate the update of pll registers from the actual set_rate function
so that the init callback does not need to access clk-API functions.
As we now have separated the getting and setting of the pll parameters
we can also directly use these new functions in other places too.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add a new type of clocks that can be provided to a peripheral.
In addition to the peripheral clock, this new clock that can use several
input clocks as parents can generate divided rates.
This would allow a peripheral to have finer grained clocks for generating
a baud rate, clocking an asynchronous part or having more
options in frequency.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[sboyd@codeaurora.org: Transition to new clk_hw provider APIs]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add support for the new sama5d2 SoC and adapt capabilities.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
As some more information is added to the PCR register, we'd better use
a copy of its content and modify just the peripheral-related bits.
Implement a read-modify-write for the enable() and disable() callbacks.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add _MASK and _OFFSET values and cleanup register fields layout.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add REF2USB_TX clock support into MT8173 APMIXEDSYS. This clock
is needed by USB 3.0.
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Most multimedia subsystem clocks will be accessed by multiple
drivers, so it's a better way to manage these clocks in CCF.
This patch adds clock support for MM, IMG, VDEC, VENC and VENC_LT
subsystems.
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Remove the dependency from clk_null, and give all root clocks a
typical rate, include clkph_mck_o, usb_syspll_125m and hdmitx_dig_cts.
dpi_ck was removed due to no clock reference to it.
Replace parent clock of infra_cpum with cpum_ck, which is an external
clock and can be defined in the device tree.
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
This patch adds fixed clocks support by using CCF fixed-rate
clock implementation.
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Add __init for clock registration functions, and add __initdata for
mtk_gate_regs initial structures.
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Remove unused header files from MT8173, and remove unused
keywords from function declaration.
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
The dpi_ck clock can be removed because it not actually used
in topckgen and subsystems.
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Add 13mhz clock used by GPT timer in infracfg.
Signed-off-by: Yingjoe Chen <yingjoe.chen@mediatek.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
mxc_timer_init must not be called from within mx31_clocks_init_dt. It will
eventually be called by imx31_timer_init_dt
(drivers/clocksource/timer-imx-gpt.c).
This arranges the initialization code similar to clk-imx27.c
Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Power management on of NoC(Notwork On Chip) requires that disconnect
and reconnect routine should been done during clk disable/enable.
also there are different types of clocks,
For NoC Macro clocks, write idle_bit and wait for hardward ACK;
For Socket clocks, write idle_bit;
For others, do nothing.
Signed-off-by: Guo Zeng <Guo.Zeng@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
re-order the codes more reasonable by moving variable-definition
together.
Signed-off-by: Guo Zeng <Guo.Zeng@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
The clocks for the CPUs are provided by SCP and are managed by this
clock driver. So the cpufreq device needs to be added only after the
clock get registered and removed when this driver is unloaded.
This patch manages the cpufreq virtual device based on the clock
availability.
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Cc: Mike Turquette <mturquette@baylibre.com>
Cc: Liviu Dudau <Liviu.Dudau@arm.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Jon Medhurst (Tixy) <tixy@linaro.org>
Cc: linux-clk@vger.kernel.org
On some ARM based systems, a separate Cortex-M based System Control
Processor(SCP) provides the overall power, clock, reset and system
control. System Control and Power Interface(SCPI) Message Protocol
is defined for the communication between the Application Cores(AP)
and the SCP.
This patch adds support for the clocks provided by SCP using SCPI
protocol.
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Cc: Mike Turquette <mturquette@baylibre.com>
Cc: Liviu Dudau <Liviu.Dudau@arm.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Jon Medhurst (Tixy) <tixy@linaro.org>
Cc: linux-clk@vger.kernel.org
Make sure to keep UART clocks enabled during kernel init if
earlyprintk or earlycon are active.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Make sure to keep UART clocks enabled during kernel init if
earlyprintk or earlycon are active.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Make sure to keep UART clocks enabled during kernel init if
earlyprintk or earlycon are active.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Make sure to keep UART clocks enabled during kernel init if
earlyprintk or earlycon are active.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Make sure to keep UART clocks enabled during kernel init if
earlyprintk or earlycon are active.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Make sure to keep UART clocks enabled during kernel init if
earlyprintk or earlycon are active.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Make sure to keep UART clocks enabled during kernel init if
earlyprintk or earlycon are active.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Both earlycon and eralyprintk depend on the bootloader setup UART
clocks being retained. This patch adds the common logic to detect such
situations and make the information available to the clock drivers, as
well as adding the facilities to disable those clocks at the end of
the kernel init.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
mxc_timer_init must not be called from within mx35_clocks_init_dt. It will
eventually be called by imx31_timer_init_dt
(drivers/clocksource/timer-imx-gpt.c).
This arranges the initialization code similar to clk-imx27.c
Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
