Cliff Brake b6018958a5 pxamci: enable DMA for write ops after CMD/RESP ... With the PXA270 MMC hardware, there seems to be an issue of data corruption on writes where a 4KB data block is offset by one byte. If we delay enabling the DMA for writes until after the CMD/RESP has finished, the problem seems to be fixed. related to PXA270 Erratum #91 Tested-by: Vernon Sauder <VernonInHand@gmail.com> Signed-off-by: Cliff Brake <cbrake@bec-systems.com> Acked-by: Eric Miao <eric.miao@marvell.com> Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>		2009-02-02 20:57:07 +01:00
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at91_mci.c
atmel-mci-regs.h
atmel-mci.c
au1xmmc.c
imxmmc.c
imxmmc.h
Kconfig	mmc: Add a MX2/MX3 specific SDHC driver	2009-02-02 20:57:05 +01:00
Makefile	mmc: Add a MX2/MX3 specific SDHC driver	2009-02-02 20:57:05 +01:00
mmc_spi.c
mmci.c	mmci: Add support for ST Micro derivate	2009-02-02 20:57:06 +01:00
mmci.h	mmci: Add support for ST Micro derivate	2009-02-02 20:57:06 +01:00
mxcmmc.c	mmc: Add a MX2/MX3 specific SDHC driver	2009-02-02 20:57:05 +01:00
of_mmc_spi.c
omap_hsmmc.c	[ARM] 5369/1: omap mmc: Add new omap hsmmc controller for 2430 and 34xx, v3	2009-01-24 11:41:21 +00:00
omap.c
pxamci.c	pxamci: enable DMA for write ops after CMD/RESP	2009-02-02 20:57:07 +01:00
pxamci.h
ricoh_mmc.c	ricoh_mmc: Use suspend_late/resume_early	2009-02-02 20:57:06 +01:00
s3cmci.c
s3cmci.h
sdhci-pci.c
sdhci.c
sdhci.h
sdricoh_cs.c
tifm_sd.c
tmio_mmc.c
tmio_mmc.h
wbsd.c
wbsd.h