Thierry Reding 0f1bc12e9e clk: tegra: Allow PLLE training to succeed ...

Under some circumstances the PLLE needs to be retrained, in which case
access to the PMC registers is required. Fix this by passing a pointer
to the PMC registers instead of NULL when registering the PLLE clock.

Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

2013-04-01 11:44:38 -07:00

..

clk-audio-sync.c

…

clk-divider.c

…

clk-periph-gate.c

…

clk-periph.c

ARM: tegra: migrate to new clock code

2013-01-28 11:19:07 -07:00

clk-pll-out.c

…

clk-pll.c

…

clk-super.c

clk: tegra: Implement locking for super clock

2013-02-12 10:29:12 -07:00

clk-tegra20.c

clk: tegra: Allow PLLE training to succeed

2013-04-01 11:44:38 -07:00

clk-tegra30.c

clk: Tegra: Remove duplicate smp_twd clock

2013-03-04 17:16:37 -08:00

clk.c

ARM: tegra: migrate to new clock code

2013-01-28 11:19:07 -07:00

clk.h

clk: tegra: add clock support for Tegra30

2013-01-28 11:19:07 -07:00

Makefile

clk: tegra: add clock support for Tegra30

2013-01-28 11:19:07 -07:00