mirror of
https://github.com/n64decomp/mk64.git
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update libultra asm (#648)
* update libultra asm * fix gcc __osThreadTail --------- Co-authored-by: MegaMech <MegaMech@users.noreply.github.com>
This commit is contained in:
coco875
GitHub
parent
8733751fb5
commit
7025ff0ca1
2
Makefile
2
Makefile
@ -33,7 +33,7 @@ $(eval $(call validate-option,COMPILER,ido gcc))
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DEBUG ?= 0
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# Compile with GCC
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GCC ?= 0
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GCC ?= 1
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# VERSION - selects the version of the game to build
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# us - builds the 1997 North American version
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90
asm/boot.s
90
asm/boot.s
@ -19,8 +19,8 @@ glabel ipl3_entry # 0xA4000040
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mtc0 $zero, $13
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mtc0 $zero, $9
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mtc0 $zero, $11
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lui $t0, %hi(RI_MODE_REG)
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addiu $t0, %lo(RI_MODE_REG)
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lui $t0, %hi(PHYS_TO_K1|RI_MODE_REG)
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addiu $t0, %lo(PHYS_TO_K1|RI_MODE_REG)
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lw $t1, 0xc($t0)
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bnez $t1, .LA4000410
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nop
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@ -30,12 +30,12 @@ glabel ipl3_entry # 0xA4000040
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sw $s5, 8($sp)
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sw $s6, 0xc($sp)
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sw $s7, 0x10($sp)
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lui $t0, %hi(RI_MODE_REG)
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addiu $t0, %lo(RI_MODE_REG)
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lui $t0, %hi(PHYS_TO_K1|RI_MODE_REG)
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addiu $t0, %lo(PHYS_TO_K1|RI_MODE_REG)
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lui $t2, (0xa3f80000 >> 16)
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lui $t3, (0xa3f00000 >> 16)
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lui $t4, %hi(MI_MODE_REG)
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addiu $t4, %lo(MI_MODE_REG)
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lui $t4, %hi(PHYS_TO_K1|MI_MODE_REG)
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addiu $t4, %lo(PHYS_TO_K1|MI_MODE_REG)
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ori $t1, $zero, 64
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sw $t1, 4($t0)
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li $s1, 8000
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@ -81,8 +81,8 @@ glabel ipl3_entry # 0xA4000040
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lui $s4, (0xA0000000 >> 16)
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addiu $sp, $sp, -0x48
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move $fp, $sp
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lui $s0, %hi(MI_VERSION_REG)
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lw $s0, %lo(MI_VERSION_REG)($s0)
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lui $s0, %hi(PHYS_TO_K1|MI_VERSION_REG)
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lw $s0, %lo(PHYS_TO_K1|MI_VERSION_REG)($s0)
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lui $s1, (0x01010101 >> 16)
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addiu $s1, (0x01010101 & 0xFFFF)
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bne $s0, $s1, .LA4000160
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@ -232,13 +232,13 @@ glabel ipl3_entry # 0xA4000040
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slt $t0, $v1, $t5
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bnez $t0, .LA4000274
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nop
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lui $t2, %hi(RI_REFRESH_REG)
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lui $t2, %hi(PHYS_TO_K1|RI_REFRESH_REG)
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sll $s2, $s2, 0x13
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lui $t1, (0x00063634 >> 16)
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ori $t1, (0x00063634 & 0xFFFF)
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or $t1, $t1, $s2
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sw $t1, %lo(RI_REFRESH_REG)($t2)
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lw $t1, %lo(RI_REFRESH_REG)($t2)
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sw $t1, %lo(PHYS_TO_K1|RI_REFRESH_REG)($t2)
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lw $t1, %lo(PHYS_TO_K1|RI_REFRESH_REG)($t2)
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lui $t0, (0xA0000300 >> 16)
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ori $t0, (0xA0000300 & 0xFFFF)
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lui $t1, (0x0FFFFFFF >> 16)
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@ -328,24 +328,24 @@ glabel ipl3_entry # 0xA4000040
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lw $t1, %lo(D_B0000008)($t3)
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lui $t2, (0x1FFFFFFF >> 16)
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ori $t2, (0x1FFFFFFF & 0xFFFF)
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lui $at, %hi(PI_DRAM_ADDR_REG)
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lui $at, %hi(PHYS_TO_K1|PI_DRAM_ADDR_REG)
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and $t1, $t1, $t2
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sw $t1, %lo(PI_DRAM_ADDR_REG)($at)
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lui $t0, %hi(PI_STATUS_REG)
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sw $t1, %lo(PHYS_TO_K1|PI_DRAM_ADDR_REG)($at)
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lui $t0, %hi(PHYS_TO_K1|PI_STATUS_REG)
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.LA40004D0:
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lw $t0, %lo(PI_STATUS_REG)($t0)
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lw $t0, %lo(PHYS_TO_K1|PI_STATUS_REG)($t0)
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andi $t0, $t0, 2
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bnezl $t0, .LA40004D0
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lui $t0, %hi(PI_STATUS_REG)
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lui $t0, %hi(PHYS_TO_K1|PI_STATUS_REG)
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li $t0, 0x1000
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add $t0, $t0, $t3
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and $t0, $t0, $t2
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lui $at, %hi(PI_CART_ADDR_REG)
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sw $t0, %lo(PI_CART_ADDR_REG)($at)
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lui $at, %hi(PHYS_TO_K1|PI_CART_ADDR_REG)
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sw $t0, %lo(PHYS_TO_K1|PI_CART_ADDR_REG)($at)
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lui $t2, 0x0010
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addiu $t2, 0xFFFF
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lui $at, %hi(PI_WR_LEN_REG)
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sw $t2, %lo(PI_WR_LEN_REG)($at)
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lui $at, %hi(PHYS_TO_K1|PI_WR_LEN_REG)
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sw $t2, %lo(PHYS_TO_K1|PI_WR_LEN_REG)($at)
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.LA4000514:
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nop
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@ -376,8 +376,8 @@ glabel ipl3_entry # 0xA4000040
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nop
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nop
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nop
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lui $t3, %hi(PI_STATUS_REG)
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lw $t3, %lo(PI_STATUS_REG)($t3)
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lui $t3, %hi(PHYS_TO_K1|PI_STATUS_REG)
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lw $t3, %lo(PHYS_TO_K1|PI_STATUS_REG)($t3)
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andi $t3, $t3, 0x1
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bnez $t3, .LA4000514
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nop
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@ -451,37 +451,37 @@ halt: # checksum fail
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nop
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func_A4000690:
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lui $t1, %hi(SP_PC)
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lw $t1, %lo(SP_PC)($t1)
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lui $t1, %hi(PHYS_TO_K1|SP_PC_REG)
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lw $t1, %lo(PHYS_TO_K1|SP_PC_REG)($t1)
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lw $s0, 0x14($sp)
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lw $ra, 0x1c($sp)
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beqz $t1, .LA40006BC
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addiu $sp, $sp, 0x20
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li $t2, 65
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lui $at, %hi(SP_STATUS_REG)
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sw $t2, %lo(SP_STATUS_REG)($at)
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lui $at, %hi(SP_PC)
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sw $zero, %lo(SP_PC)($at)
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lui $at, %hi(PHYS_TO_K1|SP_STATUS_REG)
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sw $t2, %lo(PHYS_TO_K1|SP_STATUS_REG)($at)
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lui $at, %hi(PHYS_TO_K1|SP_PC_REG)
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sw $zero, %lo(PHYS_TO_K1|SP_PC_REG)($at)
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.LA40006BC:
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lui $t3, (0x00AAAAAE >> 16)
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ori $t3, (0x00AAAAAE & 0xFFFF)
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lui $at, %hi(SP_STATUS_REG)
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sw $t3, %lo(SP_STATUS_REG)($at)
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lui $at, %hi(MI_INTR_MASK_REG)
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lui $at, %hi(PHYS_TO_K1|SP_STATUS_REG)
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sw $t3, %lo(PHYS_TO_K1|SP_STATUS_REG)($at)
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lui $at, %hi(PHYS_TO_K1|MI_INTR_MASK_REG)
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li $t0, 1365
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sw $t0, %lo(MI_INTR_MASK_REG)($at)
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lui $at, %hi(SI_STATUS_REG)
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sw $zero, %lo(SI_STATUS_REG)($at)
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lui $at, %hi(AI_STATUS_REG)
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sw $zero, %lo(AI_STATUS_REG)($at)
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lui $at, %hi(MI_MODE_REG)
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sw $t0, %lo(PHYS_TO_K1|MI_INTR_MASK_REG)($at)
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lui $at, %hi(PHYS_TO_K1|SI_STATUS_REG)
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sw $zero, %lo(PHYS_TO_K1|SI_STATUS_REG)($at)
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lui $at, %hi(PHYS_TO_K1|AI_STATUS_REG)
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sw $zero, %lo(PHYS_TO_K1|AI_STATUS_REG)($at)
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lui $at, %hi(PHYS_TO_K1|MI_MODE_REG)
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li $t1, 2048
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sw $t1, %lo(MI_MODE_REG)($at)
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sw $t1, %lo(PHYS_TO_K1|MI_MODE_REG)($at)
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li $t1, 2
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lui $at, %hi(PI_STATUS_REG)
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lui $at, %hi(PHYS_TO_K1|PI_STATUS_REG)
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lui $t0, (0xA0000300 >> 16)
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ori $t0, (0xA0000300 & 0xFFFF)
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sw $t1, %lo(PI_STATUS_REG)($at)
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sw $t1, %lo(PHYS_TO_K1|PI_STATUS_REG)($at)
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sw $s7, 0x14($t0)
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sw $s5, 0xc($t0)
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sw $s3, 0x4($t0)
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@ -747,8 +747,8 @@ func_A4000A40:
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li $k1, 1
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bne $a1, $k1, .LA4000AC0
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sw $t7, ($s5)
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lui $k0, %hi(MI_MODE_REG)
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sw $zero, %lo(MI_MODE_REG)($k0)
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lui $k0, %hi(PHYS_TO_K1|MI_MODE_REG)
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sw $zero, %lo(PHYS_TO_K1|MI_MODE_REG)($k0)
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.LA4000AC0:
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lw $ra, 0x1c($sp)
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addiu $sp, $sp, 0x28
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@ -759,12 +759,12 @@ func_A4000AD0:
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addiu $sp, $sp, -0x28
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sw $ra, 0x1c($sp)
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li $k0, 0x2000
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lui $k1, %hi(MI_MODE_REG)
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sw $k0, %lo(MI_MODE_REG)($k1)
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lui $k1, %hi(PHYS_TO_K1|MI_MODE_REG)
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sw $k0, %lo(PHYS_TO_K1|MI_MODE_REG)($k1)
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move $fp, $zero
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lw $fp, ($s5)
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li $k0, 0x1000
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sw $k0, %lo(MI_MODE_REG)($k1)
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sw $k0, %lo(PHYS_TO_K1|MI_MODE_REG)($k1)
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li $k1, 0x40
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and $k1, $k1, $fp
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srl $k1, $k1, 6
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@ -8,10 +8,10 @@
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glabel __osDisableInt
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mfc0 $t0, $12
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and $t1, $t0, -2
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mtc0 $t1, $12
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andi $v0, $t0, 1
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mfc0 $t0, C0_SR
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and $t1, $t0, ~SR_IE
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mtc0 $t1, C0_SR
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andi $v0, $t0, SR_IE
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nop
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jr $ra
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nop
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File diff suppressed because it is too large
Load Diff
@ -7,7 +7,7 @@
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.section .text, "ax"
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glabel __osGetSR
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mfc0 $v0, $12
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mfc0 $v0, C0_SR
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jr $ra
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nop
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@ -8,20 +8,20 @@
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.section .text, "ax"
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glabel __osProbeTLB
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mfc0 $t0, $10
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andi $t1, $t0, 0xff
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li $at, -8192
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mfc0 $t0, C0_ENTRYHI
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andi $t1, $t0, TLBHI_PIDMASK
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li $at, TLBHI_VPN2MASK
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and $t2, $a0, $at
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or $t1, $t1, $t2
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mtc0 $t1, $10
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mtc0 $t1, C0_ENTRYHI
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nop
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nop
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nop
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tlbp
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nop
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nop
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mfc0 $t3, $0
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lui $at, 0x8000
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mfc0 $t3, C0_INX
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lui $at, %hi(TLBINX_PROBE)
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and $t3, $t3, $at
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bnez $t3, .L8032A0D8
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nop
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@ -29,25 +29,25 @@ glabel __osProbeTLB
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nop
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nop
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nop
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mfc0 $t3, $5
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addi $t3, $t3, 0x2000
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mfc0 $t3, C0_PAGEMASK
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addi $t3, $t3, DCACHE_SIZE
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srl $t3, $t3, 1
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and $t4, $t3, $a0
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bnez $t4, .L8032A0A8
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addi $t3, $t3, -1
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mfc0 $v0, $2
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mfc0 $v0, C0_ENTRYLO0
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b .L8032A0AC
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nop
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.L8032A0A8:
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mfc0 $v0, $3
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mfc0 $v0, C0_ENTRYLO1
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.L8032A0AC:
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andi $t5, $v0, 2
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andi $t5, $v0, TLBLO_V
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beqz $t5, .L8032A0D8
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nop
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lui $at, (0x3FFFFFC0 >> 16) # lui $at, 0x3fff
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ori $at, (0x3FFFFFC0 & 0xFFFF) # ori $at, $at, 0xffc0
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lui $at, (TLBLO_PFNMASK >> 16) # lui $at, 0x3fff
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ori $at, %lo(TLBLO_PFNMASK) # ori $at, $at, 0xffc0
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and $v0, $v0, $at
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sll $v0, $v0, 6
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sll $v0, $v0, TLBLO_PFNSHIFT
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and $t5, $a0, $t3
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add $v0, $v0, $t5
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b .L8032A0DC
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@ -55,7 +55,7 @@ glabel __osProbeTLB
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.L8032A0D8:
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li $v0, -1
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.L8032A0DC:
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mtc0 $t0, $10
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mtc0 $t0, C0_ENTRYHI
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jr $ra
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nop
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@ -7,9 +7,9 @@
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.section .text, "ax"
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glabel __osRestoreInt
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mfc0 $t0, $12
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mfc0 $t0, C0_SR
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or $t0, $t0, $a0
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mtc0 $t0, $12
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mtc0 $t0, C0_SR
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nop
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nop
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jr $ra
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@ -7,7 +7,7 @@
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.section .text, "ax"
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glabel __osSetCompare
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mtc0 $a0, $11
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mtc0 $a0, C0_COMPARE
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jr $ra
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nop
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@ -7,7 +7,7 @@
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.section .text, "ax"
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glabel __osSetSR
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mtc0 $a0, $12
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mtc0 $a0, C0_SR
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nop
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jr $ra
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nop
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@ -8,28 +8,28 @@
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.section .text, "ax"
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glabel bcopy
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beqz $a2, .L80323A4C
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beqz $a2, ret
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move $a3, $a1
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beq $a0, $a1, .L80323A4C
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beq $a0, $a1, ret
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slt $at, $a1, $a0
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bnezl $at, .L80323A14
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bnezl $at, goforwards
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slti $at, $a2, 0x10
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add $v0, $a0, $a2
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slt $at, $a1, $v0
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beql $at, $zero, .L80323A14
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beql $at, $zero, goforwards
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slti $at, $a2, 0x10
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b .L80323B78
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b gobackwards
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slti $at, $a2, 0x10
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slti $at, $a2, 0x10
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.L80323A14:
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bnez $at, .L80323A2C
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goforwards:
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bnez $at, forwards_bytecopy
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nop
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andi $v0, $a0, 3
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andi $v1, $a1, 3
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beq $v0, $v1, .L80323A54
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beq $v0, $v1, forwalignable
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nop
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.L80323A2C:
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beqz $a2, .L80323A4C
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forwards_bytecopy:
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beqz $a2, ret
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nop
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addu $v1, $a0, $a2
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.L80323A38:
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@ -38,31 +38,31 @@ glabel bcopy
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addiu $a1, $a1, 1
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bne $a0, $v1, .L80323A38
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sb $v0, -1($a1)
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.L80323A4C:
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ret:
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jr $ra
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move $v0, $a3
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.L80323A54:
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beqz $v0, .L80323AB8
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forwalignable:
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beqz $v0, forwards
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li $at, 1
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beq $v0, $at, .L80323A9C
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beq $v0, $at, forw_copy3
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li $at, 2
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beql $v0, $at, .L80323A88
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beql $v0, $at, forw_copy2
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lh $v0, ($a0)
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lb $v0, ($a0)
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addiu $a0, $a0, 1
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addiu $a1, $a1, 1
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addiu $a2, $a2, -1
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b .L80323AB8
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b forwards
|
||||
sb $v0, -1($a1)
|
||||
lh $v0, ($a0)
|
||||
.L80323A88:
|
||||
forw_copy2:
|
||||
addiu $a0, $a0, 2
|
||||
addiu $a1, $a1, 2
|
||||
addiu $a2, $a2, -2
|
||||
b .L80323AB8
|
||||
b forwards
|
||||
sh $v0, -2($a1)
|
||||
.L80323A9C:
|
||||
forw_copy3:
|
||||
lb $v0, ($a0)
|
||||
lh $v1, 1($a0)
|
||||
addiu $a0, $a0, 3
|
||||
@ -70,9 +70,9 @@ glabel bcopy
|
||||
addiu $a2, $a2, -3
|
||||
sb $v0, -3($a1)
|
||||
sh $v1, -2($a1)
|
||||
.L80323AB8:
|
||||
forwards:
|
||||
slti $at, $a2, 0x20
|
||||
bnezl $at, .L80323B18
|
||||
bnezl $at, forwards_16
|
||||
slti $at, $a2, 0x10
|
||||
lw $v0, ($a0)
|
||||
lw $v1, 4($a0)
|
||||
@ -92,11 +92,11 @@ glabel bcopy
|
||||
sw $t2, -0x10($a1)
|
||||
sw $t3, -0xc($a1)
|
||||
sw $t4, -8($a1)
|
||||
b .L80323AB8
|
||||
b forwards
|
||||
sw $t5, -4($a1)
|
||||
.L80323B14:
|
||||
slti $at, $a2, 0x10
|
||||
.L80323B18:
|
||||
forwards_16:
|
||||
bnezl $at, .L80323B54
|
||||
slti $at, $a2, 4
|
||||
lw $v0, ($a0)
|
||||
@ -111,19 +111,19 @@ glabel bcopy
|
||||
sw $t0, -8($a1)
|
||||
b .L80323B14
|
||||
sw $t1, -4($a1)
|
||||
.L80323B50:
|
||||
forwards_4:
|
||||
slti $at, $a2, 4
|
||||
.L80323B54:
|
||||
bnez $at, .L80323A2C
|
||||
bnez $at, forwards_bytecopy
|
||||
nop
|
||||
lw $v0, ($a0)
|
||||
addiu $a0, $a0, 4
|
||||
addiu $a1, $a1, 4
|
||||
addiu $a2, $a2, -4
|
||||
b .L80323B50
|
||||
b forwards_4
|
||||
sw $v0, -4($a1)
|
||||
slti $at, $a2, 0x10
|
||||
.L80323B78:
|
||||
gobackwards:
|
||||
add $a0, $a0, $a2
|
||||
bnez $at, .L80323B94
|
||||
add $a1, $a1, $a2
|
||||
@ -132,7 +132,7 @@ glabel bcopy
|
||||
beq $v0, $v1, .L80323BC4
|
||||
nop
|
||||
.L80323B94:
|
||||
beqz $a2, .L80323A4C
|
||||
beqz $a2, ret
|
||||
nop
|
||||
addiu $a0, $a0, -1
|
||||
addiu $a1, $a1, -1
|
||||
@ -147,7 +147,7 @@ glabel bcopy
|
||||
move $v0, $a3
|
||||
|
||||
.L80323BC4:
|
||||
beqz $v0, .L80323C28
|
||||
beqz $v0, backwards_32
|
||||
li $at, 3
|
||||
beq $v0, $at, .L80323C0C
|
||||
li $at, 2
|
||||
@ -157,14 +157,14 @@ glabel bcopy
|
||||
addiu $a0, $a0, -1
|
||||
addiu $a1, $a1, -1
|
||||
addiu $a2, $a2, -1
|
||||
b .L80323C28
|
||||
b backwards_32
|
||||
sb $v0, ($a1)
|
||||
lh $v0, -2($a0)
|
||||
.L80323BF8:
|
||||
addiu $a0, $a0, -2
|
||||
addiu $a1, $a1, -2
|
||||
addiu $a2, $a2, -2
|
||||
b .L80323C28
|
||||
b backwards_32
|
||||
sh $v0, ($a1)
|
||||
.L80323C0C:
|
||||
lb $v0, -1($a0)
|
||||
@ -174,7 +174,7 @@ glabel bcopy
|
||||
addiu $a2, $a2, -3
|
||||
sb $v0, 2($a1)
|
||||
sh $v1, ($a1)
|
||||
.L80323C28:
|
||||
backwards_32:
|
||||
slti $at, $a2, 0x20
|
||||
bnezl $at, .L80323C88
|
||||
slti $at, $a2, 0x10
|
||||
@ -196,9 +196,9 @@ glabel bcopy
|
||||
sw $t2, 0xc($a1)
|
||||
sw $t3, 8($a1)
|
||||
sw $t4, 4($a1)
|
||||
b .L80323C28
|
||||
b backwards_32
|
||||
sw $t5, ($a1)
|
||||
.L80323C84:
|
||||
backwards_16:
|
||||
slti $at, $a2, 0x10
|
||||
.L80323C88:
|
||||
bnezl $at, .L80323CC4
|
||||
@ -213,9 +213,9 @@ glabel bcopy
|
||||
sw $v0, 0xc($a1)
|
||||
sw $v1, 8($a1)
|
||||
sw $t0, 4($a1)
|
||||
b .L80323C84
|
||||
b backwards_16
|
||||
sw $t1, ($a1)
|
||||
.L80323CC0:
|
||||
backwards_4:
|
||||
slti $at, $a2, 4
|
||||
.L80323CC4:
|
||||
bnez $at, .L80323B94
|
||||
@ -224,7 +224,7 @@ glabel bcopy
|
||||
addiu $a0, $a0, -4
|
||||
addiu $a1, $a1, -4
|
||||
addiu $a2, $a2, -4
|
||||
b .L80323CC0
|
||||
b backwards_4
|
||||
sw $v0, ($a1)
|
||||
nop
|
||||
nop
|
||||
|
||||
@ -11,17 +11,17 @@
|
||||
|
||||
glabel bzero
|
||||
/* 0CE660 800CDA60 28A1000C */ slti $at, $a1, 0xc
|
||||
/* 0CE664 800CDA64 1420001D */ bnez $at, .L800CDADC
|
||||
/* 0CE664 800CDA64 1420001D */ bnez $at, bytezero
|
||||
/* 0CE668 800CDA68 00041823 */ negu $v1, $a0
|
||||
/* 0CE66C 800CDA6C 30630003 */ andi $v1, $v1, 3
|
||||
/* 0CE670 800CDA70 10600003 */ beqz $v1, .L800CDA80
|
||||
/* 0CE670 800CDA70 10600003 */ beqz $v1, blkzero
|
||||
/* 0CE674 800CDA74 00A32823 */ subu $a1, $a1, $v1
|
||||
/* 0CE678 800CDA78 A8800000 */ swl $zero, ($a0)
|
||||
/* 0CE67C 800CDA7C 00832021 */ addu $a0, $a0, $v1
|
||||
.L800CDA80:
|
||||
blkzero:
|
||||
/* 0CE680 800CDA80 2401FFE0 */ li $at, -32
|
||||
/* 0CE684 800CDA84 00A13824 */ and $a3, $a1, $at
|
||||
/* 0CE688 800CDA88 10E0000C */ beqz $a3, .L800CDABC
|
||||
/* 0CE688 800CDA88 10E0000C */ beqz $a3, wordzero
|
||||
/* 0CE68C 800CDA8C 00A72823 */ subu $a1, $a1, $a3
|
||||
/* 0CE690 800CDA90 00E43821 */ addu $a3, $a3, $a0
|
||||
.L800CDA94:
|
||||
@ -35,25 +35,25 @@ glabel bzero
|
||||
/* 0CE6B0 800CDAB0 AC80FFF8 */ sw $zero, -8($a0)
|
||||
/* 0CE6B4 800CDAB4 1487FFF7 */ bne $a0, $a3, .L800CDA94
|
||||
/* 0CE6B8 800CDAB8 AC80FFFC */ sw $zero, -4($a0)
|
||||
.L800CDABC:
|
||||
wordzero:
|
||||
/* 0CE6BC 800CDABC 2401FFFC */ li $at, -4
|
||||
/* 0CE6C0 800CDAC0 00A13824 */ and $a3, $a1, $at
|
||||
/* 0CE6C4 800CDAC4 10E00005 */ beqz $a3, .L800CDADC
|
||||
/* 0CE6C4 800CDAC4 10E00005 */ beqz $a3, bytezero
|
||||
/* 0CE6C8 800CDAC8 00A72823 */ subu $a1, $a1, $a3
|
||||
/* 0CE6CC 800CDACC 00E43821 */ addu $a3, $a3, $a0
|
||||
.L800CDAD0:
|
||||
/* 0CE6D0 800CDAD0 24840004 */ addiu $a0, $a0, 4
|
||||
/* 0CE6D4 800CDAD4 1487FFFE */ bne $a0, $a3, .L800CDAD0
|
||||
/* 0CE6D8 800CDAD8 AC80FFFC */ sw $zero, -4($a0)
|
||||
.L800CDADC:
|
||||
/* 0CE6DC 800CDADC 18A00005 */ blez $a1, .L800CDAF4
|
||||
bytezero:
|
||||
/* 0CE6DC 800CDADC 18A00005 */ blez $a1, zerodone
|
||||
/* 0CE6E0 800CDAE0 00000000 */ nop
|
||||
/* 0CE6E4 800CDAE4 00A42821 */ addu $a1, $a1, $a0
|
||||
.L800CDAE8:
|
||||
/* 0CE6E8 800CDAE8 24840001 */ addiu $a0, $a0, 1
|
||||
/* 0CE6EC 800CDAEC 1485FFFE */ bne $a0, $a1, .L800CDAE8
|
||||
/* 0CE6F0 800CDAF0 A080FFFF */ sb $zero, -1($a0)
|
||||
.L800CDAF4:
|
||||
zerodone:
|
||||
/* 0CE6F4 800CDAF4 03E00008 */ jr $ra
|
||||
/* 0CE6F8 800CDAF8 00000000 */ nop
|
||||
|
||||
|
||||
@ -11,7 +11,7 @@
|
||||
glabel osInvalDCache
|
||||
/* 0CE780 800CDB80 18A0001F */ blez $a1, .L800CDC00
|
||||
/* 0CE784 800CDB84 00000000 */ nop
|
||||
/* 0CE788 800CDB88 240B2000 */ li $t3, 8192
|
||||
/* 0CE788 800CDB88 240B2000 */ li $t3, DCACHE_SIZE
|
||||
/* 0CE78C 800CDB8C 00AB082B */ sltu $at, $a1, $t3
|
||||
/* 0CE790 800CDB90 1020001D */ beqz $at, .L800CDC08
|
||||
/* 0CE794 800CDB94 00000000 */ nop
|
||||
@ -20,42 +20,42 @@ glabel osInvalDCache
|
||||
/* 0CE7A0 800CDBA0 0109082B */ sltu $at, $t0, $t1
|
||||
/* 0CE7A4 800CDBA4 10200016 */ beqz $at, .L800CDC00
|
||||
/* 0CE7A8 800CDBA8 00000000 */ nop
|
||||
/* 0CE7AC 800CDBAC 310A000F */ andi $t2, $t0, 0xf
|
||||
/* 0CE7AC 800CDBAC 310A000F */ andi $t2, $t0, DCACHE_LINEMASK
|
||||
/* 0CE7B0 800CDBB0 11400007 */ beqz $t2, .L800CDBD0
|
||||
/* 0CE7B4 800CDBB4 2529FFF0 */ addiu $t1, $t1, -0x10
|
||||
/* 0CE7B4 800CDBB4 2529FFF0 */ addiu $t1, $t1, -DCACHE_LINESIZE
|
||||
/* 0CE7B8 800CDBB8 010A4023 */ subu $t0, $t0, $t2
|
||||
/* 0CE7BC 800CDBBC BD150000 */ cache 0x15, ($t0)
|
||||
/* 0CE7BC 800CDBBC BD150000 */ cache (C_HWBINV|CACH_PD), ($t0)
|
||||
/* 0CE7C0 800CDBC0 0109082B */ sltu $at, $t0, $t1
|
||||
/* 0CE7C4 800CDBC4 1020000E */ beqz $at, .L800CDC00
|
||||
/* 0CE7C8 800CDBC8 00000000 */ nop
|
||||
/* 0CE7CC 800CDBCC 25080010 */ addiu $t0, $t0, 0x10
|
||||
/* 0CE7CC 800CDBCC 25080010 */ addiu $t0, $t0, DCACHE_LINESIZE
|
||||
.L800CDBD0:
|
||||
/* 0CE7D0 800CDBD0 312A000F */ andi $t2, $t1, 0xf
|
||||
/* 0CE7D0 800CDBD0 312A000F */ andi $t2, $t1, DCACHE_LINEMASK
|
||||
/* 0CE7D4 800CDBD4 11400006 */ beqz $t2, .L800CDBF0
|
||||
/* 0CE7D8 800CDBD8 00000000 */ nop
|
||||
/* 0CE7DC 800CDBDC 012A4823 */ subu $t1, $t1, $t2
|
||||
/* 0CE7E0 800CDBE0 BD350010 */ cache 0x15, 0x10($t1)
|
||||
/* 0CE7E0 800CDBE0 BD350010 */ cache C_HWBINV|CACH_PD, 0x10($t1)
|
||||
/* 0CE7E4 800CDBE4 0128082B */ sltu $at, $t1, $t0
|
||||
/* 0CE7E8 800CDBE8 14200005 */ bnez $at, .L800CDC00
|
||||
/* 0CE7EC 800CDBEC 00000000 */ nop
|
||||
.L800CDBF0:
|
||||
/* 0CE7F0 800CDBF0 BD110000 */ cache 0x11, ($t0)
|
||||
/* 0CE7F0 800CDBF0 BD110000 */ cache C_HINV|CACH_PD, ($t0)
|
||||
/* 0CE7F4 800CDBF4 0109082B */ sltu $at, $t0, $t1
|
||||
/* 0CE7F8 800CDBF8 1420FFFD */ bnez $at, .L800CDBF0
|
||||
/* 0CE7FC 800CDBFC 25080010 */ addiu $t0, $t0, 0x10
|
||||
/* 0CE7FC 800CDBFC 25080010 */ addiu $t0, $t0, DCACHE_LINESIZE
|
||||
.L800CDC00:
|
||||
/* 0CE800 800CDC00 03E00008 */ jr $ra
|
||||
/* 0CE804 800CDC04 00000000 */ nop
|
||||
|
||||
.L800CDC08:
|
||||
/* 0CE808 800CDC08 3C088000 */ li $t0, 0x80000000
|
||||
/* 0CE808 800CDC08 3C088000 */ li $t0, KUSIZE
|
||||
/* 0CE80C 800CDC0C 010B4821 */ addu $t1, $t0, $t3
|
||||
/* 0CE810 800CDC10 2529FFF0 */ addiu $t1, $t1, -0x10
|
||||
/* 0CE810 800CDC10 2529FFF0 */ addiu $t1, $t1, -DCACHE_LINESIZE
|
||||
.L800CDC14:
|
||||
/* 0CE814 800CDC14 BD010000 */ cache 1, ($t0)
|
||||
/* 0CE818 800CDC18 0109082B */ sltu $at, $t0, $t1
|
||||
/* 0CE81C 800CDC1C 1420FFFD */ bnez $at, .L800CDC14
|
||||
/* 0CE820 800CDC20 25080010 */ addiu $t0, $t0, 0x10
|
||||
/* 0CE820 800CDC20 25080010 */ addiu $t0, $t0, DCACHE_LINESIZE
|
||||
/* 0CE824 800CDC24 03E00008 */ jr $ra
|
||||
/* 0CE828 800CDC28 00000000 */ nop
|
||||
|
||||
|
||||
@ -12,7 +12,7 @@
|
||||
glabel osInvalICache
|
||||
/* 0CE700 800CDB00 18A00011 */ blez $a1, .L800CDB48
|
||||
/* 0CE704 800CDB04 00000000 */ nop
|
||||
/* 0CE708 800CDB08 240B4000 */ li $t3, 16384
|
||||
/* 0CE708 800CDB08 240B4000 */ li $t3, ICACHE_SIZE
|
||||
/* 0CE70C 800CDB0C 00AB082B */ sltu $at, $a1, $t3
|
||||
/* 0CE710 800CDB10 1020000F */ beqz $at, .L800CDB50
|
||||
/* 0CE714 800CDB14 00000000 */ nop
|
||||
@ -21,27 +21,27 @@ glabel osInvalICache
|
||||
/* 0CE720 800CDB20 0109082B */ sltu $at, $t0, $t1
|
||||
/* 0CE724 800CDB24 10200008 */ beqz $at, .L800CDB48
|
||||
/* 0CE728 800CDB28 00000000 */ nop
|
||||
/* 0CE72C 800CDB2C 310A001F */ andi $t2, $t0, 0x1f
|
||||
/* 0CE730 800CDB30 2529FFE0 */ addiu $t1, $t1, -0x20
|
||||
/* 0CE72C 800CDB2C 310A001F */ andi $t2, $t0, ICACHE_LINEMASK
|
||||
/* 0CE730 800CDB30 2529FFE0 */ addiu $t1, $t1, -ICACHE_LINESIZE
|
||||
/* 0CE734 800CDB34 010A4023 */ subu $t0, $t0, $t2
|
||||
.L800CDB38:
|
||||
/* 0CE738 800CDB38 BD100000 */ cache 0x10, ($t0)
|
||||
/* 0CE738 800CDB38 BD100000 */ cache C_HINV|CACH_PI, ($t0)
|
||||
/* 0CE73C 800CDB3C 0109082B */ sltu $at, $t0, $t1
|
||||
/* 0CE740 800CDB40 1420FFFD */ bnez $at, .L800CDB38
|
||||
/* 0CE744 800CDB44 25080020 */ addiu $t0, $t0, 0x20
|
||||
/* 0CE744 800CDB44 25080020 */ addiu $t0, $t0, ICACHE_LINESIZE
|
||||
.L800CDB48:
|
||||
/* 0CE748 800CDB48 03E00008 */ jr $ra
|
||||
/* 0CE74C 800CDB4C 00000000 */ nop
|
||||
|
||||
.L800CDB50:
|
||||
/* 0CE750 800CDB50 3C088000 */ li $t0, 0x80000000
|
||||
/* 0CE750 800CDB50 3C088000 */ li $t0, KUSIZE
|
||||
/* 0CE754 800CDB54 010B4821 */ addu $t1, $t0, $t3
|
||||
/* 0CE758 800CDB58 2529FFE0 */ addiu $t1, $t1, -0x20
|
||||
/* 0CE758 800CDB58 2529FFE0 */ addiu $t1, $t1, -ICACHE_LINESIZE
|
||||
.L800CDB5C:
|
||||
/* 0CE75C 800CDB5C BD000000 */ cache 0, ($t0)
|
||||
/* 0CE75C 800CDB5C BD000000 */ cache C_IINV|CACH_PI, ($t0)
|
||||
/* 0CE760 800CDB60 0109082B */ sltu $at, $t0, $t1
|
||||
/* 0CE764 800CDB64 1420FFFD */ bnez $at, .L800CDB5C
|
||||
/* 0CE768 800CDB68 25080020 */ addiu $t0, $t0, 0x20
|
||||
/* 0CE768 800CDB68 25080020 */ addiu $t0, $t0, ICACHE_LINESIZE
|
||||
/* 0CE76C 800CDB6C 03E00008 */ jr $ra
|
||||
/* 0CE770 800CDB70 00000000 */ nop
|
||||
|
||||
|
||||
@ -8,26 +8,26 @@
|
||||
.section .text, "ax"
|
||||
|
||||
glabel osMapTLBRdb
|
||||
mfc0 $t0, $10
|
||||
mfc0 $t0, C0_ENTRYHI
|
||||
li $t1, 31
|
||||
mtc0 $t1, $0
|
||||
mtc0 $zero, $5
|
||||
li $t2, 23
|
||||
lui $t1, 0xc000
|
||||
mtc0 $t1, $10
|
||||
lui $t1, 0x8000
|
||||
srl $t3, $t1, 6
|
||||
mtc0 $t1, C0_INX
|
||||
mtc0 $zero, C0_PAGEMASK
|
||||
li $t2, TLBLO_UNCACHED | TLBLO_D | TLBLO_V | TLBLO_G
|
||||
lui $t1, K2BASE >> 16
|
||||
mtc0 $t1, C0_ENTRYHI
|
||||
lui $t1, KUSIZE >> 16
|
||||
srl $t3, $t1, TLBLO_PFNSHIFT
|
||||
or $t3, $t3, $t2
|
||||
mtc0 $t3, $2
|
||||
li $t1, 1
|
||||
mtc0 $t1, $3
|
||||
mtc0 $t3, C0_ENTRYLO0
|
||||
li $t1, TLBLO_G
|
||||
mtc0 $t1, C0_ENTRYLO1
|
||||
nop
|
||||
tlbwi
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
mtc0 $t0, $10
|
||||
mtc0 $t0, C0_ENTRYHI
|
||||
jr $ra
|
||||
nop
|
||||
|
||||
|
||||
@ -4,66 +4,64 @@
|
||||
|
||||
.include "macros.inc"
|
||||
|
||||
.eqv MI_INTR_MASK_REG, 0xA430000C
|
||||
|
||||
.set VERSION_EU_SH, 1
|
||||
|
||||
.section .text, "ax"
|
||||
|
||||
glabel osSetIntMask
|
||||
.ifdef VERSION_EU_SH
|
||||
mfc0 $t4, $12
|
||||
andi $v0, $t4, 0xff01
|
||||
mfc0 $t4, C0_SR
|
||||
andi $v0, $t4, OS_IM_CPU
|
||||
lui $t0, %hi(__OSGlobalIntMask) # $t0, 0x8030
|
||||
addiu $t0, %lo(__OSGlobalIntMask) # addiu $t0, $t0, 0x208c
|
||||
lw $t3, ($t0)
|
||||
li $at, -1
|
||||
xor $t0, $t3, $at
|
||||
andi $t0, $t0, 0xff00
|
||||
andi $t0, $t0, SR_IMASK
|
||||
or $v0, $v0, $t0
|
||||
.else
|
||||
mfc0 $t1, $12
|
||||
andi $v0, $t1, 0xff01
|
||||
mfc0 $t1, C0_SR
|
||||
andi $v0, $t1, OS_IM_CPU
|
||||
.endif
|
||||
lui $t2, %hi(MI_INTR_MASK_REG) # $t2, 0xa430
|
||||
lw $t2, %lo(MI_INTR_MASK_REG)($t2)
|
||||
lui $t2, %hi(PHYS_TO_K1|MI_INTR_MASK_REG) # $t2, 0xa430
|
||||
lw $t2, %lo(PHYS_TO_K1|MI_INTR_MASK_REG)($t2)
|
||||
.ifdef VERSION_EU_SH
|
||||
beqz $t2, .L80200074
|
||||
srl $t1, $t3, 0x10
|
||||
li $at, -1
|
||||
xor $t1, $t1, $at
|
||||
andi $t1, $t1, 0x3f
|
||||
andi $t1, $t1, MI_INTR_MASK
|
||||
or $t2, $t2, $t1
|
||||
.L80200074:
|
||||
.endif
|
||||
sll $t2, $t2, 0x10
|
||||
or $v0, $v0, $t2
|
||||
lui $at, 0x3f
|
||||
lui $at, MI_INTR_MASK
|
||||
and $t0, $a0, $at
|
||||
.ifdef VERSION_EU_SH
|
||||
and $t0, $t0, $t3
|
||||
.endif
|
||||
srl $t0, $t0, 0xf
|
||||
lui $t2, %hi(D_800F3C10)
|
||||
lui $t2, %hi(__osRcpImTable)
|
||||
addu $t2, $t2, $t0
|
||||
lhu $t2, %lo(D_800F3C10)($t2)
|
||||
lui $at, %hi(MI_INTR_MASK_REG) # $at, 0xa430
|
||||
sw $t2, %lo(MI_INTR_MASK_REG)($at)
|
||||
andi $t0, $a0, 0xff01
|
||||
lhu $t2, %lo(__osRcpImTable)($t2)
|
||||
lui $at, %hi(PHYS_TO_K1|MI_INTR_MASK_REG) # $at, 0xa430
|
||||
sw $t2, %lo(PHYS_TO_K1|MI_INTR_MASK_REG)($at)
|
||||
andi $t0, $a0, OS_IM_CPU
|
||||
.ifdef VERSION_EU_SH
|
||||
andi $t1, $t3, 0xff00
|
||||
andi $t1, $t3, SR_IMASK
|
||||
and $t0, $t0, $t1
|
||||
.endif
|
||||
lui $at, (0xFFFF00FF >> 16) # lui $at, 0xffff
|
||||
ori $at, (0xFFFF00FF & 0xFFFF) # ori $at, $at, 0xff
|
||||
lui $at, %hi(~SR_IMASK) # lui $at, 0xffff
|
||||
ori $at, %lo(~SR_IMASK) # ori $at, $at, 0xff
|
||||
.ifdef VERSION_EU_SH
|
||||
and $t4, $t4, $at
|
||||
or $t4, $t4, $t0
|
||||
mtc0 $t4, $12
|
||||
mtc0 $t4, C0_SR
|
||||
.else
|
||||
and $t1, $t1, $at
|
||||
or $t1, $t1, $t0
|
||||
mtc0 $t1, $12
|
||||
mtc0 $t1, C0_SR
|
||||
.endif
|
||||
nop
|
||||
nop
|
||||
@ -73,68 +71,85 @@ glabel osSetIntMask
|
||||
|
||||
.section .rodata
|
||||
|
||||
glabel D_800F3C10
|
||||
.half 0x0555
|
||||
.half 0x0556
|
||||
.half 0x0559
|
||||
.half 0x055A
|
||||
.half 0x0565
|
||||
.half 0x0566
|
||||
.half 0x0569
|
||||
.half 0x056A
|
||||
.half 0x0595
|
||||
.half 0x0596
|
||||
.half 0x0599
|
||||
.half 0x059A
|
||||
.half 0x05A5
|
||||
.half 0x05A6
|
||||
.half 0x05A9
|
||||
.half 0x05AA
|
||||
.half 0x0655
|
||||
.half 0x0656
|
||||
.half 0x0659
|
||||
.half 0x065A
|
||||
.half 0x0665
|
||||
.half 0x0666
|
||||
.half 0x0669
|
||||
.half 0x066A
|
||||
.half 0x0695
|
||||
.half 0x0696
|
||||
.half 0x0699
|
||||
.half 0x069A
|
||||
.half 0x06A5
|
||||
.half 0x06A6
|
||||
.half 0x06A9
|
||||
.half 0x06AA
|
||||
.half 0x0955
|
||||
.half 0x0956
|
||||
.half 0x0959
|
||||
.half 0x095A
|
||||
.half 0x0965
|
||||
.half 0x0966
|
||||
.half 0x0969
|
||||
.half 0x096A
|
||||
.half 0x0995
|
||||
.half 0x0996
|
||||
.half 0x0999
|
||||
.half 0x099A
|
||||
.half 0x09A5
|
||||
.half 0x09A6
|
||||
.half 0x09A9
|
||||
.half 0x09AA
|
||||
.half 0x0A55
|
||||
.half 0x0A56
|
||||
.half 0x0A59
|
||||
.half 0x0A5A
|
||||
.half 0x0A65
|
||||
.half 0x0A66
|
||||
.half 0x0A69
|
||||
.half 0x0A6A
|
||||
.half 0x0A95
|
||||
.half 0x0A96
|
||||
.half 0x0A99
|
||||
.half 0x0A9A
|
||||
.half 0x0AA5
|
||||
.half 0x0AA6
|
||||
.half 0x0AA9
|
||||
.half 0x0AAA
|
||||
.set MI_INTR_MASK, 0x3f
|
||||
.set CLR_SP, 0x0001
|
||||
.set SET_SP, 0x0002
|
||||
.set CLR_SI, 0x0004
|
||||
.set SET_SI, 0x0008
|
||||
.set CLR_AI, 0x0010
|
||||
.set SET_AI, 0x0020
|
||||
.set CLR_VI, 0x0040
|
||||
.set SET_VI, 0x0080
|
||||
.set CLR_PI, 0x0100
|
||||
.set SET_PI, 0x0200
|
||||
.set CLR_DP, 0x0400
|
||||
.set SET_DP, 0x0800
|
||||
|
||||
glabel __osRcpImTable
|
||||
/* LUT to convert between MI_INTR and MI_INTR_MASK */
|
||||
/* MI_INTR is status for each interrupt whereas */
|
||||
/* MI_INTR_MASK has seperate bits for set/clr */
|
||||
.half CLR_SP | CLR_SI | CLR_AI | CLR_VI | CLR_PI | CLR_DP
|
||||
.half SET_SP | CLR_SI | CLR_AI | CLR_VI | CLR_PI | CLR_DP
|
||||
.half CLR_SP | SET_SI | CLR_AI | CLR_VI | CLR_PI | CLR_DP
|
||||
.half SET_SP | SET_SI | CLR_AI | CLR_VI | CLR_PI | CLR_DP
|
||||
.half CLR_SP | CLR_SI | SET_AI | CLR_VI | CLR_PI | CLR_DP
|
||||
.half SET_SP | CLR_SI | SET_AI | CLR_VI | CLR_PI | CLR_DP
|
||||
.half CLR_SP | SET_SI | SET_AI | CLR_VI | CLR_PI | CLR_DP
|
||||
.half SET_SP | SET_SI | SET_AI | CLR_VI | CLR_PI | CLR_DP
|
||||
.half CLR_SP | CLR_SI | CLR_AI | SET_VI | CLR_PI | CLR_DP
|
||||
.half SET_SP | CLR_SI | CLR_AI | SET_VI | CLR_PI | CLR_DP
|
||||
.half CLR_SP | SET_SI | CLR_AI | SET_VI | CLR_PI | CLR_DP
|
||||
.half SET_SP | SET_SI | CLR_AI | SET_VI | CLR_PI | CLR_DP
|
||||
.half CLR_SP | CLR_SI | SET_AI | SET_VI | CLR_PI | CLR_DP
|
||||
.half SET_SP | CLR_SI | SET_AI | SET_VI | CLR_PI | CLR_DP
|
||||
.half CLR_SP | SET_SI | SET_AI | SET_VI | CLR_PI | CLR_DP
|
||||
.half SET_SP | SET_SI | SET_AI | SET_VI | CLR_PI | CLR_DP
|
||||
.half CLR_SP | CLR_SI | CLR_AI | CLR_VI | SET_PI | CLR_DP
|
||||
.half SET_SP | CLR_SI | CLR_AI | CLR_VI | SET_PI | CLR_DP
|
||||
.half CLR_SP | SET_SI | CLR_AI | CLR_VI | SET_PI | CLR_DP
|
||||
.half SET_SP | SET_SI | CLR_AI | CLR_VI | SET_PI | CLR_DP
|
||||
.half CLR_SP | CLR_SI | SET_AI | CLR_VI | SET_PI | CLR_DP
|
||||
.half SET_SP | CLR_SI | SET_AI | CLR_VI | SET_PI | CLR_DP
|
||||
.half CLR_SP | SET_SI | SET_AI | CLR_VI | SET_PI | CLR_DP
|
||||
.half SET_SP | SET_SI | SET_AI | CLR_VI | SET_PI | CLR_DP
|
||||
.half CLR_SP | CLR_SI | CLR_AI | SET_VI | SET_PI | CLR_DP
|
||||
.half SET_SP | CLR_SI | CLR_AI | SET_VI | SET_PI | CLR_DP
|
||||
.half CLR_SP | SET_SI | CLR_AI | SET_VI | SET_PI | CLR_DP
|
||||
.half SET_SP | SET_SI | CLR_AI | SET_VI | SET_PI | CLR_DP
|
||||
.half CLR_SP | CLR_SI | SET_AI | SET_VI | SET_PI | CLR_DP
|
||||
.half SET_SP | CLR_SI | SET_AI | SET_VI | SET_PI | CLR_DP
|
||||
.half CLR_SP | SET_SI | SET_AI | SET_VI | SET_PI | CLR_DP
|
||||
.half SET_SP | SET_SI | SET_AI | SET_VI | SET_PI | CLR_DP
|
||||
.half CLR_SP | CLR_SI | CLR_AI | CLR_VI | CLR_PI | SET_DP
|
||||
.half SET_SP | CLR_SI | CLR_AI | CLR_VI | CLR_PI | SET_DP
|
||||
.half CLR_SP | SET_SI | CLR_AI | CLR_VI | CLR_PI | SET_DP
|
||||
.half SET_SP | SET_SI | CLR_AI | CLR_VI | CLR_PI | SET_DP
|
||||
.half CLR_SP | CLR_SI | SET_AI | CLR_VI | CLR_PI | SET_DP
|
||||
.half SET_SP | CLR_SI | SET_AI | CLR_VI | CLR_PI | SET_DP
|
||||
.half CLR_SP | SET_SI | SET_AI | CLR_VI | CLR_PI | SET_DP
|
||||
.half SET_SP | SET_SI | SET_AI | CLR_VI | CLR_PI | SET_DP
|
||||
.half CLR_SP | CLR_SI | CLR_AI | SET_VI | CLR_PI | SET_DP
|
||||
.half SET_SP | CLR_SI | CLR_AI | SET_VI | CLR_PI | SET_DP
|
||||
.half CLR_SP | SET_SI | CLR_AI | SET_VI | CLR_PI | SET_DP
|
||||
.half SET_SP | SET_SI | CLR_AI | SET_VI | CLR_PI | SET_DP
|
||||
.half CLR_SP | CLR_SI | SET_AI | SET_VI | CLR_PI | SET_DP
|
||||
.half SET_SP | CLR_SI | SET_AI | SET_VI | CLR_PI | SET_DP
|
||||
.half CLR_SP | SET_SI | SET_AI | SET_VI | CLR_PI | SET_DP
|
||||
.half SET_SP | SET_SI | SET_AI | SET_VI | CLR_PI | SET_DP
|
||||
.half CLR_SP | CLR_SI | CLR_AI | CLR_VI | SET_PI | SET_DP
|
||||
.half SET_SP | CLR_SI | CLR_AI | CLR_VI | SET_PI | SET_DP
|
||||
.half CLR_SP | SET_SI | CLR_AI | CLR_VI | SET_PI | SET_DP
|
||||
.half SET_SP | SET_SI | CLR_AI | CLR_VI | SET_PI | SET_DP
|
||||
.half CLR_SP | CLR_SI | SET_AI | CLR_VI | SET_PI | SET_DP
|
||||
.half SET_SP | CLR_SI | SET_AI | CLR_VI | SET_PI | SET_DP
|
||||
.half CLR_SP | SET_SI | SET_AI | CLR_VI | SET_PI | SET_DP
|
||||
.half SET_SP | SET_SI | SET_AI | CLR_VI | SET_PI | SET_DP
|
||||
.half CLR_SP | CLR_SI | CLR_AI | SET_VI | SET_PI | SET_DP
|
||||
.half SET_SP | CLR_SI | CLR_AI | SET_VI | SET_PI | SET_DP
|
||||
.half CLR_SP | SET_SI | CLR_AI | SET_VI | SET_PI | SET_DP
|
||||
.half SET_SP | SET_SI | CLR_AI | SET_VI | SET_PI | SET_DP
|
||||
.half CLR_SP | CLR_SI | SET_AI | SET_VI | SET_PI | SET_DP
|
||||
.half SET_SP | CLR_SI | SET_AI | SET_VI | SET_PI | SET_DP
|
||||
.half CLR_SP | SET_SI | SET_AI | SET_VI | SET_PI | SET_DP
|
||||
.half SET_SP | SET_SI | SET_AI | SET_VI | SET_PI | SET_DP
|
||||
|
||||
@ -9,18 +9,18 @@
|
||||
glabel osWritebackDCache
|
||||
blez $a1, .osWritebackDCacheReturn
|
||||
nop
|
||||
li $t3, 8192
|
||||
li $t3, DCACHE_SIZE
|
||||
bgeu $a1, $t3, .L80324E40
|
||||
nop
|
||||
move $t0, $a0
|
||||
addu $t1, $a0, $a1
|
||||
bgeu $t0, $t1, .osWritebackDCacheReturn
|
||||
nop
|
||||
andi $t2, $t0, 0xf
|
||||
addiu $t1, $t1, -0x10
|
||||
andi $t2, $t0, DCACHE_LINEMASK
|
||||
addiu $t1, $t1, -DCACHE_LINESIZE
|
||||
subu $t0, $t0, $t2
|
||||
.L80324E28:
|
||||
cache 0x19, ($t0)
|
||||
cache C_HWB|CACH_PD, ($t0)
|
||||
bltu $t0, $t1, .L80324E28
|
||||
addiu $t0, $t0, 0x10
|
||||
.osWritebackDCacheReturn:
|
||||
@ -28,12 +28,12 @@ glabel osWritebackDCache
|
||||
nop
|
||||
|
||||
.L80324E40:
|
||||
lui $t0, 0x8000
|
||||
li $t0, KUSIZE
|
||||
addu $t1, $t0, $t3
|
||||
addiu $t1, $t1, -0x10
|
||||
addiu $t1, $t1, -DCACHE_LINESIZE
|
||||
.L80324E4C:
|
||||
cache 1, ($t0)
|
||||
cache C_IWBINV|CACH_PD, ($t0)
|
||||
bltu $t0, $t1, .L80324E4C
|
||||
addiu $t0, 0x10 # addiu $t0, $t0, 0x10
|
||||
addiu $t0, DCACHE_LINESIZE # addiu $t0, $t0, 0x10
|
||||
jr $ra
|
||||
nop
|
||||
|
||||
@ -9,15 +9,15 @@
|
||||
.section .text, "ax"
|
||||
|
||||
glabel osWritebackDCacheAll
|
||||
/* 0CE490 800CD890 3C088000 */ li $t0, 0x80000000 # $t0, 0x8000
|
||||
/* 0CE494 800CD894 240A2000 */ li $t2, 8192
|
||||
/* 0CE490 800CD890 3C088000 */ li $t0, KUSIZE # $t0, 0x8000
|
||||
/* 0CE494 800CD894 240A2000 */ li $t2, DCACHE_SIZE
|
||||
/* 0CE498 800CD898 010A4821 */ addu $t1, $t0, $t2
|
||||
/* 0CE49C 800CD89C 2529FFF0 */ addiu $t1, $t1, -0x10
|
||||
/* 0CE49C 800CD89C 2529FFF0 */ addiu $t1, $t1, -DCACHE_LINESIZE
|
||||
.L800CD8A0:
|
||||
/* 0CE4A0 800CD8A0 BD010000 */ cache 1, ($t0)
|
||||
/* 0CE4A0 800CD8A0 BD010000 */ cache C_IWBINV | CACH_PD, ($t0)
|
||||
/* 0CE4A4 800CD8A4 0109082B */ sltu $at, $t0, $t1
|
||||
/* 0CE4A8 800CD8A8 1420FFFD */ bnez $at, .L800CD8A0
|
||||
/* 0CE4AC 800CD8AC 25080010 */ addiu $t0, $t0, 0x10
|
||||
/* 0CE4AC 800CD8AC 25080010 */ addiu $t0, $t0, DCACHE_LINESIZE
|
||||
/* 0CE4B0 800CD8B0 03E00008 */ jr $ra
|
||||
/* 0CE4B4 800CD8B4 00000000 */ nop
|
||||
|
||||
|
||||
@ -31,6 +31,13 @@
|
||||
#define NORETURN
|
||||
#endif
|
||||
|
||||
// Avoid undefined behaviour for non-returning functions
|
||||
#ifdef __GNUC__
|
||||
#define NO_REORDER __attribute__((no_reorder))
|
||||
#else
|
||||
#define NO_REORDER
|
||||
#endif
|
||||
|
||||
// Static assertions
|
||||
#ifdef __GNUC__
|
||||
#define STATIC_ASSERT(cond, msg) _Static_assert(cond, msg)
|
||||
|
||||
1227
include/macros.inc
1227
include/macros.inc
File diff suppressed because it is too large
Load Diff
@ -1,15 +1,11 @@
|
||||
#include "libultra_internal.h"
|
||||
|
||||
#ifndef AVOID_UB
|
||||
OSThread *__osThreadTail = NULL;
|
||||
u32 __osTest = -1;
|
||||
OSThread *__osRunQueue = (OSThread *) &__osThreadTail;
|
||||
OSThread *__osActiveQueue = (OSThread *) &__osThreadTail;
|
||||
NO_REORDER OSThread *__osThreadTail = NULL;
|
||||
NO_REORDER u32 __osTest = -1;
|
||||
NO_REORDER OSThread *__osRunQueue = (OSThread *) &__osThreadTail;
|
||||
NO_REORDER OSThread *__osActiveQueue = (OSThread *) &__osThreadTail;
|
||||
OSThread *__osRunningThread = NULL;
|
||||
OSThread *__osFaultedThread = NULL;
|
||||
#else
|
||||
OSThread_ListHead __osThreadTail_fix = {NULL, -1, (OSThread *) &__osThreadTail_fix, (OSThread *) &__osThreadTail_fix, NULL, 0};
|
||||
#endif
|
||||
|
||||
void __osDequeueThread(OSThread **queue, OSThread *thread) {
|
||||
register OSThread **a2;
|
||||
|
||||
@ -10,10 +10,13 @@ typedef struct __OSEventState
|
||||
OSMesg message;
|
||||
} __OSEventState;
|
||||
|
||||
typedef struct __osThreadTail
|
||||
typedef struct // __osThreadTail
|
||||
{
|
||||
OSThread *next;
|
||||
OSPri priority;
|
||||
/* 0x00 */ OSThread *next;
|
||||
/* 0x04 */ OSPri priority;
|
||||
/* 0x08 */ OSThread *queue;
|
||||
/* 0x0c */ OSThread *tlnext;
|
||||
|
||||
} OSThreadTail;
|
||||
|
||||
/*
|
||||
@ -31,23 +34,12 @@ typedef struct
|
||||
/*0x10*/ struct OSThread_s *unk10;
|
||||
/*0x14*/ u32 unk14;
|
||||
} OSThread_ListHead;
|
||||
#ifdef AVOID_UB
|
||||
|
||||
// Now fix the symbols to the new one.
|
||||
extern OSThread_ListHead __osThreadTail_fix;
|
||||
|
||||
#define __osThreadTail __osThreadTail_fix.next
|
||||
#define D_80334894 __osThreadTail_fix.priority
|
||||
#define __osRunQueue __osThreadTail_fix.queue
|
||||
#define __osActiveQueue __osThreadTail_fix.tlnext
|
||||
#define __osRunningThread __osThreadTail_fix.unk10
|
||||
#else
|
||||
// Original OSThread_ListHead definitions
|
||||
extern OSThread *__osThreadTail;
|
||||
extern OSThread *__osActiveQueue;
|
||||
extern OSThread *__osRunQueue;
|
||||
extern OSThread *__osRunningThread;
|
||||
#endif
|
||||
|
||||
// Original EEPROM definitions
|
||||
extern u32 D_80365E00[15];
|
||||
|
||||
@ -14,7 +14,7 @@ typedef struct {
|
||||
u32 D_80194040;
|
||||
|
||||
u64 osClockRate = 62500000;
|
||||
u32 D_800EA5E8 = 0;
|
||||
u32 __osShutdown = 0;
|
||||
u32 __OSGlobalIntMask = OS_IM_ALL;
|
||||
u32 D_800EA5F0 = 0;
|
||||
|
||||
|
||||
@ -16,14 +16,10 @@ extern void __osTimerInterrupt(void);
|
||||
extern u32 __osProbeTLB(void *);
|
||||
extern int __osSpDeviceBusy(void);
|
||||
|
||||
#ifdef AVOID_UB
|
||||
extern OSThread_ListHead __osThreadTail_fix;
|
||||
#else
|
||||
extern OSThread *__osRunningThread;
|
||||
extern OSThread *__osActiveQueue;
|
||||
extern OSThread *__osFaultedThread;
|
||||
extern OSThread *__osRunQueue;
|
||||
#endif
|
||||
|
||||
extern OSTimer *__osTimerList;
|
||||
extern OSTimer __osBaseTimer;
|
||||
|
||||
@ -13,39 +13,6 @@ SP_DMEM = 0xA4000000;
|
||||
SP_DMEM_UNK0 = 0xA40004C0;
|
||||
SP_DMEM_UNK1 = 0xA4000774;
|
||||
SP_IMEM = 0xA4001000;
|
||||
SP_STATUS_REG = 0xA4040010;
|
||||
SP_PC = 0xA4080000;
|
||||
|
||||
/* MI */
|
||||
|
||||
MI_MODE_REG = 0xA4300000;
|
||||
MI_VERSION_REG = 0xA4300004;
|
||||
MI_INTR_REG = 0xA4300008;
|
||||
MI_INTR_MASK_REG = 0xA430000C;
|
||||
|
||||
/* VI */
|
||||
|
||||
VI_CURRENT_REG = 0xA4400010;
|
||||
|
||||
/* AI */
|
||||
|
||||
AI_STATUS_REG = 0xA450000C;
|
||||
|
||||
/* PI */
|
||||
|
||||
PI_DRAM_ADDR_REG = 0xA4600000;
|
||||
PI_CART_ADDR_REG = 0xA4600004;
|
||||
PI_WR_LEN_REG = 0xA460000C;
|
||||
PI_STATUS_REG = 0xA4600010;
|
||||
|
||||
/* RI */
|
||||
|
||||
RI_MODE_REG = 0xA4700000;
|
||||
RI_REFRESH_REG = 0xA4700010;
|
||||
|
||||
/* SI */
|
||||
|
||||
SI_STATUS_REG = 0xA4800018;
|
||||
|
||||
/* Unknown */
|
||||
|
||||
@ -73,41 +40,6 @@ D_05FF8DB8 = 0x05FF8DB8;
|
||||
|
||||
D_0B002A00 = 0x0B002A00;
|
||||
|
||||
D_A4040004 = 0xA4040004;
|
||||
D_A4040008 = 0xA4040008;
|
||||
D_A404000C = 0xA404000C;
|
||||
D_A4040010 = 0xA4040010;
|
||||
D_A4300008 = 0xA4300008;
|
||||
D_A430000C = 0xA430000C;
|
||||
D_A4400004 = 0xA4400004;
|
||||
D_A4400008 = 0xA4400008;
|
||||
D_A440000C = 0xA440000C;
|
||||
D_A4400010 = 0xA4400010;
|
||||
D_A4400014 = 0xA4400014;
|
||||
D_A4400018 = 0xA4400018;
|
||||
D_A440001C = 0xA440001C;
|
||||
D_A4400020 = 0xA4400020;
|
||||
D_A4400024 = 0xA4400024;
|
||||
D_A4400028 = 0xA4400028;
|
||||
D_A440002C = 0xA440002C;
|
||||
D_A4400030 = 0xA4400030;
|
||||
D_A4400034 = 0xA4400034;
|
||||
D_A4500004 = 0xA4500004;
|
||||
D_A4500008 = 0xA4500008;
|
||||
D_A450000C = 0xA450000C;
|
||||
D_A4500010 = 0xA4500010;
|
||||
D_A4500014 = 0xA4500014;
|
||||
D_A4600004 = 0xA4600004;
|
||||
D_A4600008 = 0xA4600008;
|
||||
D_A460000C = 0xA460000C;
|
||||
D_A4600010 = 0xA4600010;
|
||||
D_A4600024 = 0xA4600024;
|
||||
D_A4600028 = 0xA4600028;
|
||||
D_A460002C = 0xA460002C;
|
||||
D_A4600030 = 0xA4600030;
|
||||
D_A4800004 = 0xA4800004;
|
||||
D_A4800010 = 0xA4800010;
|
||||
D_A4800018 = 0xA4800018;
|
||||
D_A5000508 = 0xA5000508;
|
||||
D_A5000510 = 0xA5000510;
|
||||
D_E6FFFFFC = 0xE6FFFFFC;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user