capstone/Makefile

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# Capstone Disassembly Engine
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# By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014
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include config.mk
include pkgconfig.mk # package version
include functions.mk
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# Verbose output?
V ?= 0
OS := $(shell uname)
ifeq ($(OS),Darwin)
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LIBARCHS = x86_64
PREFIX ?= /usr/local
endif
ifeq ($(PKG_EXTRA),)
PKG_VERSION = $(PKG_MAJOR).$(PKG_MINOR)
else
PKG_VERSION = $(PKG_MAJOR).$(PKG_MINOR).$(PKG_EXTRA)
endif
ifeq ($(CROSS),)
RANLIB ?= ranlib
else
CC = $(CROSS)gcc
AR = $(CROSS)ar
RANLIB = $(CROSS)ranlib
STRIP = $(CROSS)strip
endif
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ifneq (,$(findstring yes,$(CAPSTONE_DIET)))
CFLAGS ?= -Os
CFLAGS += -DCAPSTONE_DIET
else
CFLAGS ?= -O3
endif
ifneq (,$(findstring yes,$(CAPSTONE_X86_ATT_DISABLE)))
CFLAGS += -DCAPSTONE_X86_ATT_DISABLE
endif
Constify backend data (#1040) * Constify string literals Use -Wwrite-strings to force string literals to be of type "const char[]", then fix up all warning fallout. * Constify common infrastructure Step one in allowing backend data to be readonly. Minimal changes to backends for now; just set all pointers in common structs that aren't modified to const. * Constify AArch64 backend Section size changes within libcapstone.so are -.rodata 602587 -.data.rel.ro 228416 -.data 1003746 +.rodata 769051 +.data.rel.ro 241120 +.data 824578 * Constify ARM backend Section size changes within libcapstone.so are -.rodata 769051 -.data.rel.ro 241120 -.data 824578 +.rodata 959835 +.data.rel.ro 245120 +.data 629506 * Constify Mips backend Section size changes within libcapstone.so are -.rodata 959835 -.data.rel.ro 245120 -.data 629506 +.rodata 1069851 +.data.rel.ro 256416 +.data 508194 * Constify PowerPC backend Section size changes within libcapstone.so are -.rodata 1069851 -.data.rel.ro 256416 -.data 508194 +.rodata 1142715 +.data.rel.ro 272224 +.data 419490 * Constify Sparc backend Section size changes within libcapstone.so are -.rodata 1142715 -.data.rel.ro 272224 -.data 419490 +.rodata 1175227 +.data.rel.ro 277536 +.data 381666 * Constify SystemZ backend Section size changes within libcapstone.so are -.rodata 1175227 -.data.rel.ro 277536 -.data 381666 +.rodata 1221883 +.data.rel.ro 278016 +.data 334498 * Constify X86 backend Section size changes within libcapstone.so are -.rodata 1221883 -.data.rel.ro 278016 -.data 334498 +.rodata 1533531 +.data.rel.ro 281184 +.data 19714 * Constify XCore backend Section size changes within libcapstone.so are -.rodata 1533531 -.data.rel.ro 281184 -.data 19714 +.rodata 1553026 +.data.rel.ro 281280 +.data 40
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CFLAGS += -fPIC -Wall -Wwrite-strings -Iinclude
ifeq ($(CAPSTONE_USE_SYS_DYN_MEM),yes)
CFLAGS += -DCAPSTONE_USE_SYS_DYN_MEM
endif
ifeq ($(CAPSTONE_HAS_OSXKERNEL), yes)
CFLAGS += -DCAPSTONE_HAS_OSXKERNEL
SDKROOT ?= $(shell xcodebuild -version -sdk macosx Path)
CFLAGS += -mmacosx-version-min=10.5 \
-isysroot$(SDKROOT) \
-I$(SDKROOT)/System/Library/Frameworks/Kernel.framework/Headers \
-mkernel \
-fno-builtin
endif
PREFIX ?= /usr
DESTDIR ?=
ifndef BUILDDIR
BLDIR = .
OBJDIR = .
else
BLDIR = $(abspath $(BUILDDIR))
OBJDIR = $(BLDIR)/obj
endif
INCDIR ?= $(PREFIX)/include
UNAME_S := $(shell uname -s)
LIBDIRARCH ?= lib
# Uncomment the below line to installs x86_64 libs to lib64/ directory.
# Or better, pass 'LIBDIRARCH=lib64' to 'make install/uninstall' via 'make.sh'.
#LIBDIRARCH ?= lib64
LIBDIR = $(DESTDIR)$(PREFIX)/$(LIBDIRARCH)
BINDIR = $(DESTDIR)$(PREFIX)/bin
LIBDATADIR = $(LIBDIR)
# Don't redefine $LIBDATADIR when global environment variable
# USE_GENERIC_LIBDATADIR is set. This is used by the pkgsrc framework.
ifndef USE_GENERIC_LIBDATADIR
ifeq ($(UNAME_S), FreeBSD)
LIBDATADIR = $(PREFIX)/libdata
endif
ifeq ($(UNAME_S), DragonFly)
LIBDATADIR = $(PREFIX)/libdata
endif
endif
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INSTALL_BIN ?= install
INSTALL_DATA ?= $(INSTALL_BIN) -m0644
INSTALL_LIB ?= $(INSTALL_BIN) -m0755
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LIBNAME = capstone
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DEP_ARM =
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DEP_ARM += $(wildcard arch/ARM/ARM*.inc)
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LIBOBJ_ARM =
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ifneq (,$(findstring arm,$(CAPSTONE_ARCHS)))
CFLAGS += -DCAPSTONE_HAS_ARM
LIBSRC_ARM += $(wildcard arch/ARM/ARM*.c)
LIBOBJ_ARM += $(LIBSRC_ARM:%.c=$(OBJDIR)/%.o)
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endif
DEP_ARM64 =
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DEP_ARM64 += $(wildcard arch/AArch64/AArch64*.inc)
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LIBOBJ_ARM64 =
ifneq (,$(findstring aarch64,$(CAPSTONE_ARCHS)))
CFLAGS += -DCAPSTONE_HAS_ARM64
LIBSRC_ARM64 += $(wildcard arch/AArch64/AArch64*.c)
LIBOBJ_ARM64 += $(LIBSRC_ARM64:%.c=$(OBJDIR)/%.o)
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endif
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DEP_M68K =
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DEP_M68K += $(wildcard arch/M68K/M68K*.h)
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LIBOBJ_M68K =
ifneq (,$(findstring m68k,$(CAPSTONE_ARCHS)))
CFLAGS += -DCAPSTONE_HAS_M68K
LIBSRC_M68K += $(wildcard arch/M68K/M68K*.c)
LIBOBJ_M68K += $(LIBSRC_M68K:%.c=$(OBJDIR)/%.o)
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endif
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DEP_MIPS =
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DEP_MIPS += $(wildcard arch/Mips/Mips*.inc)
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LIBOBJ_MIPS =
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ifneq (,$(findstring mips,$(CAPSTONE_ARCHS)))
CFLAGS += -DCAPSTONE_HAS_MIPS
LIBSRC_MIPS += $(wildcard arch/Mips/Mips*.c)
LIBOBJ_MIPS += $(LIBSRC_MIPS:%.c=$(OBJDIR)/%.o)
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endif
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DEP_PPC =
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DEP_PPC += $(wildcard arch/PowerPC/PPC*.inc)
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LIBOBJ_PPC =
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ifneq (,$(findstring powerpc,$(CAPSTONE_ARCHS)))
CFLAGS += -DCAPSTONE_HAS_POWERPC
LIBSRC_PPC += $(wildcard arch/PowerPC/PPC*.c)
LIBOBJ_PPC += $(LIBSRC_PPC:%.c=$(OBJDIR)/%.o)
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endif
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DEP_SPARC =
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DEP_SPARC += $(wildcard arch/Sparc/Sparc*.inc)
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LIBOBJ_SPARC =
ifneq (,$(findstring sparc,$(CAPSTONE_ARCHS)))
CFLAGS += -DCAPSTONE_HAS_SPARC
LIBSRC_SPARC += $(wildcard arch/Sparc/Sparc*.c)
LIBOBJ_SPARC += $(LIBSRC_SPARC:%.c=$(OBJDIR)/%.o)
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endif
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DEP_SYSZ =
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DEP_SYSZ += $(wildcard arch/SystemZ/SystemZ*.inc)
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LIBOBJ_SYSZ =
ifneq (,$(findstring systemz,$(CAPSTONE_ARCHS)))
CFLAGS += -DCAPSTONE_HAS_SYSZ
LIBSRC_SYSZ += $(wildcard arch/SystemZ/SystemZ*.c)
LIBOBJ_SYSZ += $(LIBSRC_SYSZ:%.c=$(OBJDIR)/%.o)
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endif
# by default, we compile full X86 instruction sets
X86_REDUCE =
ifneq (,$(findstring yes,$(CAPSTONE_X86_REDUCE)))
X86_REDUCE = _reduce
CFLAGS += -DCAPSTONE_X86_REDUCE -Os
endif
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DEP_X86 =
DEP_X86 += arch/X86/X86GenAsmWriter$(X86_REDUCE).inc
DEP_X86 += arch/X86/X86GenAsmWriter1$(X86_REDUCE).inc
DEP_X86 += arch/X86/X86GenDisassemblerTables$(X86_REDUCE).inc
DEP_X86 += arch/X86/X86GenInstrInfo$(X86_REDUCE).inc
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DEP_X86 += arch/X86/X86GenRegisterInfo.inc
DEP_X86 += arch/X86/X86MappingInsn$(X86_REDUCE).inc
DEP_X86 += arch/X86/X86MappingInsnOp$(X86_REDUCE).inc
DEP_X86 += arch/X86/X86ImmSize.inc
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LIBOBJ_X86 =
ifneq (,$(findstring x86,$(CAPSTONE_ARCHS)))
CFLAGS += -DCAPSTONE_HAS_X86
LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86DisassemblerDecoder.o
LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86Disassembler.o
LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86IntelInstPrinter.o
# assembly syntax is irrelevant in Diet mode, when this info is suppressed
ifeq (,$(findstring yes,$(CAPSTONE_DIET)))
ifeq (,$(findstring yes,$(CAPSTONE_X86_ATT_DISABLE)))
LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86ATTInstPrinter.o
endif
endif
LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86Mapping.o
LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86Module.o
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endif
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DEP_XCORE =
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DEP_XCORE += $(wildcard arch/XCore/XCore*.inc)
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LIBOBJ_XCORE =
ifneq (,$(findstring xcore,$(CAPSTONE_ARCHS)))
CFLAGS += -DCAPSTONE_HAS_XCORE
LIBSRC_XCORE += $(wildcard arch/XCore/XCore*.c)
LIBOBJ_XCORE += $(LIBSRC_XCORE:%.c=$(OBJDIR)/%.o)
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endif
DEP_TMS320C64X =
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DEP_TMS320C64X += $(wildcard arch/TMS320C64x/TMS320C64x*.inc)
LIBOBJ_TMS320C64X =
ifneq (,$(findstring tms320c64x,$(CAPSTONE_ARCHS)))
CFLAGS += -DCAPSTONE_HAS_TMS320C64X
LIBSRC_TMS320C64X += $(wildcard arch/TMS320C64x/TMS320C64x*.c)
LIBOBJ_TMS320C64X += $(LIBSRC_TMS320C64X:%.c=$(OBJDIR)/%.o)
endif
M680X: Target ready for pull request (#1034) * Added new M680X target. Supports M6800/1/2/3/9, HD6301 * M680X: Reformat for coding guide lines. Set alphabetical order in HACK.TXT * M680X: Prepare for python binding. Move cs_m680x, m680x_insn to m680x_info. Chec > k cpu type, no default. * M680X: Add python bindings. Added python tests. * M680X: Added cpu types to usage message. * cstool: Avoid segfault for invalid <arch+mode>. * Make test_m680x.c/test_m680x.py output comparable (diff params: -bu). Keep xprint.py untouched. * M680X: Update CMake/make for m680x support. Update .gitignore. * M680X: Reduce compiler warnings. * M680X: Reduce compiler warnings. * M680X: Reduce compiler warnings. * M680X: Make test_m680x.c/test_m680x.py output comparable (diff params: -bu). * M680X: Add ocaml bindings and tests. * M680X: Add java bindings and tests. * M680X: Added tests for all indexed addressing modes. C/Python/Ocaml * M680X: Naming, use page1 for PAGE1 instructions (without prefix). * M680X: Naming, use page1 for PAGE1 instructions (without prefix). * M680X: Used M680X_FIRST_OP_IN_MNEM in tests C/python/java/ocaml. * M680X: Added access property to cs_m680x_op. * M680X: Added operand size. * M680X: Remove compiler warnings. * M680X: Added READ/WRITE access property per operator. * M680X: Make reg_inherent_hdlr independent of CPU type. * M680X: Add HD6309 support + bug fixes * M680X: Remove errors and warning. * M680X: Add Bcc/LBcc to group BRAREL (relative branch). * M680X: Add group JUMP to BVS/BVC/LBVS/LBVC. Remove BRAREL from BRN/LBRN. * M680X: Remove LBRN from group BRAREL. * M680X: Refactored cpu_type initialization for better readability. * M680X: Add two operands for insn having two reg. in mnemonic. e.g. ABX. * M680X: Remove typo in cstool.c * M680X: Some format improvements in changed_regs. * M680X: Remove insn id string list from tests (C/python/java/ocaml). * M680X: SEXW, set access of reg. D to WRITE. * M680X: Sort changed_regs in increasing m680x_insn order. * M680X: Add M68HC11 support + Reduced from two to one INDEXED operand. * M680X: cstool, also write '(in mnemonic)' for second reg. operand. * M680X: Add BRN/LBRN to group JUMP and BRAREL. * M680X: For Bcc/LBcc/BRSET/BRCLR set reg. CC to read access. * M680X: Correctly print negative immediate values with option CS_OPT_UNSIGNED. * M680X: Rename some instruction handlers. * M680X: Add M68HC05 support. * M680X: Dont print prefix '<' for direct addr. mode. * M680X: Add M68HC08 support + resorted tables + bug fixes. * M680X: Add Freescale HCS08 support. * M680X: Changed group names, avoid spaces. * M680X: Refactoring, rename addessing mode handlers. * M680X: indexed addr. mode, changed pre/post inc-/decrement representation. * M680X: Rename some M6809/HD6309 specific functions. * M680X: Add CPU12 (68HC12/HCS12) support. * M680X: Correctly display illegal instruction as FCB . * M680X: bugfix: BRA/BRN/BSR/LBRA/LBRN/LBSR does not read CC reg. * M680X: bugfix: Correctly check for sufficient code size for M6809 indexed addressing. * M680X: Better support for changing insn id within handler for addessing mode. * M680X: Remove warnings. * M680X: In set_changed_regs_read_write_counts use own access_mode. * M680X: Split cpu specific tables into separate *.inc files. * M680X: Remove warnings. * M680X: Removed address_mode. Addressing mode is available in operand.type * M680X: Bugfix: BSET/BCLR/BRSET/BRCLR correct read/modify CC reg. * M680X: Remove register TMP1. It is first visible in CPU12X. * M680X: Performance improvement + bug fixes. * M680X: Performance improvement, make cpu_tables const static. * M680X: Simplify operand decoding by using two handlers. * M680X: Replace M680X_OP_INDEX by M680X_OP_CONSTANT + bugfix in java/python/ocaml bindings. * M680X: Format with astyle. * M680X: Update documentation. * M680X: Corrected author for m680x specific files. * M680X: Make max. number of architectures single source.
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DEP_M680X =
DEP_M680X += $(wildcard arch/M680X/*.inc)
DEP_M680X += $(wildcard arch/M680X/M680X*.h)
M680X: Target ready for pull request (#1034) * Added new M680X target. Supports M6800/1/2/3/9, HD6301 * M680X: Reformat for coding guide lines. Set alphabetical order in HACK.TXT * M680X: Prepare for python binding. Move cs_m680x, m680x_insn to m680x_info. Chec > k cpu type, no default. * M680X: Add python bindings. Added python tests. * M680X: Added cpu types to usage message. * cstool: Avoid segfault for invalid <arch+mode>. * Make test_m680x.c/test_m680x.py output comparable (diff params: -bu). Keep xprint.py untouched. * M680X: Update CMake/make for m680x support. Update .gitignore. * M680X: Reduce compiler warnings. * M680X: Reduce compiler warnings. * M680X: Reduce compiler warnings. * M680X: Make test_m680x.c/test_m680x.py output comparable (diff params: -bu). * M680X: Add ocaml bindings and tests. * M680X: Add java bindings and tests. * M680X: Added tests for all indexed addressing modes. C/Python/Ocaml * M680X: Naming, use page1 for PAGE1 instructions (without prefix). * M680X: Naming, use page1 for PAGE1 instructions (without prefix). * M680X: Used M680X_FIRST_OP_IN_MNEM in tests C/python/java/ocaml. * M680X: Added access property to cs_m680x_op. * M680X: Added operand size. * M680X: Remove compiler warnings. * M680X: Added READ/WRITE access property per operator. * M680X: Make reg_inherent_hdlr independent of CPU type. * M680X: Add HD6309 support + bug fixes * M680X: Remove errors and warning. * M680X: Add Bcc/LBcc to group BRAREL (relative branch). * M680X: Add group JUMP to BVS/BVC/LBVS/LBVC. Remove BRAREL from BRN/LBRN. * M680X: Remove LBRN from group BRAREL. * M680X: Refactored cpu_type initialization for better readability. * M680X: Add two operands for insn having two reg. in mnemonic. e.g. ABX. * M680X: Remove typo in cstool.c * M680X: Some format improvements in changed_regs. * M680X: Remove insn id string list from tests (C/python/java/ocaml). * M680X: SEXW, set access of reg. D to WRITE. * M680X: Sort changed_regs in increasing m680x_insn order. * M680X: Add M68HC11 support + Reduced from two to one INDEXED operand. * M680X: cstool, also write '(in mnemonic)' for second reg. operand. * M680X: Add BRN/LBRN to group JUMP and BRAREL. * M680X: For Bcc/LBcc/BRSET/BRCLR set reg. CC to read access. * M680X: Correctly print negative immediate values with option CS_OPT_UNSIGNED. * M680X: Rename some instruction handlers. * M680X: Add M68HC05 support. * M680X: Dont print prefix '<' for direct addr. mode. * M680X: Add M68HC08 support + resorted tables + bug fixes. * M680X: Add Freescale HCS08 support. * M680X: Changed group names, avoid spaces. * M680X: Refactoring, rename addessing mode handlers. * M680X: indexed addr. mode, changed pre/post inc-/decrement representation. * M680X: Rename some M6809/HD6309 specific functions. * M680X: Add CPU12 (68HC12/HCS12) support. * M680X: Correctly display illegal instruction as FCB . * M680X: bugfix: BRA/BRN/BSR/LBRA/LBRN/LBSR does not read CC reg. * M680X: bugfix: Correctly check for sufficient code size for M6809 indexed addressing. * M680X: Better support for changing insn id within handler for addessing mode. * M680X: Remove warnings. * M680X: In set_changed_regs_read_write_counts use own access_mode. * M680X: Split cpu specific tables into separate *.inc files. * M680X: Remove warnings. * M680X: Removed address_mode. Addressing mode is available in operand.type * M680X: Bugfix: BSET/BCLR/BRSET/BRCLR correct read/modify CC reg. * M680X: Remove register TMP1. It is first visible in CPU12X. * M680X: Performance improvement + bug fixes. * M680X: Performance improvement, make cpu_tables const static. * M680X: Simplify operand decoding by using two handlers. * M680X: Replace M680X_OP_INDEX by M680X_OP_CONSTANT + bugfix in java/python/ocaml bindings. * M680X: Format with astyle. * M680X: Update documentation. * M680X: Corrected author for m680x specific files. * M680X: Make max. number of architectures single source.
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LIBOBJ_M680X =
ifneq (,$(findstring m680x,$(CAPSTONE_ARCHS)))
CFLAGS += -DCAPSTONE_HAS_M680X
LIBSRC_M680X += $(wildcard arch/M680X/*.c)
LIBOBJ_M680X += $(LIBSRC_M680X:%.c=$(OBJDIR)/%.o)
M680X: Target ready for pull request (#1034) * Added new M680X target. Supports M6800/1/2/3/9, HD6301 * M680X: Reformat for coding guide lines. Set alphabetical order in HACK.TXT * M680X: Prepare for python binding. Move cs_m680x, m680x_insn to m680x_info. Chec > k cpu type, no default. * M680X: Add python bindings. Added python tests. * M680X: Added cpu types to usage message. * cstool: Avoid segfault for invalid <arch+mode>. * Make test_m680x.c/test_m680x.py output comparable (diff params: -bu). Keep xprint.py untouched. * M680X: Update CMake/make for m680x support. Update .gitignore. * M680X: Reduce compiler warnings. * M680X: Reduce compiler warnings. * M680X: Reduce compiler warnings. * M680X: Make test_m680x.c/test_m680x.py output comparable (diff params: -bu). * M680X: Add ocaml bindings and tests. * M680X: Add java bindings and tests. * M680X: Added tests for all indexed addressing modes. C/Python/Ocaml * M680X: Naming, use page1 for PAGE1 instructions (without prefix). * M680X: Naming, use page1 for PAGE1 instructions (without prefix). * M680X: Used M680X_FIRST_OP_IN_MNEM in tests C/python/java/ocaml. * M680X: Added access property to cs_m680x_op. * M680X: Added operand size. * M680X: Remove compiler warnings. * M680X: Added READ/WRITE access property per operator. * M680X: Make reg_inherent_hdlr independent of CPU type. * M680X: Add HD6309 support + bug fixes * M680X: Remove errors and warning. * M680X: Add Bcc/LBcc to group BRAREL (relative branch). * M680X: Add group JUMP to BVS/BVC/LBVS/LBVC. Remove BRAREL from BRN/LBRN. * M680X: Remove LBRN from group BRAREL. * M680X: Refactored cpu_type initialization for better readability. * M680X: Add two operands for insn having two reg. in mnemonic. e.g. ABX. * M680X: Remove typo in cstool.c * M680X: Some format improvements in changed_regs. * M680X: Remove insn id string list from tests (C/python/java/ocaml). * M680X: SEXW, set access of reg. D to WRITE. * M680X: Sort changed_regs in increasing m680x_insn order. * M680X: Add M68HC11 support + Reduced from two to one INDEXED operand. * M680X: cstool, also write '(in mnemonic)' for second reg. operand. * M680X: Add BRN/LBRN to group JUMP and BRAREL. * M680X: For Bcc/LBcc/BRSET/BRCLR set reg. CC to read access. * M680X: Correctly print negative immediate values with option CS_OPT_UNSIGNED. * M680X: Rename some instruction handlers. * M680X: Add M68HC05 support. * M680X: Dont print prefix '<' for direct addr. mode. * M680X: Add M68HC08 support + resorted tables + bug fixes. * M680X: Add Freescale HCS08 support. * M680X: Changed group names, avoid spaces. * M680X: Refactoring, rename addessing mode handlers. * M680X: indexed addr. mode, changed pre/post inc-/decrement representation. * M680X: Rename some M6809/HD6309 specific functions. * M680X: Add CPU12 (68HC12/HCS12) support. * M680X: Correctly display illegal instruction as FCB . * M680X: bugfix: BRA/BRN/BSR/LBRA/LBRN/LBSR does not read CC reg. * M680X: bugfix: Correctly check for sufficient code size for M6809 indexed addressing. * M680X: Better support for changing insn id within handler for addessing mode. * M680X: Remove warnings. * M680X: In set_changed_regs_read_write_counts use own access_mode. * M680X: Split cpu specific tables into separate *.inc files. * M680X: Remove warnings. * M680X: Removed address_mode. Addressing mode is available in operand.type * M680X: Bugfix: BSET/BCLR/BRSET/BRCLR correct read/modify CC reg. * M680X: Remove register TMP1. It is first visible in CPU12X. * M680X: Performance improvement + bug fixes. * M680X: Performance improvement, make cpu_tables const static. * M680X: Simplify operand decoding by using two handlers. * M680X: Replace M680X_OP_INDEX by M680X_OP_CONSTANT + bugfix in java/python/ocaml bindings. * M680X: Format with astyle. * M680X: Update documentation. * M680X: Corrected author for m680x specific files. * M680X: Make max. number of architectures single source.
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endif
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DEP_EVM =
DEP_EVM += $(wildcard arch/EVM/EVM*.inc)
LIBOBJ_EVM =
ifneq (,$(findstring evm,$(CAPSTONE_ARCHS)))
CFLAGS += -DCAPSTONE_HAS_EVM
LIBSRC_EVM += $(wildcard arch/EVM/EVM*.c)
LIBOBJ_EVM += $(LIBSRC_EVM:%.c=$(OBJDIR)/%.o)
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endif
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LIBOBJ =
LIBOBJ += $(OBJDIR)/cs.o $(OBJDIR)/utils.o $(OBJDIR)/SStream.o $(OBJDIR)/MCInstrDesc.o $(OBJDIR)/MCRegisterInfo.o
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LIBOBJ += $(LIBOBJ_ARM) $(LIBOBJ_ARM64) $(LIBOBJ_M68K) $(LIBOBJ_MIPS) $(LIBOBJ_PPC) $(LIBOBJ_SPARC) $(LIBOBJ_SYSZ) $(LIBOBJ_X86) $(LIBOBJ_XCORE) $(LIBOBJ_TMS320C64X) $(LIBOBJ_M680X) $(LIBOBJ_EVM)
LIBOBJ += $(OBJDIR)/MCInst.o
2013-11-27 04:11:31 +00:00
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ifeq ($(PKG_EXTRA),)
PKGCFGDIR = $(LIBDATADIR)/pkgconfig
else
PKGCFGDIR ?= $(LIBDATADIR)/pkgconfig
ifeq ($(PKGCFGDIR),)
PKGCFGDIR = $(LIBDATADIR)/pkgconfig
endif
endif
API_MAJOR=$(shell echo `grep -e CS_API_MAJOR include/capstone/capstone.h | grep -v = | awk '{print $$3}'` | awk '{print $$1}')
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VERSION_EXT =
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IS_APPLE := $(shell $(CC) -dM -E - < /dev/null 2> /dev/null | grep __apple_build_version__ | wc -l | tr -d " ")
ifeq ($(IS_APPLE),1)
# on MacOS, do not build in Universal format by default
MACOS_UNIVERSAL ?= no
ifeq ($(MACOS_UNIVERSAL),yes)
CFLAGS += $(foreach arch,$(LIBARCHS),-arch $(arch))
LDFLAGS += $(foreach arch,$(LIBARCHS),-arch $(arch))
endif
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EXT = dylib
VERSION_EXT = $(API_MAJOR).$(EXT)
$(LIBNAME)_LDFLAGS += -dynamiclib -install_name lib$(LIBNAME).$(VERSION_EXT) -current_version $(PKG_MAJOR).$(PKG_MINOR).$(PKG_EXTRA) -compatibility_version $(PKG_MAJOR).$(PKG_MINOR)
AR_EXT = a
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# Homebrew wants to make sure its formula does not disable FORTIFY_SOURCE
# However, this is not really necessary because 'CAPSTONE_USE_SYS_DYN_MEM=yes' by default
ifneq ($(HOMEBREW_CAPSTONE),1)
ifneq ($(CAPSTONE_USE_SYS_DYN_MEM),yes)
# remove string check because OSX kernel complains about missing symbols
CFLAGS += -D_FORTIFY_SOURCE=0
endif
endif
else
CFLAGS += $(foreach arch,$(LIBARCHS),-arch $(arch))
LDFLAGS += $(foreach arch,$(LIBARCHS),-arch $(arch))
$(LIBNAME)_LDFLAGS += -shared
# Cygwin?
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IS_CYGWIN := $(shell $(CC) -dumpmachine 2>/dev/null | grep -i cygwin | wc -l)
ifeq ($(IS_CYGWIN),1)
EXT = dll
AR_EXT = lib
# Cygwin doesn't like -fPIC
CFLAGS := $(CFLAGS:-fPIC=)
# On Windows we need the shared library to be executable
else
# mingw?
IS_MINGW := $(shell $(CC) --version 2>/dev/null | grep -i "\(mingw\|MSYS\)" | wc -l)
ifeq ($(IS_MINGW),1)
EXT = dll
AR_EXT = lib
# mingw doesn't like -fPIC either
CFLAGS := $(CFLAGS:-fPIC=)
# On Windows we need the shared library to be executable
else
# Linux, *BSD
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EXT = so
VERSION_EXT = $(EXT).$(API_MAJOR)
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AR_EXT = a
$(LIBNAME)_LDFLAGS += -Wl,-soname,lib$(LIBNAME).$(VERSION_EXT)
endif
endif
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endif
ifeq ($(CAPSTONE_SHARED),yes)
ifeq ($(IS_MINGW),1)
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LIBRARY = $(BLDIR)/$(LIBNAME).$(VERSION_EXT)
else ifeq ($(IS_CYGWIN),1)
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LIBRARY = $(BLDIR)/$(LIBNAME).$(VERSION_EXT)
else # *nix
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LIBRARY = $(BLDIR)/lib$(LIBNAME).$(VERSION_EXT)
CFLAGS += -fvisibility=hidden
endif
endif
ifeq ($(CAPSTONE_STATIC),yes)
ifeq ($(IS_MINGW),1)
ARCHIVE = $(BLDIR)/$(LIBNAME).$(AR_EXT)
else ifeq ($(IS_CYGWIN),1)
ARCHIVE = $(BLDIR)/$(LIBNAME).$(AR_EXT)
else
ARCHIVE = $(BLDIR)/lib$(LIBNAME).$(AR_EXT)
endif
endif
PKGCFGF = $(BLDIR)/$(LIBNAME).pc
.PHONY: all clean install uninstall dist
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all: $(LIBRARY) $(ARCHIVE) $(PKGCFGF)
ifeq (,$(findstring yes,$(CAPSTONE_BUILD_CORE_ONLY)))
@V=$(V) CC=$(CC) $(MAKE) -C cstool
ifndef BUILDDIR
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$(MAKE) -C tests
$(MAKE) -C suite/fuzz
else
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$(MAKE) -C tests BUILDDIR=$(BLDIR)
$(MAKE) -C suite/fuzz BUILDDIR=$(BLDIR)
endif
$(call install-library,$(BLDIR)/tests/)
endif
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ifeq ($(CAPSTONE_SHARED),yes)
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$(LIBRARY): $(LIBOBJ)
ifeq ($(V),0)
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$(call log,LINK,$(@:$(BLDIR)/%=%))
@$(create-library)
else
$(create-library)
endif
endif
$(LIBOBJ): config.mk *.h include/capstone/*.h
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$(LIBOBJ_ARM): $(DEP_ARM)
$(LIBOBJ_ARM64): $(DEP_ARM64)
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$(LIBOBJ_M68K): $(DEP_M68K)
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$(LIBOBJ_MIPS): $(DEP_MIPS)
$(LIBOBJ_PPC): $(DEP_PPC)
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$(LIBOBJ_SPARC): $(DEP_SPARC)
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$(LIBOBJ_SYSZ): $(DEP_SYSZ)
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$(LIBOBJ_X86): $(DEP_X86)
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$(LIBOBJ_XCORE): $(DEP_XCORE)
$(LIBOBJ_TMS320C64X): $(DEP_TMS320C64X)
M680X: Target ready for pull request (#1034) * Added new M680X target. Supports M6800/1/2/3/9, HD6301 * M680X: Reformat for coding guide lines. Set alphabetical order in HACK.TXT * M680X: Prepare for python binding. Move cs_m680x, m680x_insn to m680x_info. Chec > k cpu type, no default. * M680X: Add python bindings. Added python tests. * M680X: Added cpu types to usage message. * cstool: Avoid segfault for invalid <arch+mode>. * Make test_m680x.c/test_m680x.py output comparable (diff params: -bu). Keep xprint.py untouched. * M680X: Update CMake/make for m680x support. Update .gitignore. * M680X: Reduce compiler warnings. * M680X: Reduce compiler warnings. * M680X: Reduce compiler warnings. * M680X: Make test_m680x.c/test_m680x.py output comparable (diff params: -bu). * M680X: Add ocaml bindings and tests. * M680X: Add java bindings and tests. * M680X: Added tests for all indexed addressing modes. C/Python/Ocaml * M680X: Naming, use page1 for PAGE1 instructions (without prefix). * M680X: Naming, use page1 for PAGE1 instructions (without prefix). * M680X: Used M680X_FIRST_OP_IN_MNEM in tests C/python/java/ocaml. * M680X: Added access property to cs_m680x_op. * M680X: Added operand size. * M680X: Remove compiler warnings. * M680X: Added READ/WRITE access property per operator. * M680X: Make reg_inherent_hdlr independent of CPU type. * M680X: Add HD6309 support + bug fixes * M680X: Remove errors and warning. * M680X: Add Bcc/LBcc to group BRAREL (relative branch). * M680X: Add group JUMP to BVS/BVC/LBVS/LBVC. Remove BRAREL from BRN/LBRN. * M680X: Remove LBRN from group BRAREL. * M680X: Refactored cpu_type initialization for better readability. * M680X: Add two operands for insn having two reg. in mnemonic. e.g. ABX. * M680X: Remove typo in cstool.c * M680X: Some format improvements in changed_regs. * M680X: Remove insn id string list from tests (C/python/java/ocaml). * M680X: SEXW, set access of reg. D to WRITE. * M680X: Sort changed_regs in increasing m680x_insn order. * M680X: Add M68HC11 support + Reduced from two to one INDEXED operand. * M680X: cstool, also write '(in mnemonic)' for second reg. operand. * M680X: Add BRN/LBRN to group JUMP and BRAREL. * M680X: For Bcc/LBcc/BRSET/BRCLR set reg. CC to read access. * M680X: Correctly print negative immediate values with option CS_OPT_UNSIGNED. * M680X: Rename some instruction handlers. * M680X: Add M68HC05 support. * M680X: Dont print prefix '<' for direct addr. mode. * M680X: Add M68HC08 support + resorted tables + bug fixes. * M680X: Add Freescale HCS08 support. * M680X: Changed group names, avoid spaces. * M680X: Refactoring, rename addessing mode handlers. * M680X: indexed addr. mode, changed pre/post inc-/decrement representation. * M680X: Rename some M6809/HD6309 specific functions. * M680X: Add CPU12 (68HC12/HCS12) support. * M680X: Correctly display illegal instruction as FCB . * M680X: bugfix: BRA/BRN/BSR/LBRA/LBRN/LBSR does not read CC reg. * M680X: bugfix: Correctly check for sufficient code size for M6809 indexed addressing. * M680X: Better support for changing insn id within handler for addessing mode. * M680X: Remove warnings. * M680X: In set_changed_regs_read_write_counts use own access_mode. * M680X: Split cpu specific tables into separate *.inc files. * M680X: Remove warnings. * M680X: Removed address_mode. Addressing mode is available in operand.type * M680X: Bugfix: BSET/BCLR/BRSET/BRCLR correct read/modify CC reg. * M680X: Remove register TMP1. It is first visible in CPU12X. * M680X: Performance improvement + bug fixes. * M680X: Performance improvement, make cpu_tables const static. * M680X: Simplify operand decoding by using two handlers. * M680X: Replace M680X_OP_INDEX by M680X_OP_CONSTANT + bugfix in java/python/ocaml bindings. * M680X: Format with astyle. * M680X: Update documentation. * M680X: Corrected author for m680x specific files. * M680X: Make max. number of architectures single source.
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$(LIBOBJ_M680X): $(DEP_M680X)
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$(LIBOBJ_EVM): $(DEP_EVM)
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ifeq ($(CAPSTONE_STATIC),yes)
$(ARCHIVE): $(LIBOBJ)
@rm -f $(ARCHIVE)
ifeq ($(V),0)
$(call log,AR,$(@:$(BLDIR)/%=%))
@$(create-archive)
else
$(create-archive)
endif
endif
$(PKGCFGF):
ifeq ($(V),0)
$(call log,GEN,$(@:$(BLDIR)/%=%))
@$(generate-pkgcfg)
else
$(generate-pkgcfg)
endif
install: $(PKGCFGF) $(ARCHIVE) $(LIBRARY)
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mkdir -p $(LIBDIR)
$(call install-library,$(LIBDIR))
ifeq ($(CAPSTONE_STATIC),yes)
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$(INSTALL_DATA) $(ARCHIVE) $(LIBDIR)
endif
mkdir -p $(DESTDIR)$(INCDIR)/$(LIBNAME)
$(INSTALL_DATA) include/capstone/*.h $(DESTDIR)$(INCDIR)/$(LIBNAME)
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mkdir -p $(PKGCFGDIR)
$(INSTALL_DATA) $(PKGCFGF) $(PKGCFGDIR)
mkdir -p $(BINDIR)
$(INSTALL_LIB) cstool/cstool $(BINDIR)
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uninstall:
rm -rf $(DESTDIR)$(INCDIR)/$(LIBNAME)
rm -f $(DESTDIR)$(LIBDIR)/lib$(LIBNAME).*
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rm -f $(PKGCFGDIR)/$(LIBNAME).pc
rm -f $(DESTDIR)$(BINDIR)/cstool
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clean:
rm -f $(LIBOBJ)
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rm -f $(BLDIR)/lib$(LIBNAME).* $(BLDIR)/$(LIBNAME).pc
rm -f $(PKGCFGF)
$(MAKE) -C cstool clean
ifeq (,$(findstring yes,$(CAPSTONE_BUILD_CORE_ONLY)))
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$(MAKE) -C tests clean
$(MAKE) -C suite/fuzz clean
rm -f $(BLDIR)/tests/lib$(LIBNAME).$(EXT)
endif
ifdef BUILDDIR
rm -rf $(BUILDDIR)
endif
ifeq (,$(findstring yes,$(CAPSTONE_BUILD_CORE_ONLY)))
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$(MAKE) -C bindings/python clean
$(MAKE) -C bindings/java clean
$(MAKE) -C bindings/ocaml clean
endif
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TAG ?= HEAD
ifeq ($(TAG), HEAD)
DIST_VERSION = latest
else
DIST_VERSION = $(TAG)
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endif
dist:
git archive --format=tar.gz --prefix=capstone-$(DIST_VERSION)/ $(TAG) > capstone-$(DIST_VERSION).tgz
git archive --format=zip --prefix=capstone-$(DIST_VERSION)/ $(TAG) > capstone-$(DIST_VERSION).zip
2014-01-18 02:42:15 +00:00
2014-10-01 08:42:29 +00:00
TESTS = test_basic test_detail test_arm test_arm64 test_m68k test_mips test_ppc test_sparc
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TESTS += test_systemz test_x86 test_xcore test_iter test_evm
TESTS += test_basic.static test_detail.static test_arm.static test_arm64.static
2015-08-03 16:45:08 +00:00
TESTS += test_m68k.static test_mips.static test_ppc.static test_sparc.static
M680X: Target ready for pull request (#1034) * Added new M680X target. Supports M6800/1/2/3/9, HD6301 * M680X: Reformat for coding guide lines. Set alphabetical order in HACK.TXT * M680X: Prepare for python binding. Move cs_m680x, m680x_insn to m680x_info. Chec > k cpu type, no default. * M680X: Add python bindings. Added python tests. * M680X: Added cpu types to usage message. * cstool: Avoid segfault for invalid <arch+mode>. * Make test_m680x.c/test_m680x.py output comparable (diff params: -bu). Keep xprint.py untouched. * M680X: Update CMake/make for m680x support. Update .gitignore. * M680X: Reduce compiler warnings. * M680X: Reduce compiler warnings. * M680X: Reduce compiler warnings. * M680X: Make test_m680x.c/test_m680x.py output comparable (diff params: -bu). * M680X: Add ocaml bindings and tests. * M680X: Add java bindings and tests. * M680X: Added tests for all indexed addressing modes. C/Python/Ocaml * M680X: Naming, use page1 for PAGE1 instructions (without prefix). * M680X: Naming, use page1 for PAGE1 instructions (without prefix). * M680X: Used M680X_FIRST_OP_IN_MNEM in tests C/python/java/ocaml. * M680X: Added access property to cs_m680x_op. * M680X: Added operand size. * M680X: Remove compiler warnings. * M680X: Added READ/WRITE access property per operator. * M680X: Make reg_inherent_hdlr independent of CPU type. * M680X: Add HD6309 support + bug fixes * M680X: Remove errors and warning. * M680X: Add Bcc/LBcc to group BRAREL (relative branch). * M680X: Add group JUMP to BVS/BVC/LBVS/LBVC. Remove BRAREL from BRN/LBRN. * M680X: Remove LBRN from group BRAREL. * M680X: Refactored cpu_type initialization for better readability. * M680X: Add two operands for insn having two reg. in mnemonic. e.g. ABX. * M680X: Remove typo in cstool.c * M680X: Some format improvements in changed_regs. * M680X: Remove insn id string list from tests (C/python/java/ocaml). * M680X: SEXW, set access of reg. D to WRITE. * M680X: Sort changed_regs in increasing m680x_insn order. * M680X: Add M68HC11 support + Reduced from two to one INDEXED operand. * M680X: cstool, also write '(in mnemonic)' for second reg. operand. * M680X: Add BRN/LBRN to group JUMP and BRAREL. * M680X: For Bcc/LBcc/BRSET/BRCLR set reg. CC to read access. * M680X: Correctly print negative immediate values with option CS_OPT_UNSIGNED. * M680X: Rename some instruction handlers. * M680X: Add M68HC05 support. * M680X: Dont print prefix '<' for direct addr. mode. * M680X: Add M68HC08 support + resorted tables + bug fixes. * M680X: Add Freescale HCS08 support. * M680X: Changed group names, avoid spaces. * M680X: Refactoring, rename addessing mode handlers. * M680X: indexed addr. mode, changed pre/post inc-/decrement representation. * M680X: Rename some M6809/HD6309 specific functions. * M680X: Add CPU12 (68HC12/HCS12) support. * M680X: Correctly display illegal instruction as FCB . * M680X: bugfix: BRA/BRN/BSR/LBRA/LBRN/LBSR does not read CC reg. * M680X: bugfix: Correctly check for sufficient code size for M6809 indexed addressing. * M680X: Better support for changing insn id within handler for addessing mode. * M680X: Remove warnings. * M680X: In set_changed_regs_read_write_counts use own access_mode. * M680X: Split cpu specific tables into separate *.inc files. * M680X: Remove warnings. * M680X: Removed address_mode. Addressing mode is available in operand.type * M680X: Bugfix: BSET/BCLR/BRSET/BRCLR correct read/modify CC reg. * M680X: Remove register TMP1. It is first visible in CPU12X. * M680X: Performance improvement + bug fixes. * M680X: Performance improvement, make cpu_tables const static. * M680X: Simplify operand decoding by using two handlers. * M680X: Replace M680X_OP_INDEX by M680X_OP_CONSTANT + bugfix in java/python/ocaml bindings. * M680X: Format with astyle. * M680X: Update documentation. * M680X: Corrected author for m680x specific files. * M680X: Make max. number of architectures single source.
2017-10-21 13:44:36 +00:00
TESTS += test_systemz.static test_x86.static test_xcore.static test_m680x.static
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TESTS += test_skipdata test_skipdata.static test_iter.static test_evm.static
check: $(TESTS) fuzztest fuzzallcorp
test_%:
./tests/$@ > /dev/null && echo OK || echo FAILED
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FUZZ_INPUTS = $(shell find suite/MC -type f -name '*.cs')
fuzztest:
./suite/fuzz/fuzz_disasm $(FUZZ_INPUTS)
fuzzallcorp:
./suite/fuzz/fuzz_bindisasm suite/fuzz/corpus-libFuzzer-capstone_fuzz_disasmnext-latest/
$(OBJDIR)/%.o: %.c
@mkdir -p $(@D)
ifeq ($(V),0)
$(call log,CC,$(@:$(OBJDIR)/%=%))
@$(compile)
else
$(compile)
endif
ifeq ($(CAPSTONE_SHARED),yes)
define install-library
$(INSTALL_LIB) $(LIBRARY) $1
$(if $(VERSION_EXT),
cd $1 && \
rm -f lib$(LIBNAME).$(EXT) && \
ln -s lib$(LIBNAME).$(VERSION_EXT) lib$(LIBNAME).$(EXT))
endef
else
define install-library
endef
endif
define create-archive
$(AR) q $(ARCHIVE) $(LIBOBJ)
$(RANLIB) $(ARCHIVE)
endef
define create-library
$(CC) $(LDFLAGS) $($(LIBNAME)_LDFLAGS) $(LIBOBJ) -o $(LIBRARY)
endef
define generate-pkgcfg
mkdir -p $(BLDIR)
echo 'Name: capstone' > $(PKGCFGF)
echo 'Description: Capstone disassembly engine' >> $(PKGCFGF)
echo 'Version: $(PKG_VERSION)' >> $(PKGCFGF)
echo 'libdir=$(LIBDIR)' >> $(PKGCFGF)
echo 'includedir=$(INCDIR)' >> $(PKGCFGF)
echo 'archive=$${libdir}/libcapstone.a' >> $(PKGCFGF)
echo 'Libs: -L$${libdir} -lcapstone' >> $(PKGCFGF)
echo 'Cflags: -I$${includedir}' >> $(PKGCFGF)
endef