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Merge pull request #1859 from adamjseitz/aarch64-sys-instruction-operands

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AArch64 SYS instruction operands
This commit is contained in:
Wu ChenXu 2022-03-22 22:56:27 +08:00 committed by GitHub
commit 065317746d
8 changed files with 187 additions and 64 deletions
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3
arch/AArch64/AArch64InstPrinter.c
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@ -814,6 +814,9 @@ static bool printSysAlias(MCInst *MI, SStream *O)
MI->ac_idx++;
#endif
#endif
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_SYS;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].sys = AArch64_map_sys_op(Name);
MI->flat_insn->detail->arm64.op_count++;
if (NeedsReg) {
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;

116
arch/AArch64/AArch64Mapping.c
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@ -491,6 +491,122 @@ arm64_reg AArch64_map_vregister(unsigned int r)
return 0;
}
static const name_map sys_op_name_map[] = {
{ ARM64_TLBI_IPAS2E1IS, "ipas2e1is" },
{ ARM64_TLBI_IPAS2LE1IS, "ipas2le1is" },
{ ARM64_TLBI_VMALLE1IS, "vmalle1is" },
{ ARM64_TLBI_ALLE2IS, "alle2is" },
{ ARM64_TLBI_ALLE3IS, "alle3is" },
{ ARM64_TLBI_VAE1IS, "vae1is" },
{ ARM64_TLBI_VAE2IS, "vae2is" },
{ ARM64_TLBI_VAE3IS, "vae3is" },
{ ARM64_TLBI_ASIDE1IS, "aside1is" },
{ ARM64_TLBI_VAAE1IS, "vaae1is" },
{ ARM64_TLBI_ALLE1IS, "alle1is" },
{ ARM64_TLBI_VALE1IS, "vale1is" },
{ ARM64_TLBI_VALE2IS, "vale2is" },
{ ARM64_TLBI_VALE3IS, "vale3is" },
{ ARM64_TLBI_VMALLS12E1IS, "vmalls12e1is" },
{ ARM64_TLBI_VAALE1IS, "vaale1is" },
{ ARM64_TLBI_IPAS2E1, "ipas2e1" },
{ ARM64_TLBI_IPAS2LE1, "ipas2le1" },
{ ARM64_TLBI_VMALLE1, "vmalle1" },
{ ARM64_TLBI_ALLE2, "alle2" },
{ ARM64_TLBI_ALLE3, "alle3" },
{ ARM64_TLBI_VAE1, "vae1" },
{ ARM64_TLBI_VAE2, "vae2" },
{ ARM64_TLBI_VAE3, "vae3" },
{ ARM64_TLBI_ASIDE1, "aside1" },
{ ARM64_TLBI_VAAE1, "vaae1" },
{ ARM64_TLBI_ALLE1, "alle1" },
{ ARM64_TLBI_VALE1, "vale1" },
{ ARM64_TLBI_VALE2, "vale2" },
{ ARM64_TLBI_VALE3, "vale3" },
{ ARM64_TLBI_VMALLS12E1, "vmalls12e1" },
{ ARM64_TLBI_VAALE1, "vaale1" },
{ ARM64_TLBI_VMALLE1OS, "vmalle1os" },
{ ARM64_TLBI_VAE1OS, "vae1os" },
{ ARM64_TLBI_ASIDE1OS, "aside1os" },
{ ARM64_TLBI_VAAE1OS, "vaae1os" },
{ ARM64_TLBI_VALE1OS, "vale1os" },
{ ARM64_TLBI_VAALE1OS, "vaale1os" },
{ ARM64_TLBI_IPAS2E1OS, "ipas2e1os" },
{ ARM64_TLBI_IPAS2LE1OS, "ipas2le1os" },
{ ARM64_TLBI_VAE2OS, "vae2os" },
{ ARM64_TLBI_VALE2OS, "vale2os" },
{ ARM64_TLBI_VMALLS12E1OS, "vmalls12e1os" },
{ ARM64_TLBI_VAE3OS, "vae3os" },
{ ARM64_TLBI_VALE3OS, "vale3os" },
{ ARM64_TLBI_ALLE2OS, "alle2os" },
{ ARM64_TLBI_ALLE1OS, "alle1os" },
{ ARM64_TLBI_ALLE3OS, "alle3os" },
{ ARM64_TLBI_RVAE1, "rvae1" },
{ ARM64_TLBI_RVAAE1, "rvaae1" },
{ ARM64_TLBI_RVALE1, "rvale1" },
{ ARM64_TLBI_RVAALE1, "rvaale1" },
{ ARM64_TLBI_RVAE1IS, "rvae1is" },
{ ARM64_TLBI_RVAAE1IS, "rvaae1is" },
{ ARM64_TLBI_RVALE1IS, "rvale1is" },
{ ARM64_TLBI_RVAALE1IS, "rvaale1is" },
{ ARM64_TLBI_RVAE1OS, "rvae1os" },
{ ARM64_TLBI_RVAAE1OS, "rvaae1os" },
{ ARM64_TLBI_RVALE1OS, "rvale1os" },
{ ARM64_TLBI_RVAALE1OS, "rvaale1os" },
{ ARM64_TLBI_RIPAS2E1IS, "ripas2e1is" },
{ ARM64_TLBI_RIPAS2LE1IS, "ripas2le1is" },
{ ARM64_TLBI_RIPAS2E1, "ripas2e1" },
{ ARM64_TLBI_RIPAS2LE1, "ripas2le1" },
{ ARM64_TLBI_RIPAS2E1OS, "ripas2e1os" },
{ ARM64_TLBI_RIPAS2LE1OS, "ripas2le1os" },
{ ARM64_TLBI_RVAE2, "rvae2" },
{ ARM64_TLBI_RVALE2, "rvale2" },
{ ARM64_TLBI_RVAE2IS, "rvae2is" },
{ ARM64_TLBI_RVALE2IS, "rvale2is" },
{ ARM64_TLBI_RVAE2OS, "rvae2os" },
{ ARM64_TLBI_RVALE2OS, "rvale2os" },
{ ARM64_TLBI_RVAE3, "rvae3" },
{ ARM64_TLBI_RVALE3, "rvale3" },
{ ARM64_TLBI_RVAE3IS, "rvae3is" },
{ ARM64_TLBI_RVALE3IS, "rvale3is" },
{ ARM64_TLBI_RVAE3OS, "rvae3os" },
{ ARM64_TLBI_RVALE3OS, "rvale3os" },
{ ARM64_AT_S1E1R, "s1e1r" },
{ ARM64_AT_S1E2R, "s1e2r" },
{ ARM64_AT_S1E3R, "s1e3r" },
{ ARM64_AT_S1E1W, "s1e1w" },
{ ARM64_AT_S1E2W, "s1e2w" },
{ ARM64_AT_S1E3W, "s1e3w" },
{ ARM64_AT_S1E0R, "s1e0r" },
{ ARM64_AT_S1E0W, "s1e0w" },
{ ARM64_AT_S12E1R, "s12e1r" },
{ ARM64_AT_S12E1W, "s12e1w" },
{ ARM64_AT_S12E0R, "s12e0r" },
{ ARM64_AT_S12E0W, "s12e0w" },
{ ARM64_AT_S1E1RP, "s1e1rp" },
{ ARM64_AT_S1E1WP, "s1e1wp" },
{ ARM64_DC_ZVA, "zva" },
{ ARM64_DC_IVAC, "ivac" },
{ ARM64_DC_ISW, "isw" },
{ ARM64_DC_CVAC, "cvac" },
{ ARM64_DC_CSW, "csw" },
{ ARM64_DC_CVAU, "cvau" },
{ ARM64_DC_CIVAC, "civac" },
{ ARM64_DC_CISW, "cisw" },
{ ARM64_DC_CVAP, "cvap" },
{ ARM64_IC_IALLUIS, "ialluis" },
{ ARM64_IC_IALLU, "iallu" },
{ ARM64_IC_IVAU, "ivau" },
};
arm64_sys_op AArch64_map_sys_op(const char *name)
{
int result = name2id(sys_op_name_map, ARR_SIZE(sys_op_name_map), name);
if (result == -1) {
return ARM64_SYS_INVALID;
}
return result;
}
void arm64_op_addVectorArrSpecifier(MCInst * MI, int sp)
{
if (MI->csh->detail) {

2
arch/AArch64/AArch64Mapping.h
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@ -24,6 +24,8 @@ arm64_insn AArch64_map_insn(const char *name);
// map internal vregister to public register
arm64_reg AArch64_map_vregister(unsigned int r);
arm64_sys_op AArch64_map_sys_op(const char *name);
void arm64_op_addReg(MCInst *MI, int reg);
void arm64_op_addVectorArrSpecifier(MCInst * MI, int sp);

28
bindings/java/capstone/Arm64_const.java
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@ -921,22 +921,18 @@ public class Arm64_const {
public static final int ARM64_AT_S12E0W = 90;
public static final int ARM64_AT_S1E1RP = 91;
public static final int ARM64_AT_S1E1WP = 92;
public static final int ARM64_DC_INVALID = 0;
public static final int ARM64_DC_ZVA = 1;
public static final int ARM64_DC_IVAC = 2;
public static final int ARM64_DC_ISW = 3;
public static final int ARM64_DC_CVAC = 4;
public static final int ARM64_DC_CSW = 5;
public static final int ARM64_DC_CVAU = 6;
public static final int ARM64_DC_CIVAC = 7;
public static final int ARM64_DC_CISW = 8;
public static final int ARM64_DC_CVAP = 9;
public static final int ARM64_IC_INVALID = 0;
public static final int ARM64_IC_IALLUIS = 1;
public static final int ARM64_IC_IALLU = 2;
public static final int ARM64_IC_IVAU = 3;
public static final int ARM64_DC_ZVA = 93;
public static final int ARM64_DC_IVAC = 94;
public static final int ARM64_DC_ISW = 95;
public static final int ARM64_DC_CVAC = 96;
public static final int ARM64_DC_CSW = 97;
public static final int ARM64_DC_CVAU = 98;
public static final int ARM64_DC_CIVAC = 99;
public static final int ARM64_DC_CISW = 100;
public static final int ARM64_DC_CVAP = 101;
public static final int ARM64_IC_IALLUIS = 102;
public static final int ARM64_IC_IALLU = 103;
public static final int ARM64_IC_IVAU = 104;
public static final int ARM64_PRFM_INVALID = 0;
public static final int ARM64_PRFM_PLDL1KEEP = 0x00+1;

29
bindings/ocaml/arm64_const.ml
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@ -918,22 +918,19 @@ let _ARM64_AT_S12E0R = 89;;
let _ARM64_AT_S12E0W = 90;;
let _ARM64_AT_S1E1RP = 91;;
let _ARM64_AT_S1E1WP = 92;;
let _ARM64_DC_INVALID = 0;;
let _ARM64_DC_ZVA = 1;;
let _ARM64_DC_IVAC = 2;;
let _ARM64_DC_ISW = 3;;
let _ARM64_DC_CVAC = 4;;
let _ARM64_DC_CSW = 5;;
let _ARM64_DC_CVAU = 6;;
let _ARM64_DC_CIVAC = 7;;
let _ARM64_DC_CISW = 8;;
let _ARM64_DC_CVAP = 9;;
let _ARM64_IC_INVALID = 0;;
let _ARM64_IC_IALLUIS = 1;;
let _ARM64_IC_IALLU = 2;;
let _ARM64_IC_IVAU = 3;;
let _ARM64_DC_ZVA = 93;;
let _ARM64_DC_IVAC = 94;;
let _ARM64_DC_ISW = 95;;
let _ARM64_DC_CVAC = 96;;
let _ARM64_DC_CSW = 97;;
let _ARM64_DC_CVAU = 98;;
let _ARM64_DC_CIVAC = 99;;
let _ARM64_DC_CISW = 100;;
let _ARM64_DC_CVAP = 101;;
let _ARM64_IC_INVALID = 102;;
let _ARM64_IC_IALLUIS = 103;;
let _ARM64_IC_IALLU = 104;;
let _ARM64_IC_IVAU = 105;;
let _ARM64_PRFM_INVALID = 0;;
let _ARM64_PRFM_PLDL1KEEP = 0x00+1;;

28
bindings/python/capstone/arm64_const.py
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@ -918,22 +918,18 @@ ARM64_AT_S12E0R = 89
ARM64_AT_S12E0W = 90
ARM64_AT_S1E1RP = 91
ARM64_AT_S1E1WP = 92
ARM64_DC_INVALID = 0
ARM64_DC_ZVA = 1
ARM64_DC_IVAC = 2
ARM64_DC_ISW = 3
ARM64_DC_CVAC = 4
ARM64_DC_CSW = 5
ARM64_DC_CVAU = 6
ARM64_DC_CIVAC = 7
ARM64_DC_CISW = 8
ARM64_DC_CVAP = 9
ARM64_IC_INVALID = 0
ARM64_IC_IALLUIS = 1
ARM64_IC_IALLU = 2
ARM64_IC_IVAU = 3
ARM64_DC_ZVA = 93
ARM64_DC_IVAC = 94
ARM64_DC_ISW = 95
ARM64_DC_CVAC = 96
ARM64_DC_CSW = 97
ARM64_DC_CVAU = 98
ARM64_DC_CIVAC = 99
ARM64_DC_CISW = 100
ARM64_DC_CVAP = 101
ARM64_IC_IALLUIS = 102
ARM64_IC_IALLU = 103
ARM64_IC_IVAU = 104
ARM64_PRFM_INVALID = 0
ARM64_PRFM_PLDL1KEEP = 0x00+1

25
include/capstone/arm64.h
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@ -866,10 +866,11 @@ typedef enum arm64_op_type {
ARM64_OP_BARRIER, ///< Memory barrier operand (ISB/DMB/DSB instructions).
} arm64_op_type;
/// TLBI operations
typedef enum arm64_tlbi_op {
ARM64_TLBI_INVALID = 0,
/// SYS operands (IC/DC/AC/TLBI)
typedef enum arm64_sys_op {
ARM64_SYS_INVALID = 0,
/// TLBI operations
ARM64_TLBI_IPAS2E1IS,
ARM64_TLBI_IPAS2LE1IS,
ARM64_TLBI_VMALLE1IS,
@ -948,10 +949,8 @@ typedef enum arm64_tlbi_op {
ARM64_TLBI_RVALE3IS,
ARM64_TLBI_RVAE3OS,
ARM64_TLBI_RVALE3OS,
} arm64_tlbi_op;
/// AT operations
typedef enum arm64_at_op {
/// AT operations
ARM64_AT_S1E1R,
ARM64_AT_S1E2R,
ARM64_AT_S1E3R,
@ -966,11 +965,8 @@ typedef enum arm64_at_op {
ARM64_AT_S12E0W,
ARM64_AT_S1E1RP,
ARM64_AT_S1E1WP,
} arm64_at_op;
/// DC operations
typedef enum arm64_dc_op {
ARM64_DC_INVALID = 0,
/// DC operations
ARM64_DC_ZVA,
ARM64_DC_IVAC,
ARM64_DC_ISW,
@ -980,15 +976,12 @@ typedef enum arm64_dc_op {
ARM64_DC_CIVAC,
ARM64_DC_CISW,
ARM64_DC_CVAP,
} arm64_dc_op;
/// IC operations
typedef enum arm64_ic_op {
ARM64_IC_INVALID = 0,
/// IC operations
ARM64_IC_IALLUIS,
ARM64_IC_IALLU,
ARM64_IC_IVAU,
} arm64_ic_op;
} arm64_sys_op;
/// Prefetch operations (PRFM)
typedef enum arm64_prefetch_op {
@ -1360,7 +1353,7 @@ typedef struct cs_arm64_op {
double fp; ///< floating point value for FP operand
arm64_op_mem mem; ///< base/index/scale/disp value for MEM operand
arm64_pstate pstate; ///< PState field of MSR instruction.
unsigned int sys; ///< IC/DC/AT/TLBI operation (see arm64_ic_op, arm64_dc_op, arm64_at_op, arm64_tlbi_op)
arm64_sys_op sys; ///< IC/DC/AT/TLBI operation (see arm64_ic_op, arm64_dc_op, arm64_at_op, arm64_tlbi_op)
arm64_prefetch_op prefetch; ///< PRFM operation.
arm64_barrier_op barrier; ///< Memory barrier operation (ISB/DMB/DSB instructions).
};

20
suite/cstest/issues.cs
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@ -1,3 +1,23 @@
!# issue 1856 AArch64 SYS instruction operands: tlbi 1 op
!# CS_ARCH_ARM64, CS_MODE_ARM, CS_OPT_DETAIL
0x1f,0x83,0x08,0xd5 == tlbi vmalle1is ; op_count: 1 ; operands[0].type: SYS = 0x3
!# issue 1856 AArch64 SYS instruction operands: tlbi 2 op
!# CS_ARCH_ARM64, CS_MODE_ARM, CS_OPT_DETAIL
0x22,0x87,0x08,0xd5 == tlbi vae1, x2 ; op_count: 2 ; operands[0].type: SYS = 0x16
!# issue 1856 AArch64 SYS instruction operands: at
!# CS_ARCH_ARM64, CS_MODE_ARM, CS_OPT_DETAIL
0xc0,0x78,0x0c,0xd5 == at s12e0r, x0 ; op_count: 2 ; operands[0].type: SYS = 0x59
!# issue 1856 AArch64 SYS instruction operands: dc
!# CS_ARCH_ARM64, CS_MODE_ARM, CS_OPT_DETAIL
0x22,0x7b,0x0b,0xd5 == dc cvau, x2 ; op_count: 2 ; operands[0].type: SYS = 0x62
!# issue 1856 AArch64 SYS instruction operands: ic
!# CS_ARCH_ARM64, CS_MODE_ARM, CS_OPT_DETAIL
0x20,0x75,0x0b,0xd5 == ic ivau, x0 ; op_count: 2 ; operands[0].type: SYS = 0x68
!# issue 1839 AArch64 Incorrect detailed disassembly of ldr
!# CS_ARCH_ARM64, CS_MODE_ARM, CS_OPT_DETAIL
0x41,0x00,0x40,0xf9 == ldr x1, [x2] ; operands[0].access: WRITE ; operands[1].access: READ