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Auto-Sync Mips (#2410)

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Giovanni 2024-09-07 22:30:47 +08:00 committed by GitHub
parent e6da49d549
commit 6a7fef60ea
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GPG Key ID: B5690EEEBB952194
202 changed files with 210042 additions and 21890 deletions
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2
.github/workflows/auto-sync.yml vendored
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@ -77,6 +77,7 @@ jobs:
./src/autosync/ASUpdater.py -d -a ARM -s IncGen
./src/autosync/ASUpdater.py -d -a PPC -s IncGen
./src/autosync/ASUpdater.py -d -a LoongArch -s IncGen
./src/autosync/ASUpdater.py -d -a Mips -s IncGen
- name: CppTranslator - Patch tests
run: |
@ -92,6 +93,7 @@ jobs:
./src/autosync/ASUpdater.py --ci -d -a ARM -s Translate
./src/autosync/ASUpdater.py --ci -d -a PPC -s Translate
./src/autosync/ASUpdater.py --ci -d -a LoongArch -s Translate
./src/autosync/ASUpdater.py --ci -d -a Mips -s Translate
- name: Differ - Test save file is up-to-date
run: |

2
.gitignore vendored
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@ -143,7 +143,7 @@ cstool/cstool
android-ndk-*
# python virtual env
.venv/
.ven*/
# Auto-sync files
suite/auto-sync/src/autosync.egg-info

5
MCInstPrinter.c
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@ -7,6 +7,7 @@
extern bool ARM_getFeatureBits(unsigned int mode, unsigned int feature);
extern bool PPC_getFeatureBits(unsigned int mode, unsigned int feature);
extern bool Mips_getFeatureBits(unsigned int mode, unsigned int feature);
extern bool AArch64_getFeatureBits(unsigned int mode, unsigned int feature);
extern bool TriCore_getFeatureBits(unsigned int mode, unsigned int feature);
@ -25,6 +26,10 @@ static bool testFeatureBits(const MCInst *MI, uint32_t Value)
case CS_ARCH_PPC:
return PPC_getFeatureBits(MI->csh->mode, Value);
#endif
#ifdef CAPSTONE_HAS_MIPS
case CS_ARCH_MIPS:
return Mips_getFeatureBits(MI->csh->mode, Value);
#endif
#ifdef CAPSTONE_HAS_AARCH64
case CS_ARCH_AARCH64:
return AArch64_getFeatureBits(MI->csh->mode, Value);

4
MCRegisterInfo.c
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@ -149,3 +149,7 @@ bool MCRegisterClass_contains(const MCRegisterClass *c, unsigned Reg)
return (c->RegSet[Byte] & (1 << InByte)) != 0;
}
unsigned MCRegisterClass_getRegister(const MCRegisterClass *c, unsigned RegNo) {
return c->RegsBegin[RegNo];
}

2
MCRegisterInfo.h
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@ -113,4 +113,6 @@ const MCRegisterClass* MCRegisterInfo_getRegClass(const MCRegisterInfo *RI, unsi
bool MCRegisterClass_contains(const MCRegisterClass *c, unsigned Reg);
unsigned MCRegisterClass_getRegister(const MCRegisterClass *c, unsigned i);
#endif

1
Mapping.c
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@ -338,6 +338,7 @@ DEFINE_get_detail_op(aarch64, AArch64);
DEFINE_get_detail_op(alpha, Alpha);
DEFINE_get_detail_op(hppa, HPPA);
DEFINE_get_detail_op(loongarch, LoongArch);
DEFINE_get_detail_op(mips, Mips);
DEFINE_get_detail_op(riscv, RISCV);
/// Returns true if for this architecture the

4
Mapping.h
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@ -138,6 +138,7 @@ DECL_get_detail_op(aarch64, AArch64);
DECL_get_detail_op(alpha, Alpha);
DECL_get_detail_op(hppa, HPPA);
DECL_get_detail_op(loongarch, LoongArch);
DECL_get_detail_op(mips, Mips);
DECL_get_detail_op(riscv, RISCV);
/// Increments the detail->arch.op_count by one.
@ -168,6 +169,8 @@ DEFINE_inc_detail_op_count(hppa, HPPA);
DEFINE_dec_detail_op_count(hppa, HPPA);
DEFINE_inc_detail_op_count(loongarch, LoongArch);
DEFINE_dec_detail_op_count(loongarch, LoongArch);
DEFINE_inc_detail_op_count(mips, Mips);
DEFINE_dec_detail_op_count(mips, Mips);
DEFINE_inc_detail_op_count(riscv, RISCV);
DEFINE_dec_detail_op_count(riscv, RISCV);
@ -198,6 +201,7 @@ DEFINE_get_arch_detail(aarch64, AArch64);
DEFINE_get_arch_detail(alpha, Alpha);
DEFINE_get_arch_detail(hppa, HPPA);
DEFINE_get_arch_detail(loongarch, LoongArch);
DEFINE_get_arch_detail(mips, Mips);
DEFINE_get_arch_detail(riscv, RISCV);
static inline bool detail_is_set(const MCInst *MI)

190
arch/Mips/MipsCP0RegisterMap.h Normal file
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@ -0,0 +1,190 @@
//===- MipsCP0RegisterMap.h - Co-processor register names for Mips/nanoMIPS -===//
// This has been created by hand.
#ifndef LLVM_LIB_TARGET_MIPS_NANOMIPSCP0REGMAP_H
#define LLVM_LIB_TARGET_MIPS_NANOMIPSCP0REGMAP_H
struct CP0SelRegister_t {
const char *Name;
int RegNum;
int Select;
int Index;
};
static const struct CP0SelRegister_t CP0SelRegs[] = {
{"index", 0, 0},
{"mvpcontrol", 0, 1},
{"mvpconf0", 0, 2},
{"mvpconf1", 0, 3},
{"vpcontrol", 0, 4},
{"random", 1, 0},
{"vpecontrol", 1, 1},
{"vpeconf0", 1, 2},
{"vpeconf1", 1, 3},
{"yqmask", 1, 4},
{"vpeschedule", 1, 5},
{"vpeschefback", 1, 6},
{"vpeopt", 1, 7},
{"entrylo0", 2, 0},
{"tcstatus", 2, 1},
{"tcbind", 2, 2},
{"tcrestart", 2, 3},
{"tchalt", 2, 4},
{"tccontext", 2, 5},
{"tcschedule", 2, 6},
{"tcschefback", 2, 7},
{"entrylo1", 3, 0},
{"globalnumber", 3, 1},
{"tcopt", 3, 7},
{"context", 4, 0},
{"contextconfig", 4, 1},
{"userlocal", 4, 2},
{"xcontextconfig", 4, 3},
{"debugcontextid", 4, 4},
{"memorymapid", 4, 5},
{"pagemask", 5, 0},
{"pagegrain", 5, 1},
{"segctl0", 5, 2},
{"segctl1", 5, 3},
{"segctl2", 5, 4},
{"pwbase", 5, 5},
{"pwfield", 5, 6},
{"pwsize", 5, 7},
{"wired", 6, 0},
{"srsconf0", 6, 1},
{"srsconf1", 6, 2},
{"srsconf2", 6, 3},
{"srsconf3", 6, 4},
{"srsconf4", 6, 5},
{"pwctl", 6, 6},
{"hwrena", 7, 0},
{"badvaddr", 8, 0},
{"badinst", 8, 1},
{"badinstrp", 8, 2},
{"badinstrx", 8, 3},
{"count", 9, 0},
{"entryhi", 10, 0},
{"guestctl1", 10, 4},
{"guestctl2", 10, 5},
{"guestctl3", 10, 6},
{"compare", 11, 0},
{"guestctl0ext", 11, 4},
{"status", 12, 0},
{"intctl", 12, 1},
{"srsctl", 12, 2},
{"srsmap", 12, 3},
{"view_ipl", 12, 4},
{"srsmap2", 12, 5},
{"guestctl0", 12, 6},
{"gtoffset", 12, 7},
{"cause", 13, 0},
{"view_ripl", 13, 4},
{"nestedexc", 13, 5},
{"epc", 14, 0},
{"nestedepc", 14, 2},
{"prid", 15, 0},
{"ebase", 15, 1},
{"cdmmbase", 15, 2},
{"cmgcrbase", 15, 3},
{"bevva", 15, 4},
{"config", 16, 0},
{"config1", 16, 1},
{"config2", 16, 2},
{"config3", 16, 3},
{"config4", 16, 4},
{"config5", 16, 5},
{"lladdr", 17, 0},
{"maar", 17, 1},
{"maari", 17, 2},
{"watchlo0", 18, 0},
{"watchlo1", 18, 1},
{"watchlo2", 18, 2},
{"watchlo3", 18, 3},
{"watchlo4", 18, 4},
{"watchlo5", 18, 5},
{"watchlo6", 18, 6},
{"watchlo7", 18, 7},
{"watchlo8", 18, 8},
{"watchlo9", 18, 9},
{"watchlo10", 18,10},
{"watchlo11", 18,11},
{"watchlo12", 18,12},
{"watchlo13", 18,13},
{"watchlo14", 18,14},
{"watchlo15", 18,15},
{"watchhi0", 19, 0},
{"watchhi1", 19, 1},
{"watchhi2", 19, 2},
{"watchhi3", 19, 3},
{"watchhi4", 19, 4},
{"watchhi5", 19, 5},
{"watchhi6", 19, 6},
{"watchhi7", 19, 7},
{"watchhi8", 19, 8},
{"watchhi9", 19, 9},
{"watchhi10", 19,10},
{"watchhi11", 19,11},
{"watchhi12", 19,12},
{"watchhi13", 19,13},
{"watchhi14", 19,14},
{"watchhi15", 19,15},
{"xcontext", 20, 0},
{"debug", 23, 0},
{"tracecontrol", 23, 1},
{"tracecontrol2", 23, 2},
{"usertracedata1", 23, 3},
{"traceibpc", 23, 4},
{"tracedbpc", 23, 5},
{"debug2", 23, 6},
{"depc", 24, 0},
{"tracecontrol3", 24, 2},
{"usertracedata2", 24, 3},
{"perfctl0", 25, 0},
{"perfcnt0", 25, 1},
{"perfctl1", 25, 2},
{"perfcnt1", 25, 3},
{"perfctl2", 25, 4},
{"perfcnt2", 25, 5},
{"perfctl3", 25, 6},
{"perfcnt3", 25, 7},
{"perfctl4", 25, 8},
{"perfcnt4", 25, 9},
{"perfctl5", 25,10},
{"perfcnt5", 25,11},
{"perfctl6", 25,12},
{"perfcnt6", 25,13},
{"perfctl7", 25,14},
{"perfcnt7", 25,15},
{"errctl", 26, 0},
{"cacheerr", 27, 0},
{"itaglo", 28, 0},
{"idatalo", 28, 1},
{"dtaglo", 28, 2},
{"ddatalo", 28, 3},
{"itaghi", 29, 0},
{"idatahi", 29, 1},
{"dtaghi", 29, 2},
{"ddatahi", 29, 3},
{"errorepc", 30, 0},
{"desave", 31, 0},
{"kscratch1", 31, 2},
{"kscratch2", 31, 3},
{"kscratch3", 31, 4},
{"kscratch4", 31, 5},
{"kscratch5", 31, 6},
{"kscratch6", 31, 7}
};
inline static int COP0Map_getEncIndexMap(int RegNo)
{
int i;
for (i = 0; i < (sizeof(CP0SelRegs) / sizeof(CP0SelRegs[0])); ++i) {
unsigned RegEnc = (CP0SelRegs[i].RegNum << 5) | CP0SelRegs[i].Select;
if (RegEnc == RegNo) {
return i;
}
}
return -1;
}
#endif // LLVM_LIB_TARGET_MIPS_NANOMIPSCP0REGMAP_H

4005
arch/Mips/MipsDisassembler.c
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File diff suppressed because it is too large Load Diff

3
arch/Mips/MipsDisassembler.h
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@ -10,7 +10,6 @@
void Mips_init(MCRegisterInfo *MRI);
bool Mips_getInstruction(csh handle, const uint8_t *code, size_t code_len,
MCInst *instr, uint16_t *size, uint64_t address, void *info);
bool Mips_getFeatureBits(unsigned int mode, unsigned int feature);
#endif

15865
arch/Mips/MipsGenAsmWriter.inc
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File diff suppressed because it is too large Load Diff

119
arch/Mips/MipsGenCSAliasEnum.inc Normal file
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@ -0,0 +1,119 @@
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
MIPS_INS_ALIAS_ADDIU_B32, // Real instr.: MIPS_ADDIUGP48_NM
MIPS_INS_ALIAS_BITREVB, // Real instr.: MIPS_ROTX_NM
MIPS_INS_ALIAS_BITREVH, // Real instr.: MIPS_ROTX_NM
MIPS_INS_ALIAS_BYTEREVH, // Real instr.: MIPS_ROTX_NM
MIPS_INS_ALIAS_NOT, // Real instr.: MIPS_NOR_NM
MIPS_INS_ALIAS_RESTORE_JRC, // Real instr.: MIPS_RESTOREJRC16_NM
MIPS_INS_ALIAS_RESTORE, // Real instr.: MIPS_RESTORE_NM
MIPS_INS_ALIAS_SAVE, // Real instr.: MIPS_SAVE16_NM
MIPS_INS_ALIAS_MOVE, // Real instr.: MIPS_OR
MIPS_INS_ALIAS_BAL, // Real instr.: MIPS_BGEZAL
MIPS_INS_ALIAS_JALR_HB, // Real instr.: MIPS_JALR_HB
MIPS_INS_ALIAS_NEG, // Real instr.: MIPS_SUB
MIPS_INS_ALIAS_NEGU, // Real instr.: MIPS_SUBu
MIPS_INS_ALIAS_NOP, // Real instr.: MIPS_SLL
MIPS_INS_ALIAS_BNEZL, // Real instr.: MIPS_BNEL
MIPS_INS_ALIAS_BEQZL, // Real instr.: MIPS_BEQL
MIPS_INS_ALIAS_SYSCALL, // Real instr.: MIPS_SYSCALL
MIPS_INS_ALIAS_BREAK, // Real instr.: MIPS_BREAK
MIPS_INS_ALIAS_EI, // Real instr.: MIPS_EI
MIPS_INS_ALIAS_DI, // Real instr.: MIPS_DI
MIPS_INS_ALIAS_TEQ, // Real instr.: MIPS_TEQ
MIPS_INS_ALIAS_TGE, // Real instr.: MIPS_TGE
MIPS_INS_ALIAS_TGEU, // Real instr.: MIPS_TGEU
MIPS_INS_ALIAS_TLT, // Real instr.: MIPS_TLT
MIPS_INS_ALIAS_TLTU, // Real instr.: MIPS_TLTU
MIPS_INS_ALIAS_TNE, // Real instr.: MIPS_TNE
MIPS_INS_ALIAS_RDHWR, // Real instr.: MIPS_RDHWR
MIPS_INS_ALIAS_SDBBP, // Real instr.: MIPS_SDBBP
MIPS_INS_ALIAS_SYNC, // Real instr.: MIPS_SYNC
MIPS_INS_ALIAS_HYPCALL, // Real instr.: MIPS_HYPCALL
MIPS_INS_ALIAS_NOR, // Real instr.: MIPS_NORImm
MIPS_INS_ALIAS_C_F_S, // Real instr.: MIPS_C_F_S
MIPS_INS_ALIAS_C_UN_S, // Real instr.: MIPS_C_UN_S
MIPS_INS_ALIAS_C_EQ_S, // Real instr.: MIPS_C_EQ_S
MIPS_INS_ALIAS_C_UEQ_S, // Real instr.: MIPS_C_UEQ_S
MIPS_INS_ALIAS_C_OLT_S, // Real instr.: MIPS_C_OLT_S
MIPS_INS_ALIAS_C_ULT_S, // Real instr.: MIPS_C_ULT_S
MIPS_INS_ALIAS_C_OLE_S, // Real instr.: MIPS_C_OLE_S
MIPS_INS_ALIAS_C_ULE_S, // Real instr.: MIPS_C_ULE_S
MIPS_INS_ALIAS_C_SF_S, // Real instr.: MIPS_C_SF_S
MIPS_INS_ALIAS_C_NGLE_S, // Real instr.: MIPS_C_NGLE_S
MIPS_INS_ALIAS_C_SEQ_S, // Real instr.: MIPS_C_SEQ_S
MIPS_INS_ALIAS_C_NGL_S, // Real instr.: MIPS_C_NGL_S
MIPS_INS_ALIAS_C_LT_S, // Real instr.: MIPS_C_LT_S
MIPS_INS_ALIAS_C_NGE_S, // Real instr.: MIPS_C_NGE_S
MIPS_INS_ALIAS_C_LE_S, // Real instr.: MIPS_C_LE_S
MIPS_INS_ALIAS_C_NGT_S, // Real instr.: MIPS_C_NGT_S
MIPS_INS_ALIAS_BC1T, // Real instr.: MIPS_BC1T
MIPS_INS_ALIAS_BC1F, // Real instr.: MIPS_BC1F
MIPS_INS_ALIAS_C_F_D, // Real instr.: MIPS_C_F_D32
MIPS_INS_ALIAS_C_UN_D, // Real instr.: MIPS_C_UN_D32
MIPS_INS_ALIAS_C_EQ_D, // Real instr.: MIPS_C_EQ_D32
MIPS_INS_ALIAS_C_UEQ_D, // Real instr.: MIPS_C_UEQ_D32
MIPS_INS_ALIAS_C_OLT_D, // Real instr.: MIPS_C_OLT_D32
MIPS_INS_ALIAS_C_ULT_D, // Real instr.: MIPS_C_ULT_D32
MIPS_INS_ALIAS_C_OLE_D, // Real instr.: MIPS_C_OLE_D32
MIPS_INS_ALIAS_C_ULE_D, // Real instr.: MIPS_C_ULE_D32
MIPS_INS_ALIAS_C_SF_D, // Real instr.: MIPS_C_SF_D32
MIPS_INS_ALIAS_C_NGLE_D, // Real instr.: MIPS_C_NGLE_D32
MIPS_INS_ALIAS_C_SEQ_D, // Real instr.: MIPS_C_SEQ_D32
MIPS_INS_ALIAS_C_NGL_D, // Real instr.: MIPS_C_NGL_D32
MIPS_INS_ALIAS_C_LT_D, // Real instr.: MIPS_C_LT_D32
MIPS_INS_ALIAS_C_NGE_D, // Real instr.: MIPS_C_NGE_D32
MIPS_INS_ALIAS_C_LE_D, // Real instr.: MIPS_C_LE_D32
MIPS_INS_ALIAS_C_NGT_D, // Real instr.: MIPS_C_NGT_D32
MIPS_INS_ALIAS_BC1TL, // Real instr.: MIPS_BC1TL
MIPS_INS_ALIAS_BC1FL, // Real instr.: MIPS_BC1FL
MIPS_INS_ALIAS_DNEG, // Real instr.: MIPS_DSUB
MIPS_INS_ALIAS_DNEGU, // Real instr.: MIPS_DSUBu
MIPS_INS_ALIAS_SLT, // Real instr.: MIPS_SLTImm64
MIPS_INS_ALIAS_SLTU, // Real instr.: MIPS_SLTUImm64
MIPS_INS_ALIAS_SIGRIE, // Real instr.: MIPS_SIGRIE
MIPS_INS_ALIAS_JR, // Real instr.: MIPS_JALR
MIPS_INS_ALIAS_JRC, // Real instr.: MIPS_JIC
MIPS_INS_ALIAS_JALRC, // Real instr.: MIPS_JIALC
MIPS_INS_ALIAS_DIV, // Real instr.: MIPS_DIV
MIPS_INS_ALIAS_DIVU, // Real instr.: MIPS_DIVU
MIPS_INS_ALIAS_LAPC, // Real instr.: MIPS_ADDIUPC
MIPS_INS_ALIAS_WRDSP, // Real instr.: MIPS_WRDSP
MIPS_INS_ALIAS_WAIT, // Real instr.: MIPS_WAIT_MM
MIPS_INS_ALIAS_SW, // Real instr.: MIPS_SWSP_MM
MIPS_INS_ALIAS_JALRC_HB, // Real instr.: MIPS_JALRC_HB_MMR6
MIPS_INS_ALIAS_ADDIU_B, // Real instr.: MIPS_ADDIUGPB_NM
MIPS_INS_ALIAS_ADDIU_W, // Real instr.: MIPS_ADDIUGPW_NM
MIPS_INS_ALIAS_JRC_HB, // Real instr.: MIPS_JALRCHB_NM
MIPS_INS_ALIAS_BEQC, // Real instr.: MIPS_BEQC16_NM
MIPS_INS_ALIAS_BNEC, // Real instr.: MIPS_BNEC16_NM
MIPS_INS_ALIAS_BEQZC, // Real instr.: MIPS_BEQC_NM
MIPS_INS_ALIAS_BNEZC, // Real instr.: MIPS_BNEC_NM
MIPS_INS_ALIAS_MFC0, // Real instr.: MIPS_MFC0_NM
MIPS_INS_ALIAS_MFHC0, // Real instr.: MIPS_MFHC0_NM
MIPS_INS_ALIAS_MTC0, // Real instr.: MIPS_MTC0_NM
MIPS_INS_ALIAS_MTHC0, // Real instr.: MIPS_MTHC0_NM
MIPS_INS_ALIAS_DMT, // Real instr.: MIPS_DMT
MIPS_INS_ALIAS_EMT, // Real instr.: MIPS_EMT
MIPS_INS_ALIAS_DVPE, // Real instr.: MIPS_DVPE
MIPS_INS_ALIAS_EVPE, // Real instr.: MIPS_EVPE
MIPS_INS_ALIAS_YIELD, // Real instr.: MIPS_YIELD
MIPS_INS_ALIAS_MFTC0, // Real instr.: MIPS_MFTC0
MIPS_INS_ALIAS_MFTLO, // Real instr.: MIPS_MFTLO
MIPS_INS_ALIAS_MFTHI, // Real instr.: MIPS_MFTHI
MIPS_INS_ALIAS_MFTACX, // Real instr.: MIPS_MFTACX
MIPS_INS_ALIAS_MTTC0, // Real instr.: MIPS_MTTC0
MIPS_INS_ALIAS_MTTLO, // Real instr.: MIPS_MTTLO
MIPS_INS_ALIAS_MTTHI, // Real instr.: MIPS_MTTHI
MIPS_INS_ALIAS_MTTACX, // Real instr.: MIPS_MTTACX

119
arch/Mips/MipsGenCSAliasMnemMap.inc Normal file
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@ -0,0 +1,119 @@
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
{ MIPS_INS_ALIAS_ADDIU_B32, "addiu_b32" },
{ MIPS_INS_ALIAS_BITREVB, "bitrevb" },
{ MIPS_INS_ALIAS_BITREVH, "bitrevh" },
{ MIPS_INS_ALIAS_BYTEREVH, "byterevh" },
{ MIPS_INS_ALIAS_NOT, "not" },
{ MIPS_INS_ALIAS_RESTORE_JRC, "restore_jrc" },
{ MIPS_INS_ALIAS_RESTORE, "restore" },
{ MIPS_INS_ALIAS_SAVE, "save" },
{ MIPS_INS_ALIAS_MOVE, "move" },
{ MIPS_INS_ALIAS_BAL, "bal" },
{ MIPS_INS_ALIAS_JALR_HB, "jalr_hb" },
{ MIPS_INS_ALIAS_NEG, "neg" },
{ MIPS_INS_ALIAS_NEGU, "negu" },
{ MIPS_INS_ALIAS_NOP, "nop" },
{ MIPS_INS_ALIAS_BNEZL, "bnezl" },
{ MIPS_INS_ALIAS_BEQZL, "beqzl" },
{ MIPS_INS_ALIAS_SYSCALL, "syscall" },
{ MIPS_INS_ALIAS_BREAK, "break" },
{ MIPS_INS_ALIAS_EI, "ei" },
{ MIPS_INS_ALIAS_DI, "di" },
{ MIPS_INS_ALIAS_TEQ, "teq" },
{ MIPS_INS_ALIAS_TGE, "tge" },
{ MIPS_INS_ALIAS_TGEU, "tgeu" },
{ MIPS_INS_ALIAS_TLT, "tlt" },
{ MIPS_INS_ALIAS_TLTU, "tltu" },
{ MIPS_INS_ALIAS_TNE, "tne" },
{ MIPS_INS_ALIAS_RDHWR, "rdhwr" },
{ MIPS_INS_ALIAS_SDBBP, "sdbbp" },
{ MIPS_INS_ALIAS_SYNC, "sync" },
{ MIPS_INS_ALIAS_HYPCALL, "hypcall" },
{ MIPS_INS_ALIAS_NOR, "nor" },
{ MIPS_INS_ALIAS_C_F_S, "c_f_s" },
{ MIPS_INS_ALIAS_C_UN_S, "c_un_s" },
{ MIPS_INS_ALIAS_C_EQ_S, "c_eq_s" },
{ MIPS_INS_ALIAS_C_UEQ_S, "c_ueq_s" },
{ MIPS_INS_ALIAS_C_OLT_S, "c_olt_s" },
{ MIPS_INS_ALIAS_C_ULT_S, "c_ult_s" },
{ MIPS_INS_ALIAS_C_OLE_S, "c_ole_s" },
{ MIPS_INS_ALIAS_C_ULE_S, "c_ule_s" },
{ MIPS_INS_ALIAS_C_SF_S, "c_sf_s" },
{ MIPS_INS_ALIAS_C_NGLE_S, "c_ngle_s" },
{ MIPS_INS_ALIAS_C_SEQ_S, "c_seq_s" },
{ MIPS_INS_ALIAS_C_NGL_S, "c_ngl_s" },
{ MIPS_INS_ALIAS_C_LT_S, "c_lt_s" },
{ MIPS_INS_ALIAS_C_NGE_S, "c_nge_s" },
{ MIPS_INS_ALIAS_C_LE_S, "c_le_s" },
{ MIPS_INS_ALIAS_C_NGT_S, "c_ngt_s" },
{ MIPS_INS_ALIAS_BC1T, "bc1t" },
{ MIPS_INS_ALIAS_BC1F, "bc1f" },
{ MIPS_INS_ALIAS_C_F_D, "c_f_d" },
{ MIPS_INS_ALIAS_C_UN_D, "c_un_d" },
{ MIPS_INS_ALIAS_C_EQ_D, "c_eq_d" },
{ MIPS_INS_ALIAS_C_UEQ_D, "c_ueq_d" },
{ MIPS_INS_ALIAS_C_OLT_D, "c_olt_d" },
{ MIPS_INS_ALIAS_C_ULT_D, "c_ult_d" },
{ MIPS_INS_ALIAS_C_OLE_D, "c_ole_d" },
{ MIPS_INS_ALIAS_C_ULE_D, "c_ule_d" },
{ MIPS_INS_ALIAS_C_SF_D, "c_sf_d" },
{ MIPS_INS_ALIAS_C_NGLE_D, "c_ngle_d" },
{ MIPS_INS_ALIAS_C_SEQ_D, "c_seq_d" },
{ MIPS_INS_ALIAS_C_NGL_D, "c_ngl_d" },
{ MIPS_INS_ALIAS_C_LT_D, "c_lt_d" },
{ MIPS_INS_ALIAS_C_NGE_D, "c_nge_d" },
{ MIPS_INS_ALIAS_C_LE_D, "c_le_d" },
{ MIPS_INS_ALIAS_C_NGT_D, "c_ngt_d" },
{ MIPS_INS_ALIAS_BC1TL, "bc1tl" },
{ MIPS_INS_ALIAS_BC1FL, "bc1fl" },
{ MIPS_INS_ALIAS_DNEG, "dneg" },
{ MIPS_INS_ALIAS_DNEGU, "dnegu" },
{ MIPS_INS_ALIAS_SLT, "slt" },
{ MIPS_INS_ALIAS_SLTU, "sltu" },
{ MIPS_INS_ALIAS_SIGRIE, "sigrie" },
{ MIPS_INS_ALIAS_JR, "jr" },
{ MIPS_INS_ALIAS_JRC, "jrc" },
{ MIPS_INS_ALIAS_JALRC, "jalrc" },
{ MIPS_INS_ALIAS_DIV, "div" },
{ MIPS_INS_ALIAS_DIVU, "divu" },
{ MIPS_INS_ALIAS_LAPC, "lapc" },
{ MIPS_INS_ALIAS_WRDSP, "wrdsp" },
{ MIPS_INS_ALIAS_WAIT, "wait" },
{ MIPS_INS_ALIAS_SW, "sw" },
{ MIPS_INS_ALIAS_JALRC_HB, "jalrc_hb" },
{ MIPS_INS_ALIAS_ADDIU_B, "addiu_b" },
{ MIPS_INS_ALIAS_ADDIU_W, "addiu_w" },
{ MIPS_INS_ALIAS_JRC_HB, "jrc_hb" },
{ MIPS_INS_ALIAS_BEQC, "beqc" },
{ MIPS_INS_ALIAS_BNEC, "bnec" },
{ MIPS_INS_ALIAS_BEQZC, "beqzc" },
{ MIPS_INS_ALIAS_BNEZC, "bnezc" },
{ MIPS_INS_ALIAS_MFC0, "mfc0" },
{ MIPS_INS_ALIAS_MFHC0, "mfhc0" },
{ MIPS_INS_ALIAS_MTC0, "mtc0" },
{ MIPS_INS_ALIAS_MTHC0, "mthc0" },
{ MIPS_INS_ALIAS_DMT, "dmt" },
{ MIPS_INS_ALIAS_EMT, "emt" },
{ MIPS_INS_ALIAS_DVPE, "dvpe" },
{ MIPS_INS_ALIAS_EVPE, "evpe" },
{ MIPS_INS_ALIAS_YIELD, "yield" },
{ MIPS_INS_ALIAS_MFTC0, "mftc0" },
{ MIPS_INS_ALIAS_MFTLO, "mftlo" },
{ MIPS_INS_ALIAS_MFTHI, "mfthi" },
{ MIPS_INS_ALIAS_MFTACX, "mftacx" },
{ MIPS_INS_ALIAS_MTTC0, "mttc0" },
{ MIPS_INS_ALIAS_MTTLO, "mttlo" },
{ MIPS_INS_ALIAS_MTTHI, "mtthi" },
{ MIPS_INS_ALIAS_MTTACX, "mttacx" },

69
arch/Mips/MipsGenCSFeatureEnum.inc Normal file
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/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
MIPS_FEATURE_HASMIPS2 = 128,
MIPS_FEATURE_HASMIPS3_32,
MIPS_FEATURE_HASMIPS3_32R2,
MIPS_FEATURE_HASMIPS3,
MIPS_FEATURE_NOTMIPS3,
MIPS_FEATURE_HASMIPS4_32,
MIPS_FEATURE_NOTMIPS4_32,
MIPS_FEATURE_HASMIPS4_32R2,
MIPS_FEATURE_HASMIPS5_32R2,
MIPS_FEATURE_HASMIPS32,
MIPS_FEATURE_HASMIPS32R2,
MIPS_FEATURE_HASMIPS32R5,
MIPS_FEATURE_HASMIPS32R6,
MIPS_FEATURE_NOTMIPS32R6,
MIPS_FEATURE_HASNANOMIPS,
MIPS_FEATURE_NOTNANOMIPS,
MIPS_FEATURE_ISGP64BIT,
MIPS_FEATURE_ISGP32BIT,
MIPS_FEATURE_ISPTR64BIT,
MIPS_FEATURE_ISPTR32BIT,
MIPS_FEATURE_HASMIPS64,
MIPS_FEATURE_NOTMIPS64,
MIPS_FEATURE_HASMIPS64R2,
MIPS_FEATURE_HASMIPS64R5,
MIPS_FEATURE_HASMIPS64R6,
MIPS_FEATURE_NOTMIPS64R6,
MIPS_FEATURE_INMIPS16MODE,
MIPS_FEATURE_NOTINMIPS16MODE,
MIPS_FEATURE_HASCNMIPS,
MIPS_FEATURE_NOTCNMIPS,
MIPS_FEATURE_HASCNMIPSP,
MIPS_FEATURE_NOTCNMIPSP,
MIPS_FEATURE_ISSYM32,
MIPS_FEATURE_ISSYM64,
MIPS_FEATURE_HASSTDENC,
MIPS_FEATURE_INMICROMIPS,
MIPS_FEATURE_NOTINMICROMIPS,
MIPS_FEATURE_HASEVA,
MIPS_FEATURE_HASMSA,
MIPS_FEATURE_HASMADD4,
MIPS_FEATURE_HASMT,
MIPS_FEATURE_USEINDIRECTJUMPSHAZARD,
MIPS_FEATURE_NOINDIRECTJUMPGUARDS,
MIPS_FEATURE_HASCRC,
MIPS_FEATURE_HASVIRT,
MIPS_FEATURE_HASGINV,
MIPS_FEATURE_HASTLB,
MIPS_FEATURE_ISFP64BIT,
MIPS_FEATURE_NOTFP64BIT,
MIPS_FEATURE_ISSINGLEFLOAT,
MIPS_FEATURE_ISNOTSINGLEFLOAT,
MIPS_FEATURE_ISNOTSOFTFLOAT,
MIPS_FEATURE_HASMIPS3D,
MIPS_FEATURE_HASDSP,
MIPS_FEATURE_HASDSPR2,
MIPS_FEATURE_HASDSPR3,

69
arch/Mips/MipsGenCSFeatureName.inc Normal file
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/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
{ MIPS_FEATURE_HASMIPS2, "HasMips2" },
{ MIPS_FEATURE_HASMIPS3_32, "HasMips3_32" },
{ MIPS_FEATURE_HASMIPS3_32R2, "HasMips3_32r2" },
{ MIPS_FEATURE_HASMIPS3, "HasMips3" },
{ MIPS_FEATURE_NOTMIPS3, "NotMips3" },
{ MIPS_FEATURE_HASMIPS4_32, "HasMips4_32" },
{ MIPS_FEATURE_NOTMIPS4_32, "NotMips4_32" },
{ MIPS_FEATURE_HASMIPS4_32R2, "HasMips4_32r2" },
{ MIPS_FEATURE_HASMIPS5_32R2, "HasMips5_32r2" },
{ MIPS_FEATURE_HASMIPS32, "HasMips32" },
{ MIPS_FEATURE_HASMIPS32R2, "HasMips32r2" },
{ MIPS_FEATURE_HASMIPS32R5, "HasMips32r5" },
{ MIPS_FEATURE_HASMIPS32R6, "HasMips32r6" },
{ MIPS_FEATURE_NOTMIPS32R6, "NotMips32r6" },
{ MIPS_FEATURE_HASNANOMIPS, "HasNanoMips" },
{ MIPS_FEATURE_NOTNANOMIPS, "NotNanoMips" },
{ MIPS_FEATURE_ISGP64BIT, "IsGP64bit" },
{ MIPS_FEATURE_ISGP32BIT, "IsGP32bit" },
{ MIPS_FEATURE_ISPTR64BIT, "IsPTR64bit" },
{ MIPS_FEATURE_ISPTR32BIT, "IsPTR32bit" },
{ MIPS_FEATURE_HASMIPS64, "HasMips64" },
{ MIPS_FEATURE_NOTMIPS64, "NotMips64" },
{ MIPS_FEATURE_HASMIPS64R2, "HasMips64r2" },
{ MIPS_FEATURE_HASMIPS64R5, "HasMips64r5" },
{ MIPS_FEATURE_HASMIPS64R6, "HasMips64r6" },
{ MIPS_FEATURE_NOTMIPS64R6, "NotMips64r6" },
{ MIPS_FEATURE_INMIPS16MODE, "InMips16Mode" },
{ MIPS_FEATURE_NOTINMIPS16MODE, "NotInMips16Mode" },
{ MIPS_FEATURE_HASCNMIPS, "HasCnMips" },
{ MIPS_FEATURE_NOTCNMIPS, "NotCnMips" },
{ MIPS_FEATURE_HASCNMIPSP, "HasCnMipsP" },
{ MIPS_FEATURE_NOTCNMIPSP, "NotCnMipsP" },
{ MIPS_FEATURE_ISSYM32, "IsSym32" },
{ MIPS_FEATURE_ISSYM64, "IsSym64" },
{ MIPS_FEATURE_HASSTDENC, "HasStdEnc" },
{ MIPS_FEATURE_INMICROMIPS, "InMicroMips" },
{ MIPS_FEATURE_NOTINMICROMIPS, "NotInMicroMips" },
{ MIPS_FEATURE_HASEVA, "HasEVA" },
{ MIPS_FEATURE_HASMSA, "HasMSA" },
{ MIPS_FEATURE_HASMADD4, "HasMadd4" },
{ MIPS_FEATURE_HASMT, "HasMT" },
{ MIPS_FEATURE_USEINDIRECTJUMPSHAZARD, "UseIndirectJumpsHazard" },
{ MIPS_FEATURE_NOINDIRECTJUMPGUARDS, "NoIndirectJumpGuards" },
{ MIPS_FEATURE_HASCRC, "HasCRC" },
{ MIPS_FEATURE_HASVIRT, "HasVirt" },
{ MIPS_FEATURE_HASGINV, "HasGINV" },
{ MIPS_FEATURE_HASTLB, "HasTLB" },
{ MIPS_FEATURE_ISFP64BIT, "IsFP64bit" },
{ MIPS_FEATURE_NOTFP64BIT, "NotFP64bit" },
{ MIPS_FEATURE_ISSINGLEFLOAT, "IsSingleFloat" },
{ MIPS_FEATURE_ISNOTSINGLEFLOAT, "IsNotSingleFloat" },
{ MIPS_FEATURE_ISNOTSOFTFLOAT, "IsNotSoftFloat" },
{ MIPS_FEATURE_HASMIPS3D, "HasMips3D" },
{ MIPS_FEATURE_HASDSP, "HasDSP" },
{ MIPS_FEATURE_HASDSPR2, "HasDSPR2" },
{ MIPS_FEATURE_HASDSPR3, "HasDSPR3" },

1373
arch/Mips/MipsGenCSInsnEnum.inc Normal file
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24465
arch/Mips/MipsGenCSMappingInsn.inc Normal file
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1373
arch/Mips/MipsGenCSMappingInsnName.inc Normal file
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18615
arch/Mips/MipsGenCSMappingInsnOp.inc Normal file
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45
arch/Mips/MipsGenCSOpGroup.inc Normal file
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@ -0,0 +1,45 @@
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
Mips_OP_GROUP_Operand = 0,
Mips_OP_GROUP_BranchOperand = 1,
Mips_OP_GROUP_UImm_1_0 = 2,
Mips_OP_GROUP_UImm_2_0 = 3,
Mips_OP_GROUP_JumpOperand = 4,
Mips_OP_GROUP_MemOperand = 5,
Mips_OP_GROUP_RegisterList = 6,
Mips_OP_GROUP_UImm_3_0 = 7,
Mips_OP_GROUP_PCRel = 8,
Mips_OP_GROUP_UImm_32_0 = 9,
Mips_OP_GROUP_UImm_16_0 = 10,
Mips_OP_GROUP_UImm_8_0 = 11,
Mips_OP_GROUP_UImm_5_0 = 12,
Mips_OP_GROUP_Hi20PCRel = 13,
Mips_OP_GROUP_MemOperandEA = 14,
Mips_OP_GROUP_UImm_6_0 = 15,
Mips_OP_GROUP_UImm_4_0 = 16,
Mips_OP_GROUP_UImm_7_0 = 17,
Mips_OP_GROUP_UImm_10_0 = 18,
Mips_OP_GROUP_UImm_6_1 = 19,
Mips_OP_GROUP_UImm_5_1 = 20,
Mips_OP_GROUP_UImm_5_33 = 21,
Mips_OP_GROUP_UImm_5_32 = 22,
Mips_OP_GROUP_UImm_6_2 = 23,
Mips_OP_GROUP_UImm_2_1 = 24,
Mips_OP_GROUP_FCCOperand = 25,
Mips_OP_GROUP_UImm_0_0 = 26,
Mips_OP_GROUP_UImm_26_0 = 27,
Mips_OP_GROUP_Hi20 = 28,
Mips_OP_GROUP_NanoMipsRegisterList = 29,
Mips_OP_GROUP_UImm_12_0 = 30,
Mips_OP_GROUP_UImm_20_0 = 31,

649
arch/Mips/MipsGenCSRegEnum.inc Normal file
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/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
MIPS_REG_INVALID = 0,
MIPS_REG_AT = 1,
MIPS_REG_AT_NM = 2,
MIPS_REG_DSPCCOND = 3,
MIPS_REG_DSPCARRY = 4,
MIPS_REG_DSPEFI = 5,
MIPS_REG_DSPOUTFLAG = 6,
MIPS_REG_DSPPOS = 7,
MIPS_REG_DSPSCOUNT = 8,
MIPS_REG_FP = 9,
MIPS_REG_FP_NM = 10,
MIPS_REG_GP = 11,
MIPS_REG_GP_NM = 12,
MIPS_REG_MSAACCESS = 13,
MIPS_REG_MSACSR = 14,
MIPS_REG_MSAIR = 15,
MIPS_REG_MSAMAP = 16,
MIPS_REG_MSAMODIFY = 17,
MIPS_REG_MSAREQUEST = 18,
MIPS_REG_MSASAVE = 19,
MIPS_REG_MSAUNMAP = 20,
MIPS_REG_PC = 21,
MIPS_REG_RA = 22,
MIPS_REG_RA_NM = 23,
MIPS_REG_SP = 24,
MIPS_REG_SP_NM = 25,
MIPS_REG_ZERO = 26,
MIPS_REG_ZERO_NM = 27,
MIPS_REG_A0 = 28,
MIPS_REG_A1 = 29,
MIPS_REG_A2 = 30,
MIPS_REG_A3 = 31,
MIPS_REG_AC0 = 32,
MIPS_REG_AC1 = 33,
MIPS_REG_AC2 = 34,
MIPS_REG_AC3 = 35,
MIPS_REG_AT_64 = 36,
MIPS_REG_COP00 = 37,
MIPS_REG_COP01 = 38,
MIPS_REG_COP02 = 39,
MIPS_REG_COP03 = 40,
MIPS_REG_COP04 = 41,
MIPS_REG_COP05 = 42,
MIPS_REG_COP06 = 43,
MIPS_REG_COP07 = 44,
MIPS_REG_COP08 = 45,
MIPS_REG_COP09 = 46,
MIPS_REG_COP20 = 47,
MIPS_REG_COP21 = 48,
MIPS_REG_COP22 = 49,
MIPS_REG_COP23 = 50,
MIPS_REG_COP24 = 51,
MIPS_REG_COP25 = 52,
MIPS_REG_COP26 = 53,
MIPS_REG_COP27 = 54,
MIPS_REG_COP28 = 55,
MIPS_REG_COP29 = 56,
MIPS_REG_COP30 = 57,
MIPS_REG_COP31 = 58,
MIPS_REG_COP32 = 59,
MIPS_REG_COP33 = 60,
MIPS_REG_COP34 = 61,
MIPS_REG_COP35 = 62,
MIPS_REG_COP36 = 63,
MIPS_REG_COP37 = 64,
MIPS_REG_COP38 = 65,
MIPS_REG_COP39 = 66,
MIPS_REG_COP010 = 67,
MIPS_REG_COP011 = 68,
MIPS_REG_COP012 = 69,
MIPS_REG_COP013 = 70,
MIPS_REG_COP014 = 71,
MIPS_REG_COP015 = 72,
MIPS_REG_COP016 = 73,
MIPS_REG_COP017 = 74,
MIPS_REG_COP018 = 75,
MIPS_REG_COP019 = 76,
MIPS_REG_COP020 = 77,
MIPS_REG_COP021 = 78,
MIPS_REG_COP022 = 79,
MIPS_REG_COP023 = 80,
MIPS_REG_COP024 = 81,
MIPS_REG_COP025 = 82,
MIPS_REG_COP026 = 83,
MIPS_REG_COP027 = 84,
MIPS_REG_COP028 = 85,
MIPS_REG_COP029 = 86,
MIPS_REG_COP030 = 87,
MIPS_REG_COP031 = 88,
MIPS_REG_COP210 = 89,
MIPS_REG_COP211 = 90,
MIPS_REG_COP212 = 91,
MIPS_REG_COP213 = 92,
MIPS_REG_COP214 = 93,
MIPS_REG_COP215 = 94,
MIPS_REG_COP216 = 95,
MIPS_REG_COP217 = 96,
MIPS_REG_COP218 = 97,
MIPS_REG_COP219 = 98,
MIPS_REG_COP220 = 99,
MIPS_REG_COP221 = 100,
MIPS_REG_COP222 = 101,
MIPS_REG_COP223 = 102,
MIPS_REG_COP224 = 103,
MIPS_REG_COP225 = 104,
MIPS_REG_COP226 = 105,
MIPS_REG_COP227 = 106,
MIPS_REG_COP228 = 107,
MIPS_REG_COP229 = 108,
MIPS_REG_COP230 = 109,
MIPS_REG_COP231 = 110,
MIPS_REG_COP310 = 111,
MIPS_REG_COP311 = 112,
MIPS_REG_COP312 = 113,
MIPS_REG_COP313 = 114,
MIPS_REG_COP314 = 115,
MIPS_REG_COP315 = 116,
MIPS_REG_COP316 = 117,
MIPS_REG_COP317 = 118,
MIPS_REG_COP318 = 119,
MIPS_REG_COP319 = 120,
MIPS_REG_COP320 = 121,
MIPS_REG_COP321 = 122,
MIPS_REG_COP322 = 123,
MIPS_REG_COP323 = 124,
MIPS_REG_COP324 = 125,
MIPS_REG_COP325 = 126,
MIPS_REG_COP326 = 127,
MIPS_REG_COP327 = 128,
MIPS_REG_COP328 = 129,
MIPS_REG_COP329 = 130,
MIPS_REG_COP330 = 131,
MIPS_REG_COP331 = 132,
MIPS_REG_D0 = 133,
MIPS_REG_D1 = 134,
MIPS_REG_D2 = 135,
MIPS_REG_D3 = 136,
MIPS_REG_D4 = 137,
MIPS_REG_D5 = 138,
MIPS_REG_D6 = 139,
MIPS_REG_D7 = 140,
MIPS_REG_D8 = 141,
MIPS_REG_D9 = 142,
MIPS_REG_D10 = 143,
MIPS_REG_D11 = 144,
MIPS_REG_D12 = 145,
MIPS_REG_D13 = 146,
MIPS_REG_D14 = 147,
MIPS_REG_D15 = 148,
MIPS_REG_DSPOUTFLAG20 = 149,
MIPS_REG_DSPOUTFLAG21 = 150,
MIPS_REG_DSPOUTFLAG22 = 151,
MIPS_REG_DSPOUTFLAG23 = 152,
MIPS_REG_F0 = 153,
MIPS_REG_F1 = 154,
MIPS_REG_F2 = 155,
MIPS_REG_F3 = 156,
MIPS_REG_F4 = 157,
MIPS_REG_F5 = 158,
MIPS_REG_F6 = 159,
MIPS_REG_F7 = 160,
MIPS_REG_F8 = 161,
MIPS_REG_F9 = 162,
MIPS_REG_F10 = 163,
MIPS_REG_F11 = 164,
MIPS_REG_F12 = 165,
MIPS_REG_F13 = 166,
MIPS_REG_F14 = 167,
MIPS_REG_F15 = 168,
MIPS_REG_F16 = 169,
MIPS_REG_F17 = 170,
MIPS_REG_F18 = 171,
MIPS_REG_F19 = 172,
MIPS_REG_F20 = 173,
MIPS_REG_F21 = 174,
MIPS_REG_F22 = 175,
MIPS_REG_F23 = 176,
MIPS_REG_F24 = 177,
MIPS_REG_F25 = 178,
MIPS_REG_F26 = 179,
MIPS_REG_F27 = 180,
MIPS_REG_F28 = 181,
MIPS_REG_F29 = 182,
MIPS_REG_F30 = 183,
MIPS_REG_F31 = 184,
MIPS_REG_FCC0 = 185,
MIPS_REG_FCC1 = 186,
MIPS_REG_FCC2 = 187,
MIPS_REG_FCC3 = 188,
MIPS_REG_FCC4 = 189,
MIPS_REG_FCC5 = 190,
MIPS_REG_FCC6 = 191,
MIPS_REG_FCC7 = 192,
MIPS_REG_FCR0 = 193,
MIPS_REG_FCR1 = 194,
MIPS_REG_FCR2 = 195,
MIPS_REG_FCR3 = 196,
MIPS_REG_FCR4 = 197,
MIPS_REG_FCR5 = 198,
MIPS_REG_FCR6 = 199,
MIPS_REG_FCR7 = 200,
MIPS_REG_FCR8 = 201,
MIPS_REG_FCR9 = 202,
MIPS_REG_FCR10 = 203,
MIPS_REG_FCR11 = 204,
MIPS_REG_FCR12 = 205,
MIPS_REG_FCR13 = 206,
MIPS_REG_FCR14 = 207,
MIPS_REG_FCR15 = 208,
MIPS_REG_FCR16 = 209,
MIPS_REG_FCR17 = 210,
MIPS_REG_FCR18 = 211,
MIPS_REG_FCR19 = 212,
MIPS_REG_FCR20 = 213,
MIPS_REG_FCR21 = 214,
MIPS_REG_FCR22 = 215,
MIPS_REG_FCR23 = 216,
MIPS_REG_FCR24 = 217,
MIPS_REG_FCR25 = 218,
MIPS_REG_FCR26 = 219,
MIPS_REG_FCR27 = 220,
MIPS_REG_FCR28 = 221,
MIPS_REG_FCR29 = 222,
MIPS_REG_FCR30 = 223,
MIPS_REG_FCR31 = 224,
MIPS_REG_FP_64 = 225,
MIPS_REG_F_HI0 = 226,
MIPS_REG_F_HI1 = 227,
MIPS_REG_F_HI2 = 228,
MIPS_REG_F_HI3 = 229,
MIPS_REG_F_HI4 = 230,
MIPS_REG_F_HI5 = 231,
MIPS_REG_F_HI6 = 232,
MIPS_REG_F_HI7 = 233,
MIPS_REG_F_HI8 = 234,
MIPS_REG_F_HI9 = 235,
MIPS_REG_F_HI10 = 236,
MIPS_REG_F_HI11 = 237,
MIPS_REG_F_HI12 = 238,
MIPS_REG_F_HI13 = 239,
MIPS_REG_F_HI14 = 240,
MIPS_REG_F_HI15 = 241,
MIPS_REG_F_HI16 = 242,
MIPS_REG_F_HI17 = 243,
MIPS_REG_F_HI18 = 244,
MIPS_REG_F_HI19 = 245,
MIPS_REG_F_HI20 = 246,
MIPS_REG_F_HI21 = 247,
MIPS_REG_F_HI22 = 248,
MIPS_REG_F_HI23 = 249,
MIPS_REG_F_HI24 = 250,
MIPS_REG_F_HI25 = 251,
MIPS_REG_F_HI26 = 252,
MIPS_REG_F_HI27 = 253,
MIPS_REG_F_HI28 = 254,
MIPS_REG_F_HI29 = 255,
MIPS_REG_F_HI30 = 256,
MIPS_REG_F_HI31 = 257,
MIPS_REG_GP_64 = 258,
MIPS_REG_HI0 = 259,
MIPS_REG_HI1 = 260,
MIPS_REG_HI2 = 261,
MIPS_REG_HI3 = 262,
MIPS_REG_HWR0 = 263,
MIPS_REG_HWR1 = 264,
MIPS_REG_HWR2 = 265,
MIPS_REG_HWR3 = 266,
MIPS_REG_HWR4 = 267,
MIPS_REG_HWR5 = 268,
MIPS_REG_HWR6 = 269,
MIPS_REG_HWR7 = 270,
MIPS_REG_HWR8 = 271,
MIPS_REG_HWR9 = 272,
MIPS_REG_HWR10 = 273,
MIPS_REG_HWR11 = 274,
MIPS_REG_HWR12 = 275,
MIPS_REG_HWR13 = 276,
MIPS_REG_HWR14 = 277,
MIPS_REG_HWR15 = 278,
MIPS_REG_HWR16 = 279,
MIPS_REG_HWR17 = 280,
MIPS_REG_HWR18 = 281,
MIPS_REG_HWR19 = 282,
MIPS_REG_HWR20 = 283,
MIPS_REG_HWR21 = 284,
MIPS_REG_HWR22 = 285,
MIPS_REG_HWR23 = 286,
MIPS_REG_HWR24 = 287,
MIPS_REG_HWR25 = 288,
MIPS_REG_HWR26 = 289,
MIPS_REG_HWR27 = 290,
MIPS_REG_HWR28 = 291,
MIPS_REG_HWR29 = 292,
MIPS_REG_HWR30 = 293,
MIPS_REG_HWR31 = 294,
MIPS_REG_K0 = 295,
MIPS_REG_K1 = 296,
MIPS_REG_LO0 = 297,
MIPS_REG_LO1 = 298,
MIPS_REG_LO2 = 299,
MIPS_REG_LO3 = 300,
MIPS_REG_MPL0 = 301,
MIPS_REG_MPL1 = 302,
MIPS_REG_MPL2 = 303,
MIPS_REG_MSA8 = 304,
MIPS_REG_MSA9 = 305,
MIPS_REG_MSA10 = 306,
MIPS_REG_MSA11 = 307,
MIPS_REG_MSA12 = 308,
MIPS_REG_MSA13 = 309,
MIPS_REG_MSA14 = 310,
MIPS_REG_MSA15 = 311,
MIPS_REG_MSA16 = 312,
MIPS_REG_MSA17 = 313,
MIPS_REG_MSA18 = 314,
MIPS_REG_MSA19 = 315,
MIPS_REG_MSA20 = 316,
MIPS_REG_MSA21 = 317,
MIPS_REG_MSA22 = 318,
MIPS_REG_MSA23 = 319,
MIPS_REG_MSA24 = 320,
MIPS_REG_MSA25 = 321,
MIPS_REG_MSA26 = 322,
MIPS_REG_MSA27 = 323,
MIPS_REG_MSA28 = 324,
MIPS_REG_MSA29 = 325,
MIPS_REG_MSA30 = 326,
MIPS_REG_MSA31 = 327,
MIPS_REG_P0 = 328,
MIPS_REG_P1 = 329,
MIPS_REG_P2 = 330,
MIPS_REG_RA_64 = 331,
MIPS_REG_S0 = 332,
MIPS_REG_S1 = 333,
MIPS_REG_S2 = 334,
MIPS_REG_S3 = 335,
MIPS_REG_S4 = 336,
MIPS_REG_S5 = 337,
MIPS_REG_S6 = 338,
MIPS_REG_S7 = 339,
MIPS_REG_SP_64 = 340,
MIPS_REG_T0 = 341,
MIPS_REG_T1 = 342,
MIPS_REG_T2 = 343,
MIPS_REG_T3 = 344,
MIPS_REG_T4 = 345,
MIPS_REG_T5 = 346,
MIPS_REG_T6 = 347,
MIPS_REG_T7 = 348,
MIPS_REG_T8 = 349,
MIPS_REG_T9 = 350,
MIPS_REG_V0 = 351,
MIPS_REG_V1 = 352,
MIPS_REG_W0 = 353,
MIPS_REG_W1 = 354,
MIPS_REG_W2 = 355,
MIPS_REG_W3 = 356,
MIPS_REG_W4 = 357,
MIPS_REG_W5 = 358,
MIPS_REG_W6 = 359,
MIPS_REG_W7 = 360,
MIPS_REG_W8 = 361,
MIPS_REG_W9 = 362,
MIPS_REG_W10 = 363,
MIPS_REG_W11 = 364,
MIPS_REG_W12 = 365,
MIPS_REG_W13 = 366,
MIPS_REG_W14 = 367,
MIPS_REG_W15 = 368,
MIPS_REG_W16 = 369,
MIPS_REG_W17 = 370,
MIPS_REG_W18 = 371,
MIPS_REG_W19 = 372,
MIPS_REG_W20 = 373,
MIPS_REG_W21 = 374,
MIPS_REG_W22 = 375,
MIPS_REG_W23 = 376,
MIPS_REG_W24 = 377,
MIPS_REG_W25 = 378,
MIPS_REG_W26 = 379,
MIPS_REG_W27 = 380,
MIPS_REG_W28 = 381,
MIPS_REG_W29 = 382,
MIPS_REG_W30 = 383,
MIPS_REG_W31 = 384,
MIPS_REG_ZERO_64 = 385,
MIPS_REG_A0_NM = 386,
MIPS_REG_A1_NM = 387,
MIPS_REG_A2_NM = 388,
MIPS_REG_A3_NM = 389,
MIPS_REG_A4_NM = 390,
MIPS_REG_A5_NM = 391,
MIPS_REG_A6_NM = 392,
MIPS_REG_A7_NM = 393,
MIPS_REG_COP0SEL_BADINST = 394,
MIPS_REG_COP0SEL_BADINSTRP = 395,
MIPS_REG_COP0SEL_BADINSTRX = 396,
MIPS_REG_COP0SEL_BADVADDR = 397,
MIPS_REG_COP0SEL_BEVVA = 398,
MIPS_REG_COP0SEL_CACHEERR = 399,
MIPS_REG_COP0SEL_CAUSE = 400,
MIPS_REG_COP0SEL_CDMMBASE = 401,
MIPS_REG_COP0SEL_CMGCRBASE = 402,
MIPS_REG_COP0SEL_COMPARE = 403,
MIPS_REG_COP0SEL_CONFIG = 404,
MIPS_REG_COP0SEL_CONTEXT = 405,
MIPS_REG_COP0SEL_CONTEXTCONFIG = 406,
MIPS_REG_COP0SEL_COUNT = 407,
MIPS_REG_COP0SEL_DDATAHI = 408,
MIPS_REG_COP0SEL_DDATALO = 409,
MIPS_REG_COP0SEL_DEBUG = 410,
MIPS_REG_COP0SEL_DEBUGCONTEXTID = 411,
MIPS_REG_COP0SEL_DEPC = 412,
MIPS_REG_COP0SEL_DESAVE = 413,
MIPS_REG_COP0SEL_DTAGHI = 414,
MIPS_REG_COP0SEL_DTAGLO = 415,
MIPS_REG_COP0SEL_EBASE = 416,
MIPS_REG_COP0SEL_ENTRYHI = 417,
MIPS_REG_COP0SEL_EPC = 418,
MIPS_REG_COP0SEL_ERRCTL = 419,
MIPS_REG_COP0SEL_ERROREPC = 420,
MIPS_REG_COP0SEL_GLOBALNUMBER = 421,
MIPS_REG_COP0SEL_GTOFFSET = 422,
MIPS_REG_COP0SEL_HWRENA = 423,
MIPS_REG_COP0SEL_IDATAHI = 424,
MIPS_REG_COP0SEL_IDATALO = 425,
MIPS_REG_COP0SEL_INDEX = 426,
MIPS_REG_COP0SEL_INTCTL = 427,
MIPS_REG_COP0SEL_ITAGHI = 428,
MIPS_REG_COP0SEL_ITAGLO = 429,
MIPS_REG_COP0SEL_LLADDR = 430,
MIPS_REG_COP0SEL_MAAR = 431,
MIPS_REG_COP0SEL_MAARI = 432,
MIPS_REG_COP0SEL_MEMORYMAPID = 433,
MIPS_REG_COP0SEL_MVPCONTROL = 434,
MIPS_REG_COP0SEL_NESTEDEPC = 435,
MIPS_REG_COP0SEL_NESTEDEXC = 436,
MIPS_REG_COP0SEL_PAGEGRAIN = 437,
MIPS_REG_COP0SEL_PAGEMASK = 438,
MIPS_REG_COP0SEL_PRID = 439,
MIPS_REG_COP0SEL_PWBASE = 440,
MIPS_REG_COP0SEL_PWCTL = 441,
MIPS_REG_COP0SEL_PWFIELD = 442,
MIPS_REG_COP0SEL_PWSIZE = 443,
MIPS_REG_COP0SEL_RANDOM = 444,
MIPS_REG_COP0SEL_SRSCTL = 445,
MIPS_REG_COP0SEL_SRSMAP = 446,
MIPS_REG_COP0SEL_STATUS = 447,
MIPS_REG_COP0SEL_TCBIND = 448,
MIPS_REG_COP0SEL_TCCONTEXT = 449,
MIPS_REG_COP0SEL_TCHALT = 450,
MIPS_REG_COP0SEL_TCOPT = 451,
MIPS_REG_COP0SEL_TCRESTART = 452,
MIPS_REG_COP0SEL_TCSCHEDULE = 453,
MIPS_REG_COP0SEL_TCSCHEFBACK = 454,
MIPS_REG_COP0SEL_TCSTATUS = 455,
MIPS_REG_COP0SEL_TRACECONTROL = 456,
MIPS_REG_COP0SEL_TRACEDBPC = 457,
MIPS_REG_COP0SEL_TRACEIBPC = 458,
MIPS_REG_COP0SEL_USERLOCAL = 459,
MIPS_REG_COP0SEL_VIEW_IPL = 460,
MIPS_REG_COP0SEL_VIEW_RIPL = 461,
MIPS_REG_COP0SEL_VPCONTROL = 462,
MIPS_REG_COP0SEL_VPECONTROL = 463,
MIPS_REG_COP0SEL_VPEOPT = 464,
MIPS_REG_COP0SEL_VPESCHEDULE = 465,
MIPS_REG_COP0SEL_VPESCHEFBACK = 466,
MIPS_REG_COP0SEL_WIRED = 467,
MIPS_REG_COP0SEL_XCONTEXT = 468,
MIPS_REG_COP0SEL_XCONTEXTCONFIG = 469,
MIPS_REG_COP0SEL_YQMASK = 470,
MIPS_REG_K0_NM = 471,
MIPS_REG_K1_NM = 472,
MIPS_REG_S0_NM = 473,
MIPS_REG_S1_NM = 474,
MIPS_REG_S2_NM = 475,
MIPS_REG_S3_NM = 476,
MIPS_REG_S4_NM = 477,
MIPS_REG_S5_NM = 478,
MIPS_REG_S6_NM = 479,
MIPS_REG_S7_NM = 480,
MIPS_REG_T0_NM = 481,
MIPS_REG_T1_NM = 482,
MIPS_REG_T2_NM = 483,
MIPS_REG_T3_NM = 484,
MIPS_REG_T4_NM = 485,
MIPS_REG_T5_NM = 486,
MIPS_REG_T8_NM = 487,
MIPS_REG_T9_NM = 488,
MIPS_REG_A0_64 = 489,
MIPS_REG_A1_64 = 490,
MIPS_REG_A2_64 = 491,
MIPS_REG_A3_64 = 492,
MIPS_REG_AC0_64 = 493,
MIPS_REG_COP0SEL_CONFIG1 = 494,
MIPS_REG_COP0SEL_CONFIG2 = 495,
MIPS_REG_COP0SEL_CONFIG3 = 496,
MIPS_REG_COP0SEL_CONFIG4 = 497,
MIPS_REG_COP0SEL_CONFIG5 = 498,
MIPS_REG_COP0SEL_DEBUG2 = 499,
MIPS_REG_COP0SEL_ENTRYLO0 = 500,
MIPS_REG_COP0SEL_ENTRYLO1 = 501,
MIPS_REG_COP0SEL_GUESTCTL0 = 502,
MIPS_REG_COP0SEL_GUESTCTL1 = 503,
MIPS_REG_COP0SEL_GUESTCTL2 = 504,
MIPS_REG_COP0SEL_GUESTCTL3 = 505,
MIPS_REG_COP0SEL_KSCRATCH1 = 506,
MIPS_REG_COP0SEL_KSCRATCH2 = 507,
MIPS_REG_COP0SEL_KSCRATCH3 = 508,
MIPS_REG_COP0SEL_KSCRATCH4 = 509,
MIPS_REG_COP0SEL_KSCRATCH5 = 510,
MIPS_REG_COP0SEL_KSCRATCH6 = 511,
MIPS_REG_COP0SEL_MVPCONF0 = 512,
MIPS_REG_COP0SEL_MVPCONF1 = 513,
MIPS_REG_COP0SEL_PERFCNT0 = 514,
MIPS_REG_COP0SEL_PERFCNT1 = 515,
MIPS_REG_COP0SEL_PERFCNT2 = 516,
MIPS_REG_COP0SEL_PERFCNT3 = 517,
MIPS_REG_COP0SEL_PERFCNT4 = 518,
MIPS_REG_COP0SEL_PERFCNT5 = 519,
MIPS_REG_COP0SEL_PERFCNT6 = 520,
MIPS_REG_COP0SEL_PERFCNT7 = 521,
MIPS_REG_COP0SEL_PERFCTL0 = 522,
MIPS_REG_COP0SEL_PERFCTL1 = 523,
MIPS_REG_COP0SEL_PERFCTL2 = 524,
MIPS_REG_COP0SEL_PERFCTL3 = 525,
MIPS_REG_COP0SEL_PERFCTL4 = 526,
MIPS_REG_COP0SEL_PERFCTL5 = 527,
MIPS_REG_COP0SEL_PERFCTL6 = 528,
MIPS_REG_COP0SEL_PERFCTL7 = 529,
MIPS_REG_COP0SEL_SEGCTL0 = 530,
MIPS_REG_COP0SEL_SEGCTL1 = 531,
MIPS_REG_COP0SEL_SEGCTL2 = 532,
MIPS_REG_COP0SEL_SRSCONF0 = 533,
MIPS_REG_COP0SEL_SRSCONF1 = 534,
MIPS_REG_COP0SEL_SRSCONF2 = 535,
MIPS_REG_COP0SEL_SRSCONF3 = 536,
MIPS_REG_COP0SEL_SRSCONF4 = 537,
MIPS_REG_COP0SEL_SRSMAP2 = 538,
MIPS_REG_COP0SEL_TRACECONTROL2 = 539,
MIPS_REG_COP0SEL_TRACECONTROL3 = 540,
MIPS_REG_COP0SEL_USERTRACEDATA1 = 541,
MIPS_REG_COP0SEL_USERTRACEDATA2 = 542,
MIPS_REG_COP0SEL_VPECONF0 = 543,
MIPS_REG_COP0SEL_VPECONF1 = 544,
MIPS_REG_COP0SEL_WATCHHI0 = 545,
MIPS_REG_COP0SEL_WATCHHI1 = 546,
MIPS_REG_COP0SEL_WATCHHI2 = 547,
MIPS_REG_COP0SEL_WATCHHI3 = 548,
MIPS_REG_COP0SEL_WATCHHI4 = 549,
MIPS_REG_COP0SEL_WATCHHI5 = 550,
MIPS_REG_COP0SEL_WATCHHI6 = 551,
MIPS_REG_COP0SEL_WATCHHI7 = 552,
MIPS_REG_COP0SEL_WATCHHI8 = 553,
MIPS_REG_COP0SEL_WATCHHI9 = 554,
MIPS_REG_COP0SEL_WATCHHI10 = 555,
MIPS_REG_COP0SEL_WATCHHI11 = 556,
MIPS_REG_COP0SEL_WATCHHI12 = 557,
MIPS_REG_COP0SEL_WATCHHI13 = 558,
MIPS_REG_COP0SEL_WATCHHI14 = 559,
MIPS_REG_COP0SEL_WATCHHI15 = 560,
MIPS_REG_COP0SEL_WATCHLO0 = 561,
MIPS_REG_COP0SEL_WATCHLO1 = 562,
MIPS_REG_COP0SEL_WATCHLO2 = 563,
MIPS_REG_COP0SEL_WATCHLO3 = 564,
MIPS_REG_COP0SEL_WATCHLO4 = 565,
MIPS_REG_COP0SEL_WATCHLO5 = 566,
MIPS_REG_COP0SEL_WATCHLO6 = 567,
MIPS_REG_COP0SEL_WATCHLO7 = 568,
MIPS_REG_COP0SEL_WATCHLO8 = 569,
MIPS_REG_COP0SEL_WATCHLO9 = 570,
MIPS_REG_COP0SEL_WATCHLO10 = 571,
MIPS_REG_COP0SEL_WATCHLO11 = 572,
MIPS_REG_COP0SEL_WATCHLO12 = 573,
MIPS_REG_COP0SEL_WATCHLO13 = 574,
MIPS_REG_COP0SEL_WATCHLO14 = 575,
MIPS_REG_COP0SEL_WATCHLO15 = 576,
MIPS_REG_D0_64 = 577,
MIPS_REG_D1_64 = 578,
MIPS_REG_D2_64 = 579,
MIPS_REG_D3_64 = 580,
MIPS_REG_D4_64 = 581,
MIPS_REG_D5_64 = 582,
MIPS_REG_D6_64 = 583,
MIPS_REG_D7_64 = 584,
MIPS_REG_D8_64 = 585,
MIPS_REG_D9_64 = 586,
MIPS_REG_D10_64 = 587,
MIPS_REG_D11_64 = 588,
MIPS_REG_D12_64 = 589,
MIPS_REG_D13_64 = 590,
MIPS_REG_D14_64 = 591,
MIPS_REG_D15_64 = 592,
MIPS_REG_D16_64 = 593,
MIPS_REG_D17_64 = 594,
MIPS_REG_D18_64 = 595,
MIPS_REG_D19_64 = 596,
MIPS_REG_D20_64 = 597,
MIPS_REG_D21_64 = 598,
MIPS_REG_D22_64 = 599,
MIPS_REG_D23_64 = 600,
MIPS_REG_D24_64 = 601,
MIPS_REG_D25_64 = 602,
MIPS_REG_D26_64 = 603,
MIPS_REG_D27_64 = 604,
MIPS_REG_D28_64 = 605,
MIPS_REG_D29_64 = 606,
MIPS_REG_D30_64 = 607,
MIPS_REG_D31_64 = 608,
MIPS_REG_DSPOUTFLAG16_19 = 609,
MIPS_REG_HI0_64 = 610,
MIPS_REG_K0_64 = 611,
MIPS_REG_K1_64 = 612,
MIPS_REG_LO0_64 = 613,
MIPS_REG_S0_64 = 614,
MIPS_REG_S1_64 = 615,
MIPS_REG_S2_64 = 616,
MIPS_REG_S3_64 = 617,
MIPS_REG_S4_64 = 618,
MIPS_REG_S5_64 = 619,
MIPS_REG_S6_64 = 620,
MIPS_REG_S7_64 = 621,
MIPS_REG_T0_64 = 622,
MIPS_REG_T1_64 = 623,
MIPS_REG_T2_64 = 624,
MIPS_REG_T3_64 = 625,
MIPS_REG_T4_64 = 626,
MIPS_REG_T5_64 = 627,
MIPS_REG_T6_64 = 628,
MIPS_REG_T7_64 = 629,
MIPS_REG_T8_64 = 630,
MIPS_REG_T9_64 = 631,
MIPS_REG_V0_64 = 632,
MIPS_REG_V1_64 = 633,
MIPS_REG_COP0SEL_GUESTCTL0EXT = 634,
MIPS_REG_ENDING, // 635

17748
arch/Mips/MipsGenDisassemblerTables.inc
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File diff suppressed because it is too large Load Diff

9263
arch/Mips/MipsGenInstrInfo.inc
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File diff suppressed because it is too large Load Diff

3903
arch/Mips/MipsGenRegisterInfo.inc
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File diff suppressed because it is too large Load Diff

119
arch/Mips/MipsGenSubtargetInfo.inc
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@ -1,52 +1,83 @@
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|* *|
|*Subtarget Enumeration Source Fragment *|
|* *|
|* Automatically generated file, do not edit! *|
|* *|
\*===----------------------------------------------------------------------===*/
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
#ifdef GET_SUBTARGETINFO_ENUM
#undef GET_SUBTARGETINFO_ENUM
#define Mips_FeatureCnMips (1ULL << 0)
#define Mips_FeatureDSP (1ULL << 1)
#define Mips_FeatureDSPR2 (1ULL << 2)
#define Mips_FeatureFP64Bit (1ULL << 3)
#define Mips_FeatureFPXX (1ULL << 4)
#define Mips_FeatureGP64Bit (1ULL << 5)
#define Mips_FeatureMSA (1ULL << 6)
#define Mips_FeatureMicroMips (1ULL << 7)
#define Mips_FeatureMips1 (1ULL << 8)
#define Mips_FeatureMips2 (1ULL << 9)
#define Mips_FeatureMips3 (1ULL << 10)
#define Mips_FeatureMips3_32 (1ULL << 11)
#define Mips_FeatureMips3_32r2 (1ULL << 12)
#define Mips_FeatureMips4 (1ULL << 13)
#define Mips_FeatureMips4_32 (1ULL << 14)
#define Mips_FeatureMips4_32r2 (1ULL << 15)
#define Mips_FeatureMips5 (1ULL << 16)
#define Mips_FeatureMips5_32r2 (1ULL << 17)
#define Mips_FeatureMips16 (1ULL << 18)
#define Mips_FeatureMips32 (1ULL << 19)
#define Mips_FeatureMips32r2 (1ULL << 20)
#define Mips_FeatureMips32r3 (1ULL << 21)
#define Mips_FeatureMips32r5 (1ULL << 22)
#define Mips_FeatureMips32r6 (1ULL << 23)
#define Mips_FeatureMips64 (1ULL << 24)
#define Mips_FeatureMips64r2 (1ULL << 25)
#define Mips_FeatureMips64r3 (1ULL << 26)
#define Mips_FeatureMips64r5 (1ULL << 27)
#define Mips_FeatureMips64r6 (1ULL << 28)
#define Mips_FeatureNaN2008 (1ULL << 29)
#define Mips_FeatureNoABICalls (1ULL << 30)
#define Mips_FeatureNoOddSPReg (1ULL << 31)
#define Mips_FeatureSingleFloat (1ULL << 32)
#define Mips_FeatureVFPU (1ULL << 33)
enum {
Mips_FeatureAbs2008 = 0,
Mips_FeatureCRC = 1,
Mips_FeatureCnMips = 2,
Mips_FeatureCnMipsP = 3,
Mips_FeatureDSP = 4,
Mips_FeatureDSPR2 = 5,
Mips_FeatureDSPR3 = 6,
Mips_FeatureEVA = 7,
Mips_FeatureFP64Bit = 8,
Mips_FeatureFPXX = 9,
Mips_FeatureGINV = 10,
Mips_FeatureGP64Bit = 11,
Mips_FeatureI7200 = 12,
Mips_FeatureLongCalls = 13,
Mips_FeatureMSA = 14,
Mips_FeatureMT = 15,
Mips_FeatureMicroMips = 16,
Mips_FeatureMips1 = 17,
Mips_FeatureMips2 = 18,
Mips_FeatureMips3 = 19,
Mips_FeatureMips3D = 20,
Mips_FeatureMips3_32 = 21,
Mips_FeatureMips3_32r2 = 22,
Mips_FeatureMips4 = 23,
Mips_FeatureMips4_32 = 24,
Mips_FeatureMips4_32r2 = 25,
Mips_FeatureMips5 = 26,
Mips_FeatureMips5_32r2 = 27,
Mips_FeatureMips16 = 28,
Mips_FeatureMips32 = 29,
Mips_FeatureMips32r2 = 30,
Mips_FeatureMips32r3 = 31,
Mips_FeatureMips32r5 = 32,
Mips_FeatureMips32r6 = 33,
Mips_FeatureMips64 = 34,
Mips_FeatureMips64r2 = 35,
Mips_FeatureMips64r3 = 36,
Mips_FeatureMips64r5 = 37,
Mips_FeatureMips64r6 = 38,
Mips_FeatureNMS1 = 39,
Mips_FeatureNaN2008 = 40,
Mips_FeatureNanoMips = 41,
Mips_FeatureNoABICalls = 42,
Mips_FeatureNoMadd4 = 43,
Mips_FeatureNoOddSPReg = 44,
Mips_FeaturePCRel = 45,
Mips_FeaturePTR64Bit = 46,
Mips_FeatureRelax = 47,
Mips_FeatureSingleFloat = 48,
Mips_FeatureSoftFloat = 49,
Mips_FeatureSym32 = 50,
Mips_FeatureTLB = 51,
Mips_FeatureUseAbsoluteJumpTables = 52,
Mips_FeatureUseIndirectJumpsHazard = 53,
Mips_FeatureUseTCCInDIV = 54,
Mips_FeatureVFPU = 55,
Mips_FeatureVirt = 56,
Mips_FeatureXGOT = 57,
Mips_FeatureXformHw110880 = 58,
Mips_ImplP5600 = 59,
Mips_NumSubtargetFeatures = 60
};
#endif // GET_SUBTARGETINFO_ENUM

865
arch/Mips/MipsInstPrinter.c
View File

@ -1,9 +1,22 @@
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2023 */
/* Automatically translated source file from LLVM. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Only small edits allowed. */
/* For multiple similar edits, please create a Patch for the translator. */
/* Capstone's C++ file translator: */
/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
//===-- MipsInstPrinter.cpp - Convert Mips MCInst to assembly syntax ------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
@ -11,251 +24,257 @@
//
//===----------------------------------------------------------------------===//
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
#ifdef CAPSTONE_HAS_MIPS
#include <capstone/platform.h>
#include <stdlib.h>
#include <stdio.h> // debug
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <capstone/platform.h>
#include "MipsInstPrinter.h"
#include "../../MCInst.h"
#include "../../utils.h"
#include "../../SStream.h"
#include "../../MCRegisterInfo.h"
#include "MipsMapping.h"
#include "MipsInstPrinter.h"
static void printUnsignedImm(MCInst *MI, int opNum, SStream *O);
static char *printAliasInstr(MCInst *MI, SStream *O, void *info);
static char *printAlias(MCInst *MI, SStream *OS);
// These enumeration declarations were originally in MipsInstrInfo.h but
// had to be moved here to avoid circular dependencies between
// LLVMMipsCodeGen and LLVMMipsAsmPrinter.
// Mips Condition Codes
typedef enum Mips_CondCode {
// To be used with float branch True
Mips_FCOND_F,
Mips_FCOND_UN,
Mips_FCOND_OEQ,
Mips_FCOND_UEQ,
Mips_FCOND_OLT,
Mips_FCOND_ULT,
Mips_FCOND_OLE,
Mips_FCOND_ULE,
Mips_FCOND_SF,
Mips_FCOND_NGLE,
Mips_FCOND_SEQ,
Mips_FCOND_NGL,
Mips_FCOND_LT,
Mips_FCOND_NGE,
Mips_FCOND_LE,
Mips_FCOND_NGT,
// To be used with float branch False
// This conditions have the same mnemonic as the
// above ones, but are used with a branch False;
Mips_FCOND_T,
Mips_FCOND_OR,
Mips_FCOND_UNE,
Mips_FCOND_ONE,
Mips_FCOND_UGE,
Mips_FCOND_OGE,
Mips_FCOND_UGT,
Mips_FCOND_OGT,
Mips_FCOND_ST,
Mips_FCOND_GLE,
Mips_FCOND_SNE,
Mips_FCOND_GL,
Mips_FCOND_NLT,
Mips_FCOND_GE,
Mips_FCOND_NLE,
Mips_FCOND_GT
} Mips_CondCode;
#define GET_SUBTARGETINFO_ENUM
#include "MipsGenSubtargetInfo.inc"
#define GET_INSTRINFO_ENUM
#include "MipsGenInstrInfo.inc"
static const char *getRegisterName(unsigned RegNo);
static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI);
#define GET_REGINFO_ENUM
#include "MipsGenRegisterInfo.inc"
static void set_mem_access(MCInst *MI, bool status)
#define CONCAT(a, b) CONCAT_(a, b)
#define CONCAT_(a, b) a##_##b
#define DEBUG_TYPE "asm-printer"
#define PRINT_ALIAS_INSTR
#include "MipsGenAsmWriter.inc"
static bool isReg(const MCInst *MI, unsigned OpNo, unsigned R)
{
MI->csh->doing_mem = status;
if (MI->csh->detail_opt != CS_OPT_ON)
return;
if (status) {
MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_MEM;
MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.base = MIPS_REG_INVALID;
MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.disp = 0;
} else {
// done, create the next operand slot
MI->flat_insn->detail->mips.op_count++;
}
return MCOperand_getReg(MCInst_getOperand((MCInst *)MI, (OpNo))) == R;
}
static bool isReg(MCInst *MI, unsigned OpNo, unsigned R)
{
return (MCOperand_isReg(MCInst_getOperand(MI, OpNo)) &&
MCOperand_getReg(MCInst_getOperand(MI, OpNo)) == R);
}
static const char* MipsFCCToString(Mips_CondCode CC)
static const char *MipsFCCToString(Mips_CondCode CC)
{
switch (CC) {
default: return 0; // never reach
case Mips_FCOND_F:
case Mips_FCOND_T: return "f";
case Mips_FCOND_UN:
case Mips_FCOND_OR: return "un";
case Mips_FCOND_OEQ:
case Mips_FCOND_UNE: return "eq";
case Mips_FCOND_UEQ:
case Mips_FCOND_ONE: return "ueq";
case Mips_FCOND_OLT:
case Mips_FCOND_UGE: return "olt";
case Mips_FCOND_ULT:
case Mips_FCOND_OGE: return "ult";
case Mips_FCOND_OLE:
case Mips_FCOND_UGT: return "ole";
case Mips_FCOND_ULE:
case Mips_FCOND_OGT: return "ule";
case Mips_FCOND_SF:
case Mips_FCOND_ST: return "sf";
case Mips_FCOND_NGLE:
case Mips_FCOND_GLE: return "ngle";
case Mips_FCOND_SEQ:
case Mips_FCOND_SNE: return "seq";
case Mips_FCOND_NGL:
case Mips_FCOND_GL: return "ngl";
case Mips_FCOND_LT:
case Mips_FCOND_NLT: return "lt";
case Mips_FCOND_NGE:
case Mips_FCOND_GE: return "nge";
case Mips_FCOND_LE:
case Mips_FCOND_NLE: return "le";
case Mips_FCOND_NGT:
case Mips_FCOND_GT: return "ngt";
case Mips_FCOND_F:
case Mips_FCOND_T:
return "f";
case Mips_FCOND_UN:
case Mips_FCOND_OR:
return "un";
case Mips_FCOND_OEQ:
case Mips_FCOND_UNE:
return "eq";
case Mips_FCOND_UEQ:
case Mips_FCOND_ONE:
return "ueq";
case Mips_FCOND_OLT:
case Mips_FCOND_UGE:
return "olt";
case Mips_FCOND_ULT:
case Mips_FCOND_OGE:
return "ult";
case Mips_FCOND_OLE:
case Mips_FCOND_UGT:
return "ole";
case Mips_FCOND_ULE:
case Mips_FCOND_OGT:
return "ule";
case Mips_FCOND_SF:
case Mips_FCOND_ST:
return "sf";
case Mips_FCOND_NGLE:
case Mips_FCOND_GLE:
return "ngle";
case Mips_FCOND_SEQ:
case Mips_FCOND_SNE:
return "seq";
case Mips_FCOND_NGL:
case Mips_FCOND_GL:
return "ngl";
case Mips_FCOND_LT:
case Mips_FCOND_NLT:
return "lt";
case Mips_FCOND_NGE:
case Mips_FCOND_GE:
return "nge";
case Mips_FCOND_LE:
case Mips_FCOND_NLE:
return "le";
case Mips_FCOND_NGT:
case Mips_FCOND_GT:
return "ngt";
}
assert(0 && "Impossible condition code!");
return "";
}
const char *Mips_LLVM_getRegisterName(unsigned RegNo, bool noRegName);
static void printRegName(MCInst *MI, SStream *OS, MCRegister Reg)
{
int syntax_opt = MI->csh->syntax;
if (!(syntax_opt & CS_OPT_SYNTAX_NO_DOLLAR)) {
SStream_concat1(OS, '$');
}
SStream_concat0(OS, Mips_LLVM_getRegisterName(Reg, syntax_opt & CS_OPT_SYNTAX_NOREGNAME));
}
void Mips_LLVM_printInst(MCInst *MI, uint64_t Address, SStream *O) {
bool useAliasDetails = map_use_alias_details(MI);
if (!useAliasDetails) {
SStream_Close(O);
printInstruction(MI, Address, O);
SStream_Open(O);
map_set_fill_detail_ops(MI, false);
}
if (printAliasInstr(MI, Address, O) ||
printAlias4(MI, Address, O)) {
MCInst_setIsAlias(MI, true);
} else {
printInstruction(MI, Address, O);
}
if (!useAliasDetails) {
map_set_fill_detail_ops(MI, true);
}
}
static void printRegName(SStream *OS, unsigned RegNo)
void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
SStream_concat(OS, "$%s", getRegisterName(RegNo));
}
void Mips_printInst(MCInst *MI, SStream *O, void *info)
{
char *mnem;
switch (MCInst_getOpcode(MI)) {
default: break;
case Mips_Save16:
case Mips_SaveX16:
case Mips_Restore16:
case Mips_RestoreX16:
return;
default:
break;
case Mips_AND16_NM:
case Mips_XOR16_NM:
case Mips_OR16_NM:
if (MCInst_getNumOperands(MI) == 2 && OpNo == 2)
OpNo = 0; // rt, rs -> rt, rs, rt
break;
case Mips_ADDu4x4_NM:
case Mips_MUL4x4_NM:
if (MCInst_getNumOperands(MI) == 2 && OpNo > 0)
OpNo = OpNo - 1; // rt, rs -> rt, rt, rs
break;
}
// Try to print any aliases first.
mnem = printAliasInstr(MI, O, info);
if (!mnem) {
mnem = printAlias(MI, O);
if (!mnem) {
printInstruction(MI, O, NULL);
}
}
if (mnem) {
// fixup instruction id due to the change in alias instruction
MCInst_setOpcodePub(MI, Mips_map_insn(mnem));
cs_mem_free(mnem);
}
}
static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
MCOperand *Op;
if (OpNo >= MI->size)
return;
Op = MCInst_getOperand(MI, OpNo);
MCOperand *Op = MCInst_getOperand(MI, (OpNo));
if (MCOperand_isReg(Op)) {
unsigned int reg = MCOperand_getReg(Op);
printRegName(O, reg);
reg = Mips_map_register(reg);
if (MI->csh->detail_opt) {
if (MI->csh->doing_mem) {
MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.base = reg;
} else {
MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_REG;
MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].reg = reg;
MI->flat_insn->detail->mips.op_count++;
}
}
} else if (MCOperand_isImm(Op)) {
int64_t imm = MCOperand_getImm(Op);
if (MI->csh->doing_mem) {
if (imm) { // only print Imm offset if it is not 0
printInt64(O, imm);
}
if (MI->csh->detail_opt)
MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.disp = imm;
} else {
printInt64(O, imm);
add_cs_detail(MI, Mips_OP_GROUP_Operand, OpNo);
printRegName(MI, O, MCOperand_getReg(Op));
return;
}
if (MI->csh->detail_opt) {
MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_IMM;
MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].imm = imm;
MI->flat_insn->detail->mips.op_count++;
}
if (MCOperand_isImm(Op)) {
switch (MCInst_getOpcode(MI)) {
case Mips_LI48_NM:
case Mips_ANDI16_NM:
case Mips_ANDI_NM:
case Mips_ORI_NM:
case Mips_XORI_NM:
case Mips_TEQ_NM:
case Mips_TNE_NM:
case Mips_SIGRIE_NM:
case Mips_SDBBP_NM:
case Mips_SDBBP16_NM:
case Mips_BREAK_NM:
case Mips_BREAK16_NM:
case Mips_SYSCALL_NM:
case Mips_SYSCALL16_NM:
case Mips_WAIT_NM:
CONCAT(printUImm, CONCAT(32, 0))
(MI, OpNo, O);
break;
default:
add_cs_detail(MI, Mips_OP_GROUP_Operand, OpNo);
printInt64(O, MCOperand_getImm(Op));
break;
}
return;
}
}
static void printUnsignedImm(MCInst *MI, int opNum, SStream *O)
static void printJumpOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
MCOperand *MO = MCInst_getOperand(MI, opNum);
if (MCOperand_isImm(MO)) {
int64_t imm = MCOperand_getImm(MO);
printInt64(O, imm);
add_cs_detail(MI, Mips_OP_GROUP_JumpOperand, OpNo);
MCOperand *Op = MCInst_getOperand(MI, (OpNo));
if (MCOperand_isReg(Op))
return printRegName(MI, O, MCOperand_getReg(Op));
if (MI->csh->detail_opt) {
MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_IMM;
MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].imm = (unsigned short int)imm;
MI->flat_insn->detail->mips.op_count++;
}
} else
printOperand(MI, opNum, O);
printInt64(O, MCOperand_getImm(Op));
}
static void printUnsignedImm8(MCInst *MI, int opNum, SStream *O)
static void printBranchOperand(MCInst *MI, uint64_t Address, unsigned OpNo, SStream *O)
{
MCOperand *MO = MCInst_getOperand(MI, opNum);
if (MCOperand_isImm(MO)) {
uint8_t imm = (uint8_t)MCOperand_getImm(MO);
if (imm > HEX_THRESHOLD)
SStream_concat(O, "0x%x", imm);
else
SStream_concat(O, "%u", imm);
if (MI->csh->detail_opt) {
MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_IMM;
MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].imm = imm;
MI->flat_insn->detail->mips.op_count++;
}
} else
printOperand(MI, opNum, O);
add_cs_detail(MI, Mips_OP_GROUP_BranchOperand, OpNo);
MCOperand *Op = MCInst_getOperand(MI, (OpNo));
if (MCOperand_isReg(Op))
return printRegName(MI, O, MCOperand_getReg(Op));
uint64_t Target = Address + MCOperand_getImm(Op);
printInt64(O, Target);
}
#define DEFINE_printUImm(Bits) \
static void CONCAT(printUImm, CONCAT(Bits, 0))(MCInst * MI, int opNum, \
SStream *O) \
{ \
add_cs_detail(MI, CONCAT(Mips_OP_GROUP_UImm, CONCAT(Bits, 0)), opNum); \
MCOperand *MO = MCInst_getOperand(MI, (opNum)); \
if (MCOperand_isImm(MO)) { \
uint64_t Imm = MCOperand_getImm(MO); \
Imm &= (((uint64_t)1) << Bits) - 1; \
printUInt64(O, Imm); \
return; \
} \
MCOperand *Op = MCInst_getOperand(MI, (opNum)); \
printRegName(MI, O, MCOperand_getReg(Op)); \
}
#define DEFINE_printUImm_2(Bits, Offset) \
static void CONCAT(printUImm, CONCAT(Bits, Offset))(MCInst * MI, int opNum, \
SStream *O) \
{ \
add_cs_detail(MI, CONCAT(Mips_OP_GROUP_UImm, CONCAT(Bits, Offset)), \
opNum); \
MCOperand *MO = MCInst_getOperand(MI, (opNum)); \
if (MCOperand_isImm(MO)) { \
uint64_t Imm = MCOperand_getImm(MO); \
Imm -= Offset; \
Imm &= (1 << Bits) - 1; \
Imm += Offset; \
printUInt64(O, Imm); \
return; \
} \
MCOperand *Op = MCInst_getOperand(MI, (opNum)); \
printRegName(MI, O, MCOperand_getReg(Op)); \
}
DEFINE_printUImm(0);
DEFINE_printUImm(1);
DEFINE_printUImm(10);
DEFINE_printUImm(12);
DEFINE_printUImm(16);
DEFINE_printUImm(2);
DEFINE_printUImm(20);
DEFINE_printUImm(26);
DEFINE_printUImm(3);
DEFINE_printUImm(32);
DEFINE_printUImm(4);
DEFINE_printUImm(5);
DEFINE_printUImm(6);
DEFINE_printUImm(7);
DEFINE_printUImm(8);
DEFINE_printUImm_2(2, 1);
DEFINE_printUImm_2(5, 1);
DEFINE_printUImm_2(5, 32);
DEFINE_printUImm_2(5, 33);
DEFINE_printUImm_2(6, 1);
DEFINE_printUImm_2(6, 2);
static void printMemOperand(MCInst *MI, int opNum, SStream *O)
{
// Load/Store memory operands -- imm($reg)
@ -265,160 +284,348 @@ static void printMemOperand(MCInst *MI, int opNum, SStream *O)
// opNum can be invalid if instruction had reglist as operand.
// MemOperand is always last operand of instruction (base + offset).
switch (MCInst_getOpcode(MI)) {
default:
break;
case Mips_SWM32_MM:
case Mips_LWM32_MM:
case Mips_SWM16_MM:
case Mips_LWM16_MM:
opNum = MCInst_getNumOperands(MI) - 2;
break;
default:
break;
case Mips_SWM32_MM:
case Mips_LWM32_MM:
case Mips_SWM16_MM:
case Mips_SWM16_MMR6:
case Mips_LWM16_MM:
case Mips_LWM16_MMR6:
opNum = MCInst_getNumOperands(MI) - 2;
break;
}
set_mem_access(MI, true);
printOperand(MI, opNum + 1, O);
// Index register is encoded as immediate value
// in case of nanoMIPS indexed instructions
switch (MCInst_getOpcode(MI)) {
// No offset needed for paired LL/SC
case Mips_LLWP_NM:
case Mips_SCWP_NM:
break;
case Mips_LWX_NM:
case Mips_LWXS_NM:
case Mips_LWXS16_NM:
case Mips_LBX_NM:
case Mips_LBUX_NM:
case Mips_LHX_NM:
case Mips_LHUX_NM:
case Mips_LHXS_NM:
case Mips_LHUXS_NM:
case Mips_SWX_NM:
case Mips_SWXS_NM:
case Mips_SBX_NM:
case Mips_SHX_NM:
case Mips_SHXS_NM:
if (!MCOperand_isReg(MCInst_getOperand(MI, (opNum + 1)))) {
add_cs_detail(MI, Mips_OP_GROUP_MemOperand, (opNum + 1));
printRegName(MI, O, MCOperand_getImm(MCInst_getOperand(
MI, (opNum + 1))));
break;
}
// Fall through
default:
printOperand((MCInst *)MI, opNum + 1, O);
break;
}
SStream_concat0(O, "(");
printOperand(MI, opNum, O);
printOperand((MCInst *)MI, opNum, O);
SStream_concat0(O, ")");
set_mem_access(MI, false);
}
// TODO???
static void printMemOperandEA(MCInst *MI, int opNum, SStream *O)
{
// when using stack locations for not load/store instructions
// print the same way as all normal 3 operand instructions.
printOperand(MI, opNum, O);
printOperand((MCInst *)MI, opNum, O);
SStream_concat0(O, ", ");
printOperand(MI, opNum + 1, O);
return;
printOperand((MCInst *)MI, opNum + 1, O);
}
static void printFCCOperand(MCInst *MI, int opNum, SStream *O)
{
MCOperand *MO = MCInst_getOperand(MI, opNum);
SStream_concat0(O, MipsFCCToString((Mips_CondCode)MCOperand_getImm(MO)));
MCOperand *MO = MCInst_getOperand(MI, (opNum));
SStream_concat0(O,
MipsFCCToString((Mips_CondCode)MCOperand_getImm(MO)));
}
static void printRegisterPair(MCInst *MI, int opNum, SStream *O)
static bool printAlias(const char *Str, const MCInst *MI, uint64_t Address,
unsigned OpNo, SStream *OS, bool IsBranch)
{
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, opNum)));
SStream_concat(OS, "%s%s", "\t", Str);
SStream_concat0(OS, "\t");
if (IsBranch)
printBranchOperand((MCInst *)MI, Address, OpNo, OS);
else
printOperand((MCInst *)MI, OpNo, OS);
return true;
}
static char *printAlias1(const char *Str, MCInst *MI, unsigned OpNo, SStream *OS)
static bool printAlias2(const char *Str, const MCInst *MI, uint64_t Address,
unsigned OpNo0, unsigned OpNo1, SStream *OS, bool IsBranch)
{
SStream_concat(OS, "%s\t", Str);
printOperand(MI, OpNo, OS);
return cs_strdup(Str);
}
static char *printAlias2(const char *Str, MCInst *MI,
unsigned OpNo0, unsigned OpNo1, SStream *OS)
{
char *tmp;
tmp = printAlias1(Str, MI, OpNo0, OS);
printAlias(Str, MI, Address, OpNo0, OS, IsBranch);
SStream_concat0(OS, ", ");
printOperand(MI, OpNo1, OS);
return tmp;
if (IsBranch)
printBranchOperand((MCInst *)MI, Address, OpNo1, OS);
else
printOperand((MCInst *)MI, OpNo1, OS);
return true;
}
#define GET_REGINFO_ENUM
#include "MipsGenRegisterInfo.inc"
static bool printAlias3(const char *Str, const MCInst *MI, uint64_t Address,
unsigned OpNo0, unsigned OpNo1, unsigned OpNo2, SStream *OS)
{
printAlias(Str, MI, Address, OpNo0, OS, false);
SStream_concat0(OS, ", ");
printOperand((MCInst *)MI, OpNo1, OS);
SStream_concat0(OS, ", ");
printOperand((MCInst *)MI, OpNo2, OS);
return true;
}
static char *printAlias(MCInst *MI, SStream *OS)
static bool printAlias4(const MCInst *MI, uint64_t Address, SStream *OS)
{
switch (MCInst_getOpcode(MI)) {
case Mips_BEQ:
case Mips_BEQ_MM:
// beq $zero, $zero, $L2 => b $L2
// beq $r0, $zero, $L2 => beqz $r0, $L2
if (isReg(MI, 0, Mips_ZERO) && isReg(MI, 1, Mips_ZERO))
return printAlias1("b", MI, 2, OS);
if (isReg(MI, 1, Mips_ZERO))
return printAlias2("beqz", MI, 0, 2, OS);
return NULL;
case Mips_BEQ64:
// beq $r0, $zero, $L2 => beqz $r0, $L2
if (isReg(MI, 1, Mips_ZERO_64))
return printAlias2("beqz", MI, 0, 2, OS);
return NULL;
case Mips_BNE:
// bne $r0, $zero, $L2 => bnez $r0, $L2
if (isReg(MI, 1, Mips_ZERO))
return printAlias2("bnez", MI, 0, 2, OS);
return NULL;
case Mips_BNE64:
// bne $r0, $zero, $L2 => bnez $r0, $L2
if (isReg(MI, 1, Mips_ZERO_64))
return printAlias2("bnez", MI, 0, 2, OS);
return NULL;
case Mips_BGEZAL:
// bgezal $zero, $L1 => bal $L1
if (isReg(MI, 0, Mips_ZERO))
return printAlias1("bal", MI, 1, OS);
return NULL;
case Mips_BC1T:
// bc1t $fcc0, $L1 => bc1t $L1
if (isReg(MI, 0, Mips_FCC0))
return printAlias1("bc1t", MI, 1, OS);
return NULL;
case Mips_BC1F:
// bc1f $fcc0, $L1 => bc1f $L1
if (isReg(MI, 0, Mips_FCC0))
return printAlias1("bc1f", MI, 1, OS);
return NULL;
case Mips_JALR:
// jalr $ra, $r1 => jalr $r1
if (isReg(MI, 0, Mips_RA))
return printAlias1("jalr", MI, 1, OS);
return NULL;
case Mips_JALR64:
// jalr $ra, $r1 => jalr $r1
if (isReg(MI, 0, Mips_RA_64))
return printAlias1("jalr", MI, 1, OS);
return NULL;
case Mips_NOR:
case Mips_NOR_MM:
// nor $r0, $r1, $zero => not $r0, $r1
if (isReg(MI, 2, Mips_ZERO))
return printAlias2("not", MI, 0, 1, OS);
return NULL;
case Mips_NOR64:
// nor $r0, $r1, $zero => not $r0, $r1
if (isReg(MI, 2, Mips_ZERO_64))
return printAlias2("not", MI, 0, 1, OS);
return NULL;
case Mips_OR:
// or $r0, $r1, $zero => move $r0, $r1
if (isReg(MI, 2, Mips_ZERO))
return printAlias2("move", MI, 0, 1, OS);
return NULL;
default: return NULL;
case Mips_BEQ:
case Mips_BEQ_MM:
// beq $zero, $zero, $L2 => b $L2
// beq $r0, $zero, $L2 => beqz $r0, $L2
return (isReg(MI, 0, Mips_ZERO) &&
isReg(MI, 1, Mips_ZERO) &&
printAlias("b", MI, Address, 2, OS, true)) ||
(isReg(MI, 1, Mips_ZERO) &&
printAlias2("beqz", MI, Address, 0, 2, OS, true));
case Mips_BEQ64:
// beq $r0, $zero, $L2 => beqz $r0, $L2
return isReg(MI, 1, Mips_ZERO_64) &&
printAlias2("beqz", MI, Address, 0, 2, OS, true);
case Mips_BNE:
case Mips_BNE_MM:
// bne $r0, $zero, $L2 => bnez $r0, $L2
return isReg(MI, 1, Mips_ZERO) &&
printAlias2("bnez", MI, Address, 0, 2, OS, true);
case Mips_BNE64:
// bne $r0, $zero, $L2 => bnez $r0, $L2
return isReg(MI, 1, Mips_ZERO_64) &&
printAlias2("bnez", MI, Address, 0, 2, OS, true);
case Mips_BGEZAL:
// bgezal $zero, $L1 => bal $L1
return isReg(MI, 0, Mips_ZERO) &&
printAlias("bal", MI, Address, 1, OS, true);
case Mips_BC1T:
// bc1t $fcc0, $L1 => bc1t $L1
return isReg(MI, 0, Mips_FCC0) &&
printAlias("bc1t", MI, Address, 1, OS, true);
case Mips_BC1F:
// bc1f $fcc0, $L1 => bc1f $L1
return isReg(MI, 0, Mips_FCC0) &&
printAlias("bc1f", MI, Address, 1, OS, true);
case Mips_JALR:
// jalr $zero, $r1 => jr $r1
// jalr $ra, $r1 => jalr $r1
return (isReg(MI, 0, Mips_ZERO) &&
printAlias("jr", MI, Address, 1, OS, false)) ||
(isReg(MI, 0, Mips_RA) &&
printAlias("jalr", MI, Address, 1, OS, false));
case Mips_JALR64:
// jalr $zero, $r1 => jr $r1
// jalr $ra, $r1 => jalr $r1
return (isReg(MI, 0, Mips_ZERO_64) &&
printAlias("jr", MI, Address, 1, OS, false)) ||
(isReg(MI, 0, Mips_RA_64) &&
printAlias("jalr", MI, Address, 1, OS, false));
case Mips_NOR:
case Mips_NOR_MM:
case Mips_NOR_MMR6:
// nor $r0, $r1, $zero => not $r0, $r1
return isReg(MI, 2, Mips_ZERO) &&
printAlias2("not", MI, Address, 0, 1, OS, false);
case Mips_NOR64:
// nor $r0, $r1, $zero => not $r0, $r1
return isReg(MI, 2, Mips_ZERO_64) &&
printAlias2("not", MI, Address, 0, 1, OS, false);
case Mips_OR:
case Mips_ADDu:
// or $r0, $r1, $zero => move $r0, $r1
// addu $r0, $r1, $zero => move $r0, $r1
return isReg(MI, 2, Mips_ZERO) &&
printAlias2("move", MI, Address, 0, 1, OS, false);
case Mips_LI48_NM:
case Mips_LI16_NM:
// li[16/48] $r0, imm => li $r0, imm
return printAlias2("li", MI, Address, 0, 1, OS, false);
case Mips_ADDIU_NM:
case Mips_ADDIUNEG_NM:
if (isReg(MI, 1, Mips_ZERO_NM))
return printAlias2("li", MI, Address, 0, 2, OS, false);
else
return printAlias3("addiu", MI, Address, 0, 1, 2, OS);
case Mips_ADDIU48_NM:
case Mips_ADDIURS5_NM:
case Mips_ADDIUR1SP_NM:
case Mips_ADDIUR2_NM:
case Mips_ADDIUGPB_NM:
case Mips_ADDIUGPW_NM:
return printAlias3("addiu", MI, Address, 0, 1, 2, OS);
case Mips_ANDI16_NM:
case Mips_ANDI_NM:
// andi[16/32] $r0, $r1, imm => andi $r0, $r1, imm
return printAlias3("andi", MI, Address, 0, 1, 2, OS);
default:
return false;
}
}
static void printRegisterList(MCInst *MI, int opNum, SStream *O)
{
int i, e, reg;
// - 2 because register List is always first operand of instruction and it is
// always followed by memory operand (base + offset).
for (i = opNum, e = MCInst_getNumOperands(MI) - 2; i != e; ++i) {
add_cs_detail(MI, Mips_OP_GROUP_RegisterList, opNum);
for (int i = opNum, e = MCInst_getNumOperands(MI) - 2; i != e; ++i) {
if (i != opNum)
SStream_concat0(O, ", ");
reg = MCOperand_getReg(MCInst_getOperand(MI, i));
printRegName(O, reg);
if (MI->csh->detail_opt) {
MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_REG;
MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].reg = reg;
MI->flat_insn->detail->mips.op_count++;
}
printRegName(MI, O, MCOperand_getReg(MCInst_getOperand(MI, (i))));
}
}
#define PRINT_ALIAS_INSTR
#include "MipsGenAsmWriter.inc"
static void printNanoMipsRegisterList(MCInst *MI, int OpNum, SStream *O)
{
add_cs_detail(MI, Mips_OP_GROUP_NanoMipsRegisterList, OpNum);
for (unsigned I = OpNum; I < MCInst_getNumOperands(MI); I++) {
SStream_concat0(O, ", ");
printRegName(MI, O, MCOperand_getReg(MCInst_getOperand(MI, (I))));
}
}
#endif
static void printHi20(MCInst *MI, int OpNum, SStream *O)
{
MCOperand *MO = MCInst_getOperand(MI, (OpNum));
if (MCOperand_isImm(MO)) {
add_cs_detail(MI, Mips_OP_GROUP_Hi20, OpNum);
SStream_concat0(O, "%hi(");
printUInt64(O, MCOperand_getImm(MO));
SStream_concat0(O, ")");
} else
printOperand(MI, OpNum, O);
}
static void printHi20PCRel(MCInst *MI, uint64_t Address, int OpNum, SStream *O)
{
MCOperand *MO = MCInst_getOperand(MI, (OpNum));
if (MCOperand_isImm(MO)) {
add_cs_detail(MI, Mips_OP_GROUP_Hi20PCRel, OpNum);
SStream_concat0(O, "%pcrel_hi(");
printUInt64(O, MCOperand_getImm(MO) + Address);
SStream_concat0(O, ")");
} else
printOperand(MI, OpNum, O);
}
static void printPCRel(MCInst *MI, uint64_t Address, int OpNum, SStream *O)
{
MCOperand *MO = MCInst_getOperand(MI, (OpNum));
if (MCOperand_isImm(MO)) {
add_cs_detail(MI, Mips_OP_GROUP_PCRel, OpNum);
printUInt64(O, MCOperand_getImm(MO) + Address);
}
else
printOperand(MI, OpNum, O);
}
const char *Mips_LLVM_getRegisterName(unsigned RegNo, bool noRegName)
{
if (!RegNo || RegNo >= MIPS_REG_ENDING) {
return NULL;
}
if (noRegName) {
return getRegisterName(RegNo);
}
switch(RegNo) {
case MIPS_REG_AT:
case MIPS_REG_AT_64:
return "at";
case MIPS_REG_A0:
case MIPS_REG_A0_64:
return "a0";
case MIPS_REG_A1:
case MIPS_REG_A1_64:
return "a1";
case MIPS_REG_A2:
case MIPS_REG_A2_64:
return "a2";
case MIPS_REG_A3:
case MIPS_REG_A3_64:
return "a3";
case MIPS_REG_K0:
case MIPS_REG_K0_64:
return "k0";
case MIPS_REG_K1:
case MIPS_REG_K1_64:
return "k1";
case MIPS_REG_S0:
case MIPS_REG_S0_64:
return "s0";
case MIPS_REG_S1:
case MIPS_REG_S1_64:
return "s1";
case MIPS_REG_S2:
case MIPS_REG_S2_64:
return "s2";
case MIPS_REG_S3:
case MIPS_REG_S3_64:
return "s3";
case MIPS_REG_S4:
case MIPS_REG_S4_64:
return "s4";
case MIPS_REG_S5:
case MIPS_REG_S5_64:
return "s5";
case MIPS_REG_S6:
case MIPS_REG_S6_64:
return "s6";
case MIPS_REG_S7:
case MIPS_REG_S7_64:
return "s7";
case MIPS_REG_T0:
case MIPS_REG_T0_64:
return "t0";
case MIPS_REG_T1:
case MIPS_REG_T1_64:
return "t1";
case MIPS_REG_T2:
case MIPS_REG_T2_64:
return "t2";
case MIPS_REG_T3:
case MIPS_REG_T3_64:
return "t3";
case MIPS_REG_T4:
case MIPS_REG_T4_64:
return "t4";
case MIPS_REG_T5:
case MIPS_REG_T5_64:
return "t5";
case MIPS_REG_T6:
case MIPS_REG_T6_64:
return "t6";
case MIPS_REG_T7:
case MIPS_REG_T7_64:
return "t7";
case MIPS_REG_T8:
case MIPS_REG_T8_64:
return "t8";
case MIPS_REG_T9:
case MIPS_REG_T9_64:
return "t9";
case MIPS_REG_V0:
case MIPS_REG_V0_64:
return "v0";
case MIPS_REG_V1:
case MIPS_REG_V1_64:
return "v1";
default:
return getRegisterName(RegNo);
}
}

155
arch/Mips/MipsInstPrinter.h
View File

@ -1,9 +1,24 @@
#include "../../SStream.h"
#include "../../MCInst.h"
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2023 */
/* Automatically translated source file from LLVM. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Only small edits allowed. */
/* For multiple similar edits, please create a Patch for the translator. */
/* Capstone's C++ file translator: */
/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
//=== MipsInstPrinter.h - Convert Mips MCInst to assembly syntax -*- C++ -*-==//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
@ -11,15 +26,133 @@
//
//===----------------------------------------------------------------------===//
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
#ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSINSTPRINTER_H
#define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSINSTPRINTER_H
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <capstone/platform.h>
#ifndef CS_MIPSINSTPRINTER_H
#define CS_MIPSINSTPRINTER_H
#include "../../MCInstPrinter.h"
#include "../../cs_priv.h"
#define CONCAT(a, b) CONCAT_(a, b)
#define CONCAT_(a, b) a##_##b
#include "../../MCInst.h"
#include "../../SStream.h"
// These enumeration declarations were originally in MipsInstrInfo.h but
// had to be moved here to avoid circular dependencies between
// LLVMMipsCodeGen and LLVMMipsAsmPrinter.
// CS namespace begin: Mips
void Mips_printInst(MCInst *MI, SStream *O, void *info);
// Mips Branch Codes
typedef enum MipsFPBranchCode {
Mips_BRANCH_F,
Mips_BRANCH_T,
Mips_BRANCH_FL,
Mips_BRANCH_TL,
Mips_BRANCH_INVALID
} Mips_FPBranchCode;
// Mips Condition Codes
typedef enum MipsCondCode {
// To be used with float branch True
Mips_FCOND_F,
Mips_FCOND_UN,
Mips_FCOND_OEQ,
Mips_FCOND_UEQ,
Mips_FCOND_OLT,
Mips_FCOND_ULT,
Mips_FCOND_OLE,
Mips_FCOND_ULE,
Mips_FCOND_SF,
Mips_FCOND_NGLE,
Mips_FCOND_SEQ,
Mips_FCOND_NGL,
Mips_FCOND_LT,
Mips_FCOND_NGE,
Mips_FCOND_LE,
Mips_FCOND_NGT,
// To be used with float branch False
// This conditions have the same mnemonic as the
// above ones, but are used with a branch False;
Mips_FCOND_T,
Mips_FCOND_OR,
Mips_FCOND_UNE,
Mips_FCOND_ONE,
Mips_FCOND_UGE,
Mips_FCOND_OGE,
Mips_FCOND_UGT,
Mips_FCOND_OGT,
Mips_FCOND_ST,
Mips_FCOND_GLE,
Mips_FCOND_SNE,
Mips_FCOND_GL,
Mips_FCOND_NLT,
Mips_FCOND_GE,
Mips_FCOND_NLE,
Mips_FCOND_GT
} Mips_CondCode;
static const char *MipsFCCToString(Mips_CondCode CC);
// CS namespace end: Mips
// end namespace Mips
// Autogenerated by tblgen.
static const char *getRegisterName(unsigned RegNo);
static void printInstruction(MCInst *MI, uint64_t Address, SStream *O);
static bool printAliasInstr(MCInst *MI, uint64_t Address, SStream *OS);
static void printCustomAliasOperand(MCInst *MI, uint64_t Address, unsigned OpIdx,
unsigned PrintMethodIdx, SStream *O);
static void printOperand(MCInst *MI, unsigned OpNo, SStream *O);
static void printJumpOperand(MCInst *MI, unsigned OpNo, SStream *O);
static void printBranchOperand(MCInst *MI, uint64_t Address, unsigned OpNo,
SStream *O);
#define DECLARE_printUImm_2(Bits, Offset) \
static void CONCAT(printUImm, CONCAT(Bits, Offset))( \
MCInst *MI, int opNum, SStream *O)
#define DECLARE_printUImm(Bits) \
static void CONCAT(printUImm, CONCAT(Bits, 0))( \
MCInst *MI, int opNum, SStream *O)
DECLARE_printUImm(0);
DECLARE_printUImm(1);
DECLARE_printUImm(10);
DECLARE_printUImm(12);
DECLARE_printUImm(16);
DECLARE_printUImm(2);
DECLARE_printUImm(20);
DECLARE_printUImm(26);
DECLARE_printUImm(3);
DECLARE_printUImm(32);
DECLARE_printUImm(4);
DECLARE_printUImm(5);
DECLARE_printUImm(6);
DECLARE_printUImm(7);
DECLARE_printUImm(8);
DECLARE_printUImm_2(2, 1);
DECLARE_printUImm_2(5, 1);
DECLARE_printUImm_2(5, 32);
DECLARE_printUImm_2(5, 33);
DECLARE_printUImm_2(6, 1);
DECLARE_printUImm_2(6, 2);
static void printMemOperand(MCInst *MI, int opNum, SStream *O);
static void printMemOperandEA(MCInst *MI, int opNum, SStream *O);
static void printFCCOperand(MCInst *MI, int opNum, SStream *O);
static bool printAlias(const char *Str, const MCInst *MI, uint64_t Address,
unsigned OpNo, SStream *OS, bool IsBranch);
static bool printAlias2(const char *Str, const MCInst *MI, uint64_t Address,
unsigned OpNo0, unsigned OpNo1, SStream *OS,
bool IsBranch);
static bool printAlias3(const char *Str, const MCInst *MI, uint64_t Address,
unsigned OpNo0, unsigned OpNo1, unsigned OpNo2, SStream *OS);
static bool printAlias4(const MCInst *MI, uint64_t Address, SStream *OS);
static void printRegisterList(MCInst *MI, int opNum, SStream *O);
static void printNanoMipsRegisterList(MCInst *MI, int opNum, SStream *O);
static void printHi20(MCInst *MI, int OpNum, SStream *O);
static void printHi20PCRel(MCInst *MI, uint64_t Address, int OpNum, SStream *O);
static void printPCRel(MCInst *MI, uint64_t Address, int OpNum, SStream *O);
#endif

21
arch/Mips/MipsLinkage.h Normal file
View File

@ -0,0 +1,21 @@
/* Capstone Disassembly Engine */
/* By Giovanni Dante Grazioli, deroad <wargio@libero.it>, 2024 */
#ifndef CS_MIPS_LINKAGE_H
#define CS_MIPS_LINKAGE_H
// Function definitions to call static LLVM functions.
#include "../../MCDisassembler.h"
#include "../../MCInst.h"
#include "../../MCRegisterInfo.h"
#include "../../SStream.h"
#include "capstone/capstone.h"
const char *Mips_LLVM_getRegisterName(unsigned RegNo, bool noRegName);
void Mips_LLVM_printInst(MCInst *MI, uint64_t Address, SStream *O);
DecodeStatus Mips_LLVM_getInstruction(MCInst *Instr, uint64_t *Size,
const uint8_t *Bytes, size_t BytesLen,
uint64_t Address, SStream *CStream);
#endif // CS_MIPS_LINKAGE_H

1410
arch/Mips/MipsMapping.c
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File diff suppressed because it is too large Load Diff

57
arch/Mips/MipsMapping.h
View File

@ -1,25 +1,62 @@
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
/* By Giovanni Dante Grazioli, deroad <wargio@libero.it>, 2024 */
#ifndef CS_MIPS_MAP_H
#define CS_MIPS_MAP_H
#ifndef CS_MIPS_MAPPING_H
#define CS_MIPS_MAPPING_H
#include "capstone/capstone.h"
#include "../../include/capstone/capstone.h"
#include "../../utils.h"
#include "../../Mapping.h"
typedef enum {
#include "MipsGenCSOpGroup.inc"
} mips_op_group;
void Mips_init_mri(MCRegisterInfo *MRI);
// return name of register in friendly string
const char *Mips_reg_name(csh handle, unsigned int reg);
// given internal insn id, return public instruction info
void Mips_printer(MCInst *MI, SStream *O,
void * /* MCRegisterInfo* */ info);
// given internal insn id, return public instruction ID
void Mips_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
const char *Mips_insn_name(csh handle, unsigned int id);
const char *Mips_group_name(csh handle, unsigned int id);
// map instruction name to instruction ID
mips_reg Mips_map_insn(const char *name);
bool Mips_getInstruction(csh handle, const uint8_t *code, size_t code_len,
MCInst *instr, uint16_t *size, uint64_t address,
void *info);
// map internal raw register to 'public' register
mips_reg Mips_map_register(unsigned int r);
void Mips_reg_access(const cs_insn *insn, cs_regs regs_read,
uint8_t *regs_read_count, cs_regs regs_write,
uint8_t *regs_write_count);
#endif
// cs_detail related functions
void Mips_init_cs_detail(MCInst *MI);
void Mips_set_mem_access(MCInst *MI, bool status);
void Mips_add_cs_detail(MCInst *MI, mips_op_group op_group, va_list args);
static inline void add_cs_detail(MCInst *MI, mips_op_group op_group, ...)
{
if (!detail_is_set(MI))
return;
va_list args;
va_start(args, op_group);
Mips_add_cs_detail(MI, op_group, args);
va_end(args);
}
static inline void set_mem_access(MCInst *MI, bool status)
{
if (!detail_is_set(MI))
return;
Mips_set_mem_access(MI, status);
}
#endif // CS_MIPS_MAPPING_H

46
arch/Mips/MipsModule.c
View File

@ -1,52 +1,52 @@
/* Capstone Disassembly Engine */
/* By Dang Hoang Vu <danghvu@gmail.com> 2013 */
/* By Giovanni Dante Grazioli, deroad <wargio@libero.it>, 2024 */
#ifdef CAPSTONE_HAS_MIPS
#include "../../utils.h"
#include "../../MCRegisterInfo.h"
#include "MipsDisassembler.h"
#include "MipsInstPrinter.h"
#include "MipsMapping.h"
#include <capstone/capstone.h>
#include "MipsModule.h"
// Returns mode value with implied bits set
static cs_mode updated_mode(cs_mode mode)
{
if (mode & CS_MODE_MIPS32R6) {
mode |= CS_MODE_32;
}
return mode;
}
#include "../../MCRegisterInfo.h"
#include "../../cs_priv.h"
#include "MipsMapping.h"
cs_err Mips_global_init(cs_struct *ud)
{
MCRegisterInfo *mri;
mri = cs_mem_malloc(sizeof(*mri));
Mips_init(mri);
ud->printer = Mips_printInst;
Mips_init_mri(mri);
ud->printer = Mips_printer;
ud->printer_info = mri;
ud->getinsn_info = mri;
ud->reg_name = Mips_reg_name;
ud->insn_id = Mips_get_insn_id;
ud->insn_name = Mips_insn_name;
ud->group_name = Mips_group_name;
ud->disasm = Mips_getInstruction;
ud->post_printer = NULL;
#ifndef CAPSTONE_DIET
ud->reg_access = Mips_reg_access;
#endif
return CS_ERR_OK;
}
cs_err Mips_option(cs_struct *handle, cs_opt_type type, size_t value)
{
if (type == CS_OPT_MODE) {
handle->mode = updated_mode(value);
return CS_ERR_OK;
switch (type) {
case CS_OPT_MODE:
handle->mode = (cs_mode)value;
break;
case CS_OPT_SYNTAX:
handle->syntax |= (int)value;
break;
default:
break;
}
return CS_ERR_OPTION;
return CS_ERR_OK;
}
#endif

4
arch/Mips/MipsModule.h
View File

@ -1,5 +1,5 @@
/* Capstone Disassembly Engine */
/* By Travis Finkenauer <tmfinken@gmail.com>, 2018 */
/* By Giovanni Dante Grazioli, deroad <wargio@libero.it>, 2024 */
#ifndef CS_MIPS_MODULE_H
#define CS_MIPS_MODULE_H
@ -9,4 +9,4 @@
cs_err Mips_global_init(cs_struct *ud);
cs_err Mips_option(cs_struct *handle, cs_opt_type type, size_t value);
#endif
#endif // CS_MIPS_MODULE_H

2
bindings/java/capstone/Capstone.java
View File

@ -84,7 +84,7 @@ public class Capstone {
public short[] regs_write = new short[20];
public byte regs_write_count;
// list of semantic groups this instruction belongs to.
public byte[] groups = new byte[8];
public byte[] groups = new byte[16];
public byte groups_count;
public UnionArch arch;

3002
bindings/java/capstone/Mips_const.java
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File diff suppressed because it is too large Load Diff

3002
bindings/ocaml/mips_const.ml
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File diff suppressed because it is too large Load Diff

65
bindings/python/capstone/__init__.py
View File

@ -51,24 +51,44 @@ __all__ = [
'CS_MODE_ARM',
'CS_MODE_THUMB',
'CS_MODE_MCLASS',
'CS_MODE_MICRO',
'CS_MODE_MIPS3',
'CS_MODE_MIPS32R6',
'CS_MODE_MIPS2',
'CS_MODE_V8',
'CS_MODE_V9',
'CS_MODE_QPX',
'CS_MODE_SPE',
'CS_MODE_BOOKE',
'CS_MODE_PS',
'CS_MODE_MIPS16',
'CS_MODE_MIPS32',
'CS_MODE_MIPS64',
'CS_MODE_MICRO',
'CS_MODE_MIPS1',
'CS_MODE_MIPS2',
'CS_MODE_MIPS32R2',
'CS_MODE_MIPS32R3',
'CS_MODE_MIPS32R5',
'CS_MODE_MIPS32R6',
'CS_MODE_MIPS3',
'CS_MODE_MIPS4',
'CS_MODE_MIPS5',
'CS_MODE_MIPS64R2',
'CS_MODE_MIPS64R3',
'CS_MODE_MIPS64R5',
'CS_MODE_MIPS64R6',
'CS_MODE_OCTEON',
'CS_MODE_OCTEONP',
'CS_MODE_NANOMIPS',
'CS_MODE_NMS1',
'CS_MODE_I7200',
'CS_MODE_MIPS_NOFLOAT',
'CS_MODE_MIPS_PTR64',
'CS_MODE_MICRO32R3',
'CS_MODE_MICRO32R6',
'CS_MODE_M68K_000',
'CS_MODE_M68K_010',
'CS_MODE_M68K_020',
'CS_MODE_M68K_030',
'CS_MODE_M68K_040',
'CS_MODE_M68K_060',
'CS_MODE_MIPS32',
'CS_MODE_MIPS64',
'CS_MODE_M680X_6301',
'CS_MODE_M680X_6309',
'CS_MODE_M680X_6800',
@ -119,8 +139,10 @@ __all__ = [
'CS_OPT_SYNTAX_MASM',
'CS_OPT_SYNTAX_MOTOROLA',
'CS_OPT_SYNTAX_CS_REG_ALIAS',
'CS_OPT_SYNTAX_NO_DOLLAR',
'CS_OPT_DETAIL',
'CS_OPT_DETAIL_REAL',
'CS_OPT_MODE',
'CS_OPT_ON',
'CS_OPT_OFF',
@ -257,8 +279,32 @@ CS_MODE_M68K_030 = (1 << 4) # M68K 68030 mode
CS_MODE_M68K_040 = (1 << 5) # M68K 68040 mode
CS_MODE_M68K_060 = (1 << 6) # M68K 68060 mode
CS_MODE_BIG_ENDIAN = (1 << 31) # big-endian mode
CS_MODE_MIPS32 = CS_MODE_32 # Mips32 ISA
CS_MODE_MIPS64 = CS_MODE_64 # Mips64 ISA
CS_MODE_MIPS16 = CS_MODE_16 # Generic mips16
CS_MODE_MIPS32 = CS_MODE_32 # Generic mips32
CS_MODE_MIPS64 = CS_MODE_64 # Generic mips64
CS_MODE_MICRO = 1 << 4 # microMips
CS_MODE_MIPS1 = 1 << 5 # Mips I ISA Support
CS_MODE_MIPS2 = 1 << 6 # Mips II ISA Support
CS_MODE_MIPS32R2 = 1 << 7 # Mips32r2 ISA Support
CS_MODE_MIPS32R3 = 1 << 8 # Mips32r3 ISA Support
CS_MODE_MIPS32R5 = 1 << 9 # Mips32r5 ISA Support
CS_MODE_MIPS32R6 = 1 << 10 # Mips32r6 ISA Support
CS_MODE_MIPS3 = 1 << 11 # MIPS III ISA Support
CS_MODE_MIPS4 = 1 << 12 # MIPS IV ISA Support
CS_MODE_MIPS5 = 1 << 13 # MIPS V ISA Support
CS_MODE_MIPS64R2 = 1 << 14 # Mips64r2 ISA Support
CS_MODE_MIPS64R3 = 1 << 15 # Mips64r3 ISA Support
CS_MODE_MIPS64R5 = 1 << 16 # Mips64r5 ISA Support
CS_MODE_MIPS64R6 = 1 << 17 # Mips64r6 ISA Support
CS_MODE_OCTEON = 1 << 18 # Octeon cnMIPS Support
CS_MODE_OCTEONP = 1 << 19 # Octeon+ cnMIPS Support
CS_MODE_NANOMIPS = 1 << 20 # Generic nanomips
CS_MODE_NMS1 = ((1 << 21) | CS_MODE_NANOMIPS) # nanoMips NMS1
CS_MODE_I7200 = ((1 << 22) | CS_MODE_NANOMIPS) # nanoMips I7200
CS_MODE_MIPS_NOFLOAT = 1 << 23 # Disable floating points ops
CS_MODE_MIPS_PTR64 = 1 << 24 # Mips pointers are 64-bit
CS_MODE_MICRO32R3 = (CS_MODE_MICRO | CS_MODE_MIPS32R3) # microMips32r3
CS_MODE_MICRO32R6 = (CS_MODE_MICRO | CS_MODE_MIPS32R6) # microMips32r6
CS_MODE_M680X_6301 = (1 << 1) # M680X HD6301/3 mode
CS_MODE_M680X_6309 = (1 << 2) # M680X HD6309 mode
CS_MODE_M680X_6800 = (1 << 3) # M680X M6800/2 mode
@ -364,6 +410,7 @@ CS_OPT_SYNTAX_MASM = (1 << 5) # MASM syntax (CS_OPT_SYNTAX, CS_ARCH_X86)
CS_OPT_SYNTAX_MOTOROLA = (1 << 6) # MOS65XX use $ as hex prefix
CS_OPT_SYNTAX_CS_REG_ALIAS = (1 << 7) # Prints common register alias which are not defined in LLVM (ARM: r9 = sb etc.)
CS_OPT_SYNTAX_PERCENT = (1 << 8) # Prints the % in front of PPC registers.
CS_OPT_SYNTAX_NO_DOLLAR = (1 << 9) # Does not print the $ in front of Mips registers.
CS_OPT_DETAIL_REAL = (1 << 1) # If enabled, always sets the real instruction detail.Even if the instruction is an alias.
# Capstone error type
@ -501,7 +548,7 @@ class _cs_detail(ctypes.Structure):
('regs_read_count', ctypes.c_ubyte),
('regs_write', ctypes.c_uint16 * 47),
('regs_write_count', ctypes.c_ubyte),
('groups', ctypes.c_ubyte * 8),
('groups', ctypes.c_ubyte * 16),
('groups_count', ctypes.c_ubyte),
('writeback', ctypes.c_bool),
('arch', _cs_arch),

4
bindings/python/capstone/mips.py
View File

@ -15,6 +15,7 @@ class MipsOpValue(ctypes.Union):
_fields_ = (
('reg', ctypes.c_uint),
('imm', ctypes.c_int64),
('uimm', ctypes.c_uint64),
('mem', MipsOpMem),
)
@ -22,6 +23,9 @@ class MipsOp(ctypes.Structure):
_fields_ = (
('type', ctypes.c_uint),
('value', MipsOpValue),
('is_reglist', ctypes.c_bool),
('is_unsigned', ctypes.c_bool),
('access', ctypes.c_uint8),
)
@property

3002
bindings/python/capstone/mips_const.py
View File

File diff suppressed because it is too large Load Diff

4
bindings/python/cstest_py/src/cstest_py/cs_modes.py
View File

@ -38,4 +38,8 @@ configs = {
"type": cs.CS_OPT_SYNTAX,
"val": cs.CS_OPT_SYNTAX_PERCENT,
},
"CS_OPT_SYNTAX_NO_DOLLAR": {
"type": cs.CS_OPT_SYNTAX,
"val": cs.CS_OPT_SYNTAX_NO_DOLLAR,
},
}

29
cs.c
View File

@ -100,8 +100,33 @@ typedef struct cs_arch_config {
{ \
Mips_global_init, \
Mips_option, \
~(CS_MODE_LITTLE_ENDIAN | CS_MODE_32 | CS_MODE_64 | CS_MODE_MICRO \
| CS_MODE_MIPS32R6 | CS_MODE_BIG_ENDIAN | CS_MODE_MIPS2 | CS_MODE_MIPS3), \
~(CS_MODE_LITTLE_ENDIAN | \
CS_MODE_BIG_ENDIAN | \
CS_MODE_MIPS16 | \
CS_MODE_MIPS32 | \
CS_MODE_MIPS64 | \
CS_MODE_MICRO | \
CS_MODE_MIPS1 | \
CS_MODE_MIPS2 | \
CS_MODE_MIPS32R2 | \
CS_MODE_MIPS32R3 | \
CS_MODE_MIPS32R5 | \
CS_MODE_MIPS32R6 | \
CS_MODE_MIPS3 | \
CS_MODE_MIPS4 | \
CS_MODE_MIPS5 | \
CS_MODE_MIPS64R2 | \
CS_MODE_MIPS64R3 | \
CS_MODE_MIPS64R5 | \
CS_MODE_MIPS64R6 | \
CS_MODE_OCTEON | \
CS_MODE_OCTEONP | \
CS_MODE_NANOMIPS | \
CS_MODE_NMS1 | \
CS_MODE_I7200 | \
CS_MODE_MIPS_NOFLOAT | \
CS_MODE_MIPS_PTR64 \
), \
}
#define CS_ARCH_CONFIG_X86 \
{ \

589
cstool/cstool.c
View File

@ -9,121 +9,210 @@
#include <capstone/capstone.h>
#include "cstool.h"
#ifdef CAPSTONE_AARCH64_COMPAT_HEADER
#define CS_ARCH_AARCH64 CS_ARCH_ARM
#endif
void print_string_hex(const char *comment, unsigned char *str, size_t len);
static struct {
const char *name;
const char *desc;
cs_arch archs[CS_ARCH_MAX];
cs_opt_value opt;
cs_mode mode;
} all_opts[] = {
// cs_opt_value only
{ "+att", "ATT syntax", {
CS_ARCH_X86, CS_ARCH_MAX }, CS_OPT_SYNTAX_ATT, 0 },
{ "+intel", "Intel syntax", {
CS_ARCH_X86, CS_ARCH_MAX }, CS_OPT_SYNTAX_INTEL, 0 },
{ "+masm", "Intel MASM syntax", {
CS_ARCH_X86, CS_ARCH_MAX }, CS_OPT_SYNTAX_MASM, 0 },
{ "+noregname", "Number only registers", {
CS_ARCH_AARCH64, CS_ARCH_ARM, CS_ARCH_LOONGARCH,
CS_ARCH_MIPS, CS_ARCH_PPC, CS_ARCH_MAX },
CS_OPT_SYNTAX_NOREGNAME, 0 },
{ "+moto", "Use $ as hex prefix", {
CS_ARCH_MOS65XX, CS_ARCH_MAX }, CS_OPT_SYNTAX_MOTOROLA, 0 },
{ "+regalias", "Use register aliases, like r9 > sb", {
CS_ARCH_ARM, CS_ARCH_AARCH64, CS_ARCH_MAX },
CS_OPT_SYNTAX_CS_REG_ALIAS, 0 },
{ "+percentage", "Adds % in front of the registers", {
CS_ARCH_PPC, CS_ARCH_MAX }, CS_OPT_SYNTAX_PERCENT, 0 },
{ "+nodollar", "Removes $ in front of the registers", {
CS_ARCH_MIPS, CS_ARCH_MAX }, CS_OPT_SYNTAX_NO_DOLLAR, 0 },
// cs_mode only
{ "+nofloat", "Disables floating point support", {
CS_ARCH_MIPS, CS_ARCH_MAX }, 0, CS_MODE_MIPS_NOFLOAT },
{ "+ptr64", "Enables 64-bit pointers support", {
CS_ARCH_MIPS, CS_ARCH_MAX }, 0, CS_MODE_MIPS_PTR64 },
{ NULL }
};
static struct {
const char *name;
const char *desc;
cs_arch arch;
cs_mode mode;
} all_archs[] = {
{ "arm", CS_ARCH_ARM, CS_MODE_ARM },
{ "armb", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_BIG_ENDIAN },
{ "armbe", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_BIG_ENDIAN },
{ "arml", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_LITTLE_ENDIAN },
{ "armle", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_LITTLE_ENDIAN },
{ "armv8", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_V8 },
{ "thumbv8", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_V8 },
{ "armv8be", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_V8 | CS_MODE_BIG_ENDIAN },
{ "thumbv8be", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_V8 | CS_MODE_BIG_ENDIAN },
{ "cortexm", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_MCLASS },
{ "cortexv8m", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_MCLASS | CS_MODE_V8 },
{ "thumb", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB },
{ "thumbbe", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_BIG_ENDIAN },
{ "thumble", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_LITTLE_ENDIAN },
{ "aarch64", CS_ARCH_AARCH64, CS_MODE_LITTLE_ENDIAN },
{ "aarch64be", CS_ARCH_AARCH64, CS_MODE_BIG_ENDIAN },
{ "mips", CS_ARCH_MIPS, CS_MODE_MIPS32 | CS_MODE_LITTLE_ENDIAN },
{ "mipsmicro", CS_ARCH_MIPS, CS_MODE_MIPS32 | CS_MODE_MICRO },
{ "mipsbemicro", CS_ARCH_MIPS, CS_MODE_MIPS32 | CS_MODE_MICRO | CS_MODE_BIG_ENDIAN },
{ "mipsbe32r6", CS_ARCH_MIPS, CS_MODE_MIPS32R6 | CS_MODE_BIG_ENDIAN},
{ "mipsbe32r6micro", CS_ARCH_MIPS, CS_MODE_MIPS32R6 | CS_MODE_BIG_ENDIAN | CS_MODE_MICRO },
{ "mips32r6", CS_ARCH_MIPS, CS_MODE_MIPS32R6 },
{ "mips32r6micro", CS_ARCH_MIPS, CS_MODE_MIPS32R6 | CS_MODE_MICRO },
{ "mipsbe", CS_ARCH_MIPS, CS_MODE_MIPS32 | CS_MODE_BIG_ENDIAN },
{ "mips64", CS_ARCH_MIPS, CS_MODE_MIPS64 | CS_MODE_LITTLE_ENDIAN },
{ "mips64be", CS_ARCH_MIPS, CS_MODE_MIPS64 | CS_MODE_BIG_ENDIAN },
{ "x16", CS_ARCH_X86, CS_MODE_16 }, // CS_MODE_16
{ "x16att", CS_ARCH_X86, CS_MODE_16 }, // CS_MODE_16 , CS_OPT_SYNTAX_ATT
{ "x32", CS_ARCH_X86, CS_MODE_32 }, // CS_MODE_32
{ "x32att", CS_ARCH_X86, CS_MODE_32 }, // CS_MODE_32, CS_OPT_SYNTAX_ATT
{ "x64", CS_ARCH_X86, CS_MODE_64 }, // CS_MODE_64
{ "x64att", CS_ARCH_X86, CS_MODE_64 }, // CS_MODE_64, CS_OPT_SYNTAX_ATT
{ "ppc32", CS_ARCH_PPC, CS_MODE_32 | CS_MODE_LITTLE_ENDIAN },
{ "ppc32be", CS_ARCH_PPC, CS_MODE_32 | CS_MODE_BIG_ENDIAN },
{ "ppc32qpx", CS_ARCH_PPC, CS_MODE_32 | CS_MODE_QPX | CS_MODE_LITTLE_ENDIAN },
{ "ppc32beqpx", CS_ARCH_PPC, CS_MODE_32 | CS_MODE_QPX | CS_MODE_BIG_ENDIAN },
{ "ppc32ps", CS_ARCH_PPC, CS_MODE_32 | CS_MODE_PS | CS_MODE_LITTLE_ENDIAN },
{ "ppc32beps", CS_ARCH_PPC, CS_MODE_32 | CS_MODE_PS | CS_MODE_BIG_ENDIAN },
{ "ppc64", CS_ARCH_PPC, CS_MODE_64 | CS_MODE_LITTLE_ENDIAN },
{ "ppc64be", CS_ARCH_PPC, CS_MODE_64 | CS_MODE_BIG_ENDIAN },
{ "ppc64qpx", CS_ARCH_PPC, CS_MODE_64 | CS_MODE_QPX | CS_MODE_LITTLE_ENDIAN },
{ "ppc64beqpx", CS_ARCH_PPC, CS_MODE_64 | CS_MODE_QPX | CS_MODE_BIG_ENDIAN },
{ "sparc", CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN },
{ "sparcv9", CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN | CS_MODE_V9 },
{ "systemz", CS_ARCH_SYSZ, CS_MODE_BIG_ENDIAN },
{ "sysz", CS_ARCH_SYSZ, CS_MODE_BIG_ENDIAN },
{ "s390x", CS_ARCH_SYSZ, CS_MODE_BIG_ENDIAN },
{ "xcore", CS_ARCH_XCORE, CS_MODE_BIG_ENDIAN },
{ "m68k", CS_ARCH_M68K, CS_MODE_BIG_ENDIAN },
{ "m68k40", CS_ARCH_M68K, CS_MODE_M68K_040 },
{ "tms320c64x", CS_ARCH_TMS320C64X, CS_MODE_BIG_ENDIAN },
{ "m6800", CS_ARCH_M680X, CS_MODE_M680X_6800 },
{ "m6801", CS_ARCH_M680X, CS_MODE_M680X_6801 },
{ "m6805", CS_ARCH_M680X, CS_MODE_M680X_6805 },
{ "m6808", CS_ARCH_M680X, CS_MODE_M680X_6808 },
{ "m6809", CS_ARCH_M680X, CS_MODE_M680X_6809 },
{ "m6811", CS_ARCH_M680X, CS_MODE_M680X_6811 },
{ "cpu12", CS_ARCH_M680X, CS_MODE_M680X_CPU12 },
{ "hd6301", CS_ARCH_M680X, CS_MODE_M680X_6301 },
{ "hd6309", CS_ARCH_M680X, CS_MODE_M680X_6309 },
{ "hcs08", CS_ARCH_M680X, CS_MODE_M680X_HCS08 },
{ "evm", CS_ARCH_EVM, 0 },
{ "wasm", CS_ARCH_WASM, 0 },
{ "bpf", CS_ARCH_BPF, CS_MODE_LITTLE_ENDIAN | CS_MODE_BPF_CLASSIC },
{ "bpfbe", CS_ARCH_BPF, CS_MODE_BIG_ENDIAN | CS_MODE_BPF_CLASSIC },
{ "ebpf", CS_ARCH_BPF, CS_MODE_LITTLE_ENDIAN | CS_MODE_BPF_EXTENDED },
{ "ebpfbe", CS_ARCH_BPF, CS_MODE_BIG_ENDIAN | CS_MODE_BPF_EXTENDED },
{ "riscv32", CS_ARCH_RISCV, CS_MODE_RISCV32 | CS_MODE_RISCVC },
{ "riscv64", CS_ARCH_RISCV, CS_MODE_RISCV64 | CS_MODE_RISCVC },
{ "6502", CS_ARCH_MOS65XX, CS_MODE_MOS65XX_6502 },
{ "65c02", CS_ARCH_MOS65XX, CS_MODE_MOS65XX_65C02 },
{ "w65c02", CS_ARCH_MOS65XX, CS_MODE_MOS65XX_W65C02 },
{ "65816", CS_ARCH_MOS65XX, CS_MODE_MOS65XX_65816_LONG_MX },
{ "sh", CS_ARCH_SH, CS_MODE_BIG_ENDIAN },
{ "sh2", CS_ARCH_SH, CS_MODE_SH2 | CS_MODE_BIG_ENDIAN},
{ "sh2e", CS_ARCH_SH, CS_MODE_SH2 | CS_MODE_SHFPU | CS_MODE_BIG_ENDIAN},
{ "sh-dsp", CS_ARCH_SH, CS_MODE_SH2 | CS_MODE_SHDSP | CS_MODE_BIG_ENDIAN},
{ "sh2a", CS_ARCH_SH, CS_MODE_SH2A | CS_MODE_BIG_ENDIAN},
{ "sh2a-fpu", CS_ARCH_SH, CS_MODE_SH2A | CS_MODE_SHFPU | CS_MODE_BIG_ENDIAN},
{ "sh3", CS_ARCH_SH, CS_MODE_LITTLE_ENDIAN | CS_MODE_SH3 },
{ "sh3be", CS_ARCH_SH, CS_MODE_BIG_ENDIAN | CS_MODE_SH3 },
{ "sh3e", CS_ARCH_SH, CS_MODE_LITTLE_ENDIAN | CS_MODE_SH3 | CS_MODE_SHFPU},
{ "sh3ebe", CS_ARCH_SH, CS_MODE_BIG_ENDIAN | CS_MODE_SH3 | CS_MODE_SHFPU},
{ "sh3-dsp", CS_ARCH_SH, CS_MODE_LITTLE_ENDIAN | CS_MODE_SH3 | CS_MODE_SHDSP },
{ "sh3-dspbe", CS_ARCH_SH, CS_MODE_BIG_ENDIAN | CS_MODE_SH3 | CS_MODE_SHDSP },
{ "sh4", CS_ARCH_SH, CS_MODE_LITTLE_ENDIAN | CS_MODE_SH4 | CS_MODE_SHFPU },
{ "sh4be", CS_ARCH_SH, CS_MODE_BIG_ENDIAN | CS_MODE_SH4 | CS_MODE_SHFPU },
{ "sh4a", CS_ARCH_SH, CS_MODE_LITTLE_ENDIAN | CS_MODE_SH4A | CS_MODE_SHFPU },
{ "sh4abe", CS_ARCH_SH, CS_MODE_BIG_ENDIAN | CS_MODE_SH4A | CS_MODE_SHFPU },
{ "sh4al-dsp", CS_ARCH_SH, CS_MODE_LITTLE_ENDIAN | CS_MODE_SH4A | CS_MODE_SHDSP | CS_MODE_SHFPU },
{ "sh4al-dspbe", CS_ARCH_SH, CS_MODE_BIG_ENDIAN | CS_MODE_SH4A | CS_MODE_SHDSP | CS_MODE_SHFPU },
{ "tc110", CS_ARCH_TRICORE, CS_MODE_TRICORE_110 },
{ "tc120", CS_ARCH_TRICORE, CS_MODE_TRICORE_120 },
{ "tc130", CS_ARCH_TRICORE, CS_MODE_TRICORE_130 },
{ "tc131", CS_ARCH_TRICORE, CS_MODE_TRICORE_131 },
{ "tc160", CS_ARCH_TRICORE, CS_MODE_TRICORE_160 },
{ "tc161", CS_ARCH_TRICORE, CS_MODE_TRICORE_161 },
{ "tc162", CS_ARCH_TRICORE, CS_MODE_TRICORE_162 },
{ "alpha", CS_ARCH_ALPHA, CS_MODE_LITTLE_ENDIAN },
{ "alphabe", CS_ARCH_ALPHA, CS_MODE_BIG_ENDIAN },
{ "hppa11", CS_ARCH_HPPA, CS_MODE_HPPA_11 | CS_MODE_LITTLE_ENDIAN },
{ "hppa11be", CS_ARCH_HPPA, CS_MODE_HPPA_11 | CS_MODE_BIG_ENDIAN },
{ "hppa20", CS_ARCH_HPPA, CS_MODE_HPPA_20 | CS_MODE_LITTLE_ENDIAN },
{ "hppa20be", CS_ARCH_HPPA, CS_MODE_HPPA_20 | CS_MODE_BIG_ENDIAN },
{ "hppa20w", CS_ARCH_HPPA, CS_MODE_HPPA_20W | CS_MODE_LITTLE_ENDIAN },
{ "hppa20wbe", CS_ARCH_HPPA, CS_MODE_HPPA_20W | CS_MODE_BIG_ENDIAN },
{ "loongarch32", CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH32 },
{ "loongarch64", CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64 },
{ "arm", "ARM, little endian", CS_ARCH_ARM, CS_MODE_ARM },
{ "armle", "ARM, little endian", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_LITTLE_ENDIAN },
{ "armbe", "ARM, big endian", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_BIG_ENDIAN },
{ "armv8", "ARM v8", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_V8 },
{ "armv8be", "ARM v8, big endian", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_V8 | CS_MODE_BIG_ENDIAN },
{ "cortexm", "ARM Cortex-M Thumb", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_MCLASS },
{ "cortexmv8", "ARM Cortex-M Thumb, v8", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_MCLASS | CS_MODE_V8 },
{ "thumb", "ARM Thumb mode, little endian", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB },
{ "thumble", "ARM Thumb mode, little endian", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_LITTLE_ENDIAN },
{ "thumbbe", "ARM Thumb mode, big endian", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_BIG_ENDIAN },
{ "thumbv8", "ARM Thumb v8", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_V8 },
{ "thumbv8be", "ARM Thumb v8, big endian", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_V8 | CS_MODE_BIG_ENDIAN },
{ "aarch64", "AArch64", CS_ARCH_AARCH64, CS_MODE_LITTLE_ENDIAN },
{ "aarch64be", "AArch64, big endian", CS_ARCH_AARCH64, CS_MODE_BIG_ENDIAN },
{ "alpha", "Alpha, little endian", CS_ARCH_ALPHA, CS_MODE_LITTLE_ENDIAN },
{ "alphabe", "Alpha, big endian", CS_ARCH_ALPHA, CS_MODE_BIG_ENDIAN },
{ "hppa11", "HPPA V1.1, little endian", CS_ARCH_HPPA, CS_MODE_HPPA_11 | CS_MODE_LITTLE_ENDIAN },
{ "hppa11be", "HPPA V1.1, big endian", CS_ARCH_HPPA, CS_MODE_HPPA_11 | CS_MODE_BIG_ENDIAN },
{ "hppa20", "HPPA V2.0, little endian", CS_ARCH_HPPA, CS_MODE_HPPA_20 | CS_MODE_LITTLE_ENDIAN },
{ "hppa20be", "HPPA V2.0, big endian", CS_ARCH_HPPA, CS_MODE_HPPA_20 | CS_MODE_BIG_ENDIAN },
{ "hppa20w", "HPPA V2.0 wide, little endian", CS_ARCH_HPPA, CS_MODE_HPPA_20W | CS_MODE_LITTLE_ENDIAN },
{ "hppa20wbe", "HPPA V2.0 wide, big endian", CS_ARCH_HPPA, CS_MODE_HPPA_20W | CS_MODE_BIG_ENDIAN },
{ "mipsel16", "Mips 16-bit (generic), little endian", CS_ARCH_MIPS, CS_MODE_MIPS16 },
{ "mips16", "Mips 16-bit (generic)", CS_ARCH_MIPS, CS_MODE_MIPS16 | CS_MODE_BIG_ENDIAN },
{ "mipsel", "Mips 32-bit (generic), little endian", CS_ARCH_MIPS, CS_MODE_MIPS32 },
{ "mips", "Mips 32-bit (generic)", CS_ARCH_MIPS, CS_MODE_MIPS32 | CS_MODE_BIG_ENDIAN },
{ "mipsel64", "Mips 64-bit (generic), little endian", CS_ARCH_MIPS, CS_MODE_MIPS64 },
{ "mips64", "Mips 64-bit (generic)", CS_ARCH_MIPS, CS_MODE_MIPS64 | CS_MODE_BIG_ENDIAN },
{ "micromipsel", "MicroMips, little endian", CS_ARCH_MIPS, CS_MODE_MICRO },
{ "micromips", "MicroMips", CS_ARCH_MIPS, CS_MODE_MICRO | CS_MODE_BIG_ENDIAN },
{ "micromipselr3", "MicroMips32r3, little endian", CS_ARCH_MIPS, CS_MODE_MICRO32R3 },
{ "micromipsr3", "MicroMips32r3", CS_ARCH_MIPS, CS_MODE_MICRO32R3 | CS_MODE_BIG_ENDIAN },
{ "micromipselr6", "MicroMips32r6, little endian", CS_ARCH_MIPS, CS_MODE_MICRO32R6 },
{ "micromipsr6", "MicroMips32r6", CS_ARCH_MIPS, CS_MODE_MICRO32R6 | CS_MODE_BIG_ENDIAN },
{ "mipsel1", "Mips I ISA, little endian", CS_ARCH_MIPS, CS_MODE_MIPS1 },
{ "mips1", "Mips I ISA", CS_ARCH_MIPS, CS_MODE_MIPS1 | CS_MODE_BIG_ENDIAN },
{ "mipsel2", "Mips II ISA, little endian", CS_ARCH_MIPS, CS_MODE_MIPS2 },
{ "mips2", "Mips II ISA", CS_ARCH_MIPS, CS_MODE_MIPS2 | CS_MODE_BIG_ENDIAN },
{ "mipsel32r2", "Mips32 r2 ISA, little endian", CS_ARCH_MIPS, CS_MODE_MIPS32R2 },
{ "mips32r2", "Mips32 r2 ISA", CS_ARCH_MIPS, CS_MODE_MIPS32R2 | CS_MODE_BIG_ENDIAN },
{ "mipsel32r3", "Mips32 r3 ISA, little endian", CS_ARCH_MIPS, CS_MODE_MIPS32R3 },
{ "mips32r3", "Mips32 r3 ISA", CS_ARCH_MIPS, CS_MODE_MIPS32R3 | CS_MODE_BIG_ENDIAN },
{ "mipsel32r5", "Mips32 r5 ISA, little endian", CS_ARCH_MIPS, CS_MODE_MIPS32R5 },
{ "mips32r5", "Mips32 r5 ISA", CS_ARCH_MIPS, CS_MODE_MIPS32R5 | CS_MODE_BIG_ENDIAN },
{ "mipsel32r6", "Mips32 r6 ISA, little endian", CS_ARCH_MIPS, CS_MODE_MIPS32R6 },
{ "mips32r6", "Mips32 r6 ISA", CS_ARCH_MIPS, CS_MODE_MIPS32R6 | CS_MODE_BIG_ENDIAN },
{ "mipsel3", "Mips III ISA, little endian", CS_ARCH_MIPS, CS_MODE_MIPS3 },
{ "mips3", "Mips III ISA", CS_ARCH_MIPS, CS_MODE_MIPS3 | CS_MODE_BIG_ENDIAN },
{ "mipsel4", "Mips IV ISA, little endian", CS_ARCH_MIPS, CS_MODE_MIPS4 },
{ "mips4", "Mips IV ISA", CS_ARCH_MIPS, CS_MODE_MIPS4 | CS_MODE_BIG_ENDIAN },
{ "mipsel5", "Mips V ISA, little endian", CS_ARCH_MIPS, CS_MODE_MIPS5 },
{ "mips5", "Mips V ISA", CS_ARCH_MIPS, CS_MODE_MIPS5 | CS_MODE_BIG_ENDIAN },
{ "mipsel64r2", "Mips64 r2 ISA, little endian", CS_ARCH_MIPS, CS_MODE_MIPS64R2 },
{ "mips64r2", "Mips64 r2 ISA", CS_ARCH_MIPS, CS_MODE_MIPS64R2 | CS_MODE_BIG_ENDIAN },
{ "mipsel64r3", "Mips64 r3 ISA, little endian", CS_ARCH_MIPS, CS_MODE_MIPS64R3 },
{ "mips64r3", "Mips64 r3 ISA", CS_ARCH_MIPS, CS_MODE_MIPS64R3 | CS_MODE_BIG_ENDIAN },
{ "mipsel64r5", "Mips64 r5 ISA, little endian", CS_ARCH_MIPS, CS_MODE_MIPS64R5 },
{ "mips64r5", "Mips64 r5 ISA", CS_ARCH_MIPS, CS_MODE_MIPS64R5 | CS_MODE_BIG_ENDIAN },
{ "mipsel64r6", "Mips64 r6 ISA, little endian", CS_ARCH_MIPS, CS_MODE_MIPS64R6 },
{ "mips64r6", "Mips64 r6 ISA", CS_ARCH_MIPS, CS_MODE_MIPS64R6 | CS_MODE_BIG_ENDIAN },
{ "octeonle", "Octeon cnMIPS, little endian", CS_ARCH_MIPS, CS_MODE_OCTEON },
{ "octeon", "Octeon cnMIPS", CS_ARCH_MIPS, CS_MODE_OCTEON | CS_MODE_BIG_ENDIAN },
{ "octeonple", "Octeon+ cnMIPS, little endian", CS_ARCH_MIPS, CS_MODE_OCTEONP },
{ "octeonp", "Octeon+ cnMIPS", CS_ARCH_MIPS, CS_MODE_OCTEONP | CS_MODE_BIG_ENDIAN },
{ "nanomips", "nanoMIPS", CS_ARCH_MIPS, CS_MODE_NANOMIPS },
{ "nms1", "nanoMIPS Subset", CS_ARCH_MIPS, CS_MODE_NMS1 },
{ "i7200", "nanoMIPS i7200", CS_ARCH_MIPS, CS_MODE_I7200 },
{ "x16", "x86 16-bit mode", CS_ARCH_X86, CS_MODE_16 }, // CS_MODE_16
{ "x32", "x86 32-bit mode", CS_ARCH_X86, CS_MODE_32 }, // CS_MODE_32
{ "x64", "x86 64-bit mode", CS_ARCH_X86, CS_MODE_64 }, // CS_MODE_64
{ "ppc32", "PowerPC 32-bit, little endian", CS_ARCH_PPC, CS_MODE_32 | CS_MODE_LITTLE_ENDIAN },
{ "ppc32be", "PowerPC 32-bit, big endian", CS_ARCH_PPC, CS_MODE_32 | CS_MODE_BIG_ENDIAN },
{ "ppc32qpx", "PowerPC 32-bit, qpx, little endian", CS_ARCH_PPC, CS_MODE_32 | CS_MODE_QPX | CS_MODE_LITTLE_ENDIAN },
{ "ppc32beqpx", "PowerPC 32-bit, qpx, big endian", CS_ARCH_PPC, CS_MODE_32 | CS_MODE_QPX | CS_MODE_BIG_ENDIAN },
{ "ppc32ps", "PowerPC 32-bit, ps, little endian", CS_ARCH_PPC, CS_MODE_32 | CS_MODE_PS | CS_MODE_LITTLE_ENDIAN },
{ "ppc32beps", "PowerPC 32-bit, ps, big endian", CS_ARCH_PPC, CS_MODE_32 | CS_MODE_PS | CS_MODE_BIG_ENDIAN },
{ "ppc64", "PowerPC 64-bit, little endian", CS_ARCH_PPC, CS_MODE_64 | CS_MODE_LITTLE_ENDIAN },
{ "ppc64be", "PowerPC 64-bit, big endian", CS_ARCH_PPC, CS_MODE_64 | CS_MODE_BIG_ENDIAN },
{ "ppc64qpx", "PowerPC 64-bit, qpx, little endian", CS_ARCH_PPC, CS_MODE_64 | CS_MODE_QPX | CS_MODE_LITTLE_ENDIAN },
{ "ppc64beqpx", "PowerPC 64-bit, qpx, big endian", CS_ARCH_PPC, CS_MODE_64 | CS_MODE_QPX | CS_MODE_BIG_ENDIAN },
{ "sparc", "Sparc, big endian", CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN },
{ "sparcv9", "Sparc v9, big endian", CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN | CS_MODE_V9 },
{ "systemz", "SystemZ, big endian", CS_ARCH_SYSZ, CS_MODE_BIG_ENDIAN },
{ "s390x", "SystemZ s390x, big endian", CS_ARCH_SYSZ, CS_MODE_BIG_ENDIAN },
{ "xcore", "xcore, big endian", CS_ARCH_XCORE, CS_MODE_BIG_ENDIAN },
{ "m68k", "m68k + big endian", CS_ARCH_M68K, CS_MODE_BIG_ENDIAN },
{ "m68k40", "m68k40", CS_ARCH_M68K, CS_MODE_M68K_040 },
{ "tms320c64x", "tms320c64x, big endian", CS_ARCH_TMS320C64X, CS_MODE_BIG_ENDIAN },
{ "m6800", "m680x, M6800/2", CS_ARCH_M680X, CS_MODE_M680X_6800 },
{ "m6801", "m680x, M6801/3", CS_ARCH_M680X, CS_MODE_M680X_6801 },
{ "m6805", "m680x, M6805", CS_ARCH_M680X, CS_MODE_M680X_6805 },
{ "m6808", "m680x, M68HC08", CS_ARCH_M680X, CS_MODE_M680X_6808 },
{ "m6809", "m680x, M6809", CS_ARCH_M680X, CS_MODE_M680X_6809 },
{ "m6811", "m680x, M68HC11", CS_ARCH_M680X, CS_MODE_M680X_6811 },
{ "cpu12", "m680x, M68HC12/HCS12", CS_ARCH_M680X, CS_MODE_M680X_CPU12 },
{ "hd6301", "m680x, HD6301/3", CS_ARCH_M680X, CS_MODE_M680X_6301 },
{ "hd6309", "m680x, HD6309", CS_ARCH_M680X, CS_MODE_M680X_6309 },
{ "hcs08", "m680x, HCS08", CS_ARCH_M680X, CS_MODE_M680X_HCS08 },
{ "evm", "ethereum virtual machine", CS_ARCH_EVM, 0 },
{ "wasm", "web assembly", CS_ARCH_WASM, 0 },
{ "bpf", "Classic BPF, little endian", CS_ARCH_BPF, CS_MODE_LITTLE_ENDIAN | CS_MODE_BPF_CLASSIC },
{ "bpfbe", "Classic BPF, big endian", CS_ARCH_BPF, CS_MODE_BIG_ENDIAN | CS_MODE_BPF_CLASSIC },
{ "ebpf", "Extended BPF, little endian", CS_ARCH_BPF, CS_MODE_LITTLE_ENDIAN | CS_MODE_BPF_EXTENDED },
{ "ebpfbe", "Extended BPF, big endian", CS_ARCH_BPF, CS_MODE_BIG_ENDIAN | CS_MODE_BPF_EXTENDED },
{ "riscv32", "Risc-V 32-bit, little endian", CS_ARCH_RISCV, CS_MODE_RISCV32 | CS_MODE_RISCVC },
{ "riscv64", "Risc-V 64-bit, little endian", CS_ARCH_RISCV, CS_MODE_RISCV64 | CS_MODE_RISCVC },
{ "6502", "MOS 6502", CS_ARCH_MOS65XX, CS_MODE_MOS65XX_6502 },
{ "65c02", "WDC 65c02", CS_ARCH_MOS65XX, CS_MODE_MOS65XX_65C02 },
{ "w65c02", "WDC w65c02", CS_ARCH_MOS65XX, CS_MODE_MOS65XX_W65C02 },
{ "65816", "WDC 65816 (long m/x)", CS_ARCH_MOS65XX, CS_MODE_MOS65XX_65816_LONG_MX },
{ "sh", "SuperH SH1", CS_ARCH_SH, CS_MODE_BIG_ENDIAN },
{ "sh2", "SuperH SH2", CS_ARCH_SH, CS_MODE_SH2 | CS_MODE_BIG_ENDIAN},
{ "sh2e", "SuperH SH2E", CS_ARCH_SH, CS_MODE_SH2 | CS_MODE_SHFPU | CS_MODE_BIG_ENDIAN},
{ "sh-dsp", "SuperH SH2-DSP", CS_ARCH_SH, CS_MODE_SH2 | CS_MODE_SHDSP | CS_MODE_BIG_ENDIAN},
{ "sh2a", "SuperH SH2A", CS_ARCH_SH, CS_MODE_SH2A | CS_MODE_BIG_ENDIAN},
{ "sh2a-fpu", "SuperH SH2A-FPU", CS_ARCH_SH, CS_MODE_SH2A | CS_MODE_SHFPU | CS_MODE_BIG_ENDIAN},
{ "sh3", "SuperH SH3", CS_ARCH_SH, CS_MODE_LITTLE_ENDIAN | CS_MODE_SH3 },
{ "sh3be", "SuperH SH3, big endian", CS_ARCH_SH, CS_MODE_BIG_ENDIAN | CS_MODE_SH3 },
{ "sh3e", "SuperH SH3E", CS_ARCH_SH, CS_MODE_LITTLE_ENDIAN | CS_MODE_SH3 | CS_MODE_SHFPU},
{ "sh3ebe", "SuperH SH3E, big endian", CS_ARCH_SH, CS_MODE_BIG_ENDIAN | CS_MODE_SH3 | CS_MODE_SHFPU},
{ "sh3-dsp", "SuperH SH3-DSP", CS_ARCH_SH, CS_MODE_LITTLE_ENDIAN | CS_MODE_SH3 | CS_MODE_SHDSP },
{ "sh3-dspbe", "SuperH SH3-DSP, big endian", CS_ARCH_SH, CS_MODE_BIG_ENDIAN | CS_MODE_SH3 | CS_MODE_SHDSP },
{ "sh4", "SuperH SH4", CS_ARCH_SH, CS_MODE_LITTLE_ENDIAN | CS_MODE_SH4 | CS_MODE_SHFPU },
{ "sh4be", "SuperH SH4, big endian", CS_ARCH_SH, CS_MODE_BIG_ENDIAN | CS_MODE_SH4 | CS_MODE_SHFPU },
{ "sh4a", "SuperH SH4A", CS_ARCH_SH, CS_MODE_LITTLE_ENDIAN | CS_MODE_SH4A | CS_MODE_SHFPU },
{ "sh4abe", "SuperH SH4A, big endian", CS_ARCH_SH, CS_MODE_BIG_ENDIAN | CS_MODE_SH4A | CS_MODE_SHFPU },
{ "sh4al-dsp", "SuperH SH4AL-DSP", CS_ARCH_SH, CS_MODE_LITTLE_ENDIAN | CS_MODE_SH4A | CS_MODE_SHDSP | CS_MODE_SHFPU },
{ "sh4al-dspbe", "SuperH SH4AL-DSP, big endian", CS_ARCH_SH, CS_MODE_BIG_ENDIAN | CS_MODE_SH4A | CS_MODE_SHDSP | CS_MODE_SHFPU },
{ "tc110", "Tricore V1.1", CS_ARCH_TRICORE, CS_MODE_TRICORE_110 },
{ "tc120", "Tricore V1.2", CS_ARCH_TRICORE, CS_MODE_TRICORE_120 },
{ "tc130", "Tricore V1.3", CS_ARCH_TRICORE, CS_MODE_TRICORE_130 },
{ "tc131", "Tricore V1.3.1", CS_ARCH_TRICORE, CS_MODE_TRICORE_131 },
{ "tc160", "Tricore V1.6", CS_ARCH_TRICORE, CS_MODE_TRICORE_160 },
{ "tc161", "Tricore V1.6.1", CS_ARCH_TRICORE, CS_MODE_TRICORE_161 },
{ "tc162", "Tricore V1.6.2", CS_ARCH_TRICORE, CS_MODE_TRICORE_162 },
{ "loongarch32", "LoongArch 32-bit", CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH32 },
{ "loongarch64", "LoongArch 64-bit", CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64 },
{ NULL }
};
@ -185,168 +274,63 @@ static uint8_t *preprocess(char *code, size_t *size)
return result;
}
static const char *get_arch_name(cs_arch arch)
{
switch(arch) {
case CS_ARCH_ARM: return "ARM";
case CS_ARCH_AARCH64: return "Arm64";
case CS_ARCH_MIPS: return "Mips";
case CS_ARCH_X86: return "x86";
case CS_ARCH_PPC: return "PowerPC";
case CS_ARCH_SPARC: return "Sparc";
case CS_ARCH_SYSZ: return "SysZ";
case CS_ARCH_XCORE: return "Xcore";
case CS_ARCH_M68K: return "M68K";
case CS_ARCH_TMS320C64X: return "TMS320C64X";
case CS_ARCH_M680X: return "M680X";
case CS_ARCH_EVM: return "Evm";
case CS_ARCH_MOS65XX: return "MOS65XX";
case CS_ARCH_WASM: return "Wasm";
case CS_ARCH_BPF: return "BPF";
case CS_ARCH_RISCV: return "RiscV";
case CS_ARCH_SH: return "SH";
case CS_ARCH_TRICORE: return "TriCore";
case CS_ARCH_ALPHA: return "Alpha";
case CS_ARCH_HPPA: return "HPPA";
case CS_ARCH_LOONGARCH: return "LoongArch";
default: return NULL;
}
}
static void usage(char *prog)
{
int i, j;
printf("Cstool for Capstone Disassembler Engine v%u.%u.%u\n\n", CS_VERSION_MAJOR, CS_VERSION_MINOR, CS_VERSION_EXTRA);
printf("Syntax: %s [-d|-a|-r|-s|-u|-v] <arch+mode> <assembly-hexstring> [start-address-in-hex-format]\n", prog);
printf("\nThe following <arch+mode> options are supported:\n");
printf("Syntax: %s [-d|-a|-r|-s|-u|-v] <arch+opts> <assembly-hexstring> [start-address-in-hex-format]\n", prog);
printf("\nThe following <arch+opts> options are supported:\n");
if (cs_support(CS_ARCH_X86)) {
printf(" x16 16-bit mode (X86)\n");
printf(" x32 32-bit mode (X86)\n");
printf(" x64 64-bit mode (X86)\n");
printf(" x16att 16-bit mode (X86), syntax AT&T\n");
printf(" x32att 32-bit mode (X86), syntax AT&T\n");
printf(" x64att 64-bit mode (X86), syntax AT&T\n");
for (i = 0; all_archs[i].name; i++) {
if (cs_support(all_archs[i].arch)) {
printf(" %-16s %s\n", all_archs[i].name, all_archs[i].desc);
}
}
if (cs_support(CS_ARCH_ARM)) {
printf(" arm arm\n");
printf(" armbe arm + big endian\n");
printf(" thumb thumb mode\n");
printf(" thumbbe thumb + big endian\n");
printf(" cortexm thumb + cortex-m extensions\n");
printf(" cortexv8m thumb + cortex-m extensions + v8\n");
printf(" armv8 arm v8\n");
printf(" thumbv8 thumb v8\n");
printf(" armv8be arm v8 + big endian\n");
printf(" thumbv8be thumb v8 + big endian\n");
}
if (cs_support(CS_ARCH_AARCH64)) {
printf(" aarch64 aarch64 mode\n");
printf(" aarch64be aarch64 + big endian\n");
}
if (cs_support(CS_ARCH_ALPHA)) {
printf(" alpha alpha + little endian\n");
printf(" alphabe alpha + big endian\n");
}
if (cs_support(CS_ARCH_HPPA)) {
printf(" hppa11 hppa V1.1 + little endian\n");
printf(" hppa11be hppa V1.1 + big endian\n");
printf(" hppa20 hppa V2.0 + little endian\n");
printf(" hppa20be hppa V2.0 + big endian\n");
printf(" hppa20w hppa V2.0 wide + little endian\n");
printf(" hppa20wbe hppa V2.0 wide + big endian\n");
}
if (cs_support(CS_ARCH_MIPS)) {
printf(" mips mips32 + little endian\n");
printf(" mipsbe mips32 + big endian\n");
printf(" mips64 mips64 + little endian\n");
printf(" mips64be mips64 + big endian\n");
}
if (cs_support(CS_ARCH_PPC)) {
printf(" ppc32 ppc32 + little endian\n");
printf(" ppc32be ppc32 + big endian\n");
printf(" ppc32qpx ppc32 + qpx + little endian\n");
printf(" ppc32beqpx ppc32 + qpx + big endian\n");
printf(" ppc32ps ppc32 + ps + little endian\n");
printf(" ppc32beps ppc32 + ps + big endian\n");
printf(" ppc64 ppc64 + little endian\n");
printf(" ppc64be ppc64 + big endian\n");
printf(" ppc64qpx ppc64 + qpx + little endian\n");
printf(" ppc64beqpx ppc64 + qpx + big endian\n");
}
if (cs_support(CS_ARCH_SPARC)) {
printf(" sparc sparc\n");
}
if (cs_support(CS_ARCH_SYSZ)) {
printf(" systemz systemz (s390x)\n");
}
if (cs_support(CS_ARCH_XCORE)) {
printf(" xcore xcore\n");
}
if (cs_support(CS_ARCH_M68K)) {
printf(" m68k m68k + big endian\n");
printf(" m68k40 m68k_040\n");
}
if (cs_support(CS_ARCH_TMS320C64X)) {
printf(" tms320c64x TMS320C64x\n");
}
if (cs_support(CS_ARCH_M680X)) {
printf(" m6800 M6800/2\n");
printf(" m6801 M6801/3\n");
printf(" m6805 M6805\n");
printf(" m6808 M68HC08\n");
printf(" m6809 M6809\n");
printf(" m6811 M68HC11\n");
printf(" cpu12 M68HC12/HCS12\n");
printf(" hd6301 HD6301/3\n");
printf(" hd6309 HD6309\n");
printf(" hcs08 HCS08\n");
}
if (cs_support(CS_ARCH_EVM)) {
printf(" evm Ethereum Virtual Machine\n");
}
if (cs_support(CS_ARCH_MOS65XX)) {
printf(" 6502 MOS 6502\n");
printf(" 65c02 WDC 65c02\n");
printf(" w65c02 WDC w65c02\n");
printf(" 65816 WDC 65816 (long m/x)\n");
}
if (cs_support(CS_ARCH_WASM)) {
printf(" wasm: Web Assembly\n");
}
if (cs_support(CS_ARCH_BPF)) {
printf(" bpf Classic BPF\n");
printf(" bpfbe Classic BPF + big endian\n");
printf(" ebpf Extended BPF\n");
printf(" ebpfbe Extended BPF + big endian\n");
}
if (cs_support(CS_ARCH_RISCV)) {
printf(" riscv32 riscv32\n");
printf(" riscv64 riscv64\n");
}
if (cs_support(CS_ARCH_SH)) {
printf(" sh superh SH1\n");
printf(" sh2 superh SH2\n");
printf(" sh2e superh SH2E\n");
printf(" sh2dsp superh SH2-DSP\n");
printf(" sh2a superh SH2A\n");
printf(" sh2afpu superh SH2A-FPU\n");
printf(" sh3 superh SH3\n");
printf(" sh3be superh SH3 big endian\n");
printf(" sh3e superh SH3E\n");
printf(" sh3ebe superh SH3E big endian\n");
printf(" sh3-dsp superh SH3-DSP\n");
printf(" sh3-dspbe superh SH3-DSP big endian\n");
printf(" sh4 superh SH4\n");
printf(" sh4be superh SH4 big endian\n");
printf(" sh4a superh SH4A\n");
printf(" sh4abe superh SH4A big endian\n");
printf(" sh4al-dsp superh SH4AL-DSP\n");
printf(" sh4al-dspbe superh SH4AL-DSP big endian\n");
}
if (cs_support(CS_ARCH_TRICORE)) {
printf(" tc110 tricore V1.1\n");
printf(" tc120 tricore V1.2\n");
printf(" tc130 tricore V1.3\n");
printf(" tc131 tricore V1.3.1\n");
printf(" tc160 tricore V1.6\n");
printf(" tc161 tricore V1.6.1\n");
printf(" tc162 tricore V1.6.2\n");
}
if (cs_support(CS_ARCH_LOONGARCH)) {
printf(" loongarch32 LoongArch32\n");
printf(" loongarch64 LoongArch64\n");
printf("\nArch specific options:\n");
for (i = 0; all_opts[i].name; i++) {
printf(" %-16s %s (only: ", all_opts[i].name, all_opts[i].desc);
for (j = 0; j < CS_ARCH_MAX; j++) {
cs_arch arch = all_opts[i].archs[j];
const char *name = get_arch_name(arch);
if (!name) {
break;
}
if (j > 0) {
printf(", %s", name);
} else {
printf("%s", name);
}
}
printf(")\n");
}
printf("\nExtra options:\n");
@ -494,17 +478,55 @@ static void run_dev_fuzz(csh handle, uint8_t *bytes, uint32_t size) {
}
}
static cs_mode find_additional_modes(const char *input, cs_arch arch) {
if (!input) {
return 0;
}
cs_mode mode = 0;
int i, j;
for (i = 0; all_opts[i].name; i++) {
if (all_opts[i].opt || !strstr(input, all_opts[i].name)) {
continue;
}
for (j = 0; j < CS_ARCH_MAX; j++) {
if (arch == all_opts[i].archs[j]) {
mode |= all_opts[i].mode;
break;
}
}
}
return mode;
}
static void enable_additional_options(csh handle, const char *input, cs_arch arch) {
if (!input) {
return;
}
int i, j;
for (i = 0; all_opts[i].name; i++) {
if (all_opts[i].mode || !strstr(input, all_opts[i].name)) {
continue;
}
for (j = 0; j < CS_ARCH_MAX; j++) {
if (arch == all_opts[i].archs[j]) {
cs_option(handle, CS_OPT_SYNTAX, all_opts[i].opt);
break;
}
}
}
}
int main(int argc, char **argv)
{
int i, c;
csh handle;
char *mode;
char *choosen_arch;
uint8_t *assembly;
size_t count, size;
uint64_t address = 0LL;
cs_insn *insn;
cs_err err;
cs_mode md;
cs_mode mode;
cs_arch arch = CS_ARCH_ALL;
bool detail_flag = false;
bool unsigned_flag = false;
@ -647,7 +669,7 @@ int main(int argc, char **argv)
return -1;
}
mode = argv[optind];
choosen_arch = argv[optind];
assembly = preprocess(argv[optind + 1], &size);
if (!assembly) {
usage(argv[0]);
@ -658,37 +680,46 @@ int main(int argc, char **argv)
char *temp, *src = argv[optind + 2];
address = strtoull(src, &temp, 16);
if (temp == src || *temp != '\0' || errno == ERANGE) {
printf("ERROR: invalid address argument, quit!\n");
fprintf(stderr, "ERROR: invalid address argument, quit!\n");
return -2;
}
}
size_t arch_len = strlen(choosen_arch);
const char *plus = strchr(choosen_arch, '+');
if (plus) {
arch_len = plus - choosen_arch;
}
for (i = 0; all_archs[i].name; i++) {
if (!strcmp(all_archs[i].name, mode)) {
size_t len = strlen(all_archs[i].name);
if (len == arch_len && !strncmp(all_archs[i].name, choosen_arch, arch_len)) {
arch = all_archs[i].arch;
err = cs_open(all_archs[i].arch, all_archs[i].mode, &handle);
mode = all_archs[i].mode;
mode |= find_additional_modes(plus, arch);
err = cs_open(all_archs[i].arch, mode, &handle);
if (!err) {
md = all_archs[i].mode;
if (strstr (mode, "att")) {
cs_option(handle, CS_OPT_SYNTAX, CS_OPT_SYNTAX_ATT);
}
enable_additional_options(handle, plus, arch);
// turn on SKIPDATA mode
if (skipdata)
if (skipdata) {
cs_option(handle, CS_OPT_SKIPDATA, CS_OPT_ON);
}
}
break;
}
}
if (arch == CS_ARCH_ALL) {
printf("ERROR: Invalid <arch+mode>: \"%s\", quit!\n", mode);
fprintf(stderr, "ERROR: Invalid <arch+mode>: \"%s\", quit!\n", choosen_arch);
usage(argv[0]);
return -1;
}
if (err) {
printf("ERROR: Failed on cs_open(), quit!\n");
const char *error = cs_strerror(err);
fprintf(stderr, "ERROR: Failed on cs_open(): %s\n", error);
usage(argv[0]);
return -1;
}
@ -745,14 +776,14 @@ int main(int argc, char **argv)
printf(" %s\t%s\n", insn[i].mnemonic, insn[i].op_str);
if (detail_flag) {
print_details(handle, arch, md, &insn[i]);
print_details(handle, arch, mode, &insn[i]);
}
}
cs_free(insn, count);
free(assembly);
} else {
printf("ERROR: invalid assembly code\n");
fprintf(stderr, "ERROR: invalid assembly code\n");
cs_close(&handle);
free(assembly);
return(-4);

2
cstool/cstool_mips.c
View File

@ -27,9 +27,11 @@ void print_insn_detail_mips(csh handle, cs_insn *ins)
break;
case MIPS_OP_REG:
printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg));
printf("\t\toperands[%u].is_reglist: %s\n", i, op->is_reglist ? "true" : "false");
break;
case MIPS_OP_IMM:
printf("\t\toperands[%u].type: IMM = 0x%" PRIx64 "\n", i, op->imm);
printf("\t\toperands[%u].is_unsigned: %s\n", i, op->is_unsigned ? "true" : "false");
break;
case MIPS_OP_MEM:
printf("\t\toperands[%u].type: MEM\n", i);

91
docs/cs_v6_release_guide.md
View File

@ -167,6 +167,53 @@ sed -i "s|detail->arm64|detail->aarch64|g" $1
Write it into `rename_arm64.sh` and run it on files with `sh rename_arm64.sh <src-file>`
**Mips**
| Keyword | Change | Justification | Possible revert |
|---------|--------|---------------|-----------------|
| `CS_OPT_SYNTAX_NO_DOLLAR` | Adds options which removes the `$` (dollar sign) from the register name. | New Feature | Enable option. |
| `CS_OPT_SYNTAX_NOREGNAME` | Implements the options to output raw register numbers (only the standard GPR are numeric). | Was not implemented | Enable option. |
| `cs_mips_op.uimm` | Access for the unsigned immediate value of the IMM operand. | Was missing | None. |
| `cs_mips_op.is_unsigned` | Defines if the IMM operand is signed (when false) or unsigned (when true). | Was missing | None. |
| `cs_mips_op.is_reglist` | Defines if the REG operand is part of a list of registers. | Was missing | None. |
| `cs_mips_op.access` | Defines how is this operand accessed, i.e. READ, WRITE or READ & WRITE. | Was missing | None. |
**Note about AArch64**
in `capstone.h` new mips ISA has been added which can be used by themselves.
```
CS_MODE_MIPS16 = CS_MODE_16, ///< Generic mips16
CS_MODE_MIPS32 = CS_MODE_32, ///< Generic mips32
CS_MODE_MIPS64 = CS_MODE_64, ///< Generic mips64
CS_MODE_MICRO = 1 << 4, ///< microMips
CS_MODE_MIPS1 = 1 << 5, ///< Mips I ISA Support
CS_MODE_MIPS2 = 1 << 6, ///< Mips II ISA Support
CS_MODE_MIPS32R2 = 1 << 7, ///< Mips32r2 ISA Support
CS_MODE_MIPS32R3 = 1 << 8, ///< Mips32r3 ISA Support
CS_MODE_MIPS32R5 = 1 << 9, ///< Mips32r5 ISA Support
CS_MODE_MIPS32R6 = 1 << 10, ///< Mips32r6 ISA Support
CS_MODE_MIPS3 = 1 << 11, ///< MIPS III ISA Support
CS_MODE_MIPS4 = 1 << 12, ///< MIPS IV ISA Support
CS_MODE_MIPS5 = 1 << 13, ///< MIPS V ISA Support
CS_MODE_MIPS64R2 = 1 << 14, ///< Mips64r2 ISA Support
CS_MODE_MIPS64R3 = 1 << 15, ///< Mips64r3 ISA Support
CS_MODE_MIPS64R5 = 1 << 16, ///< Mips64r5 ISA Support
CS_MODE_MIPS64R6 = 1 << 17, ///< Mips64r6 ISA Support
CS_MODE_OCTEON = 1 << 18, ///< Octeon cnMIPS Support
CS_MODE_OCTEONP = 1 << 19, ///< Octeon+ cnMIPS Support
CS_MODE_NANOMIPS = 1 << 20, ///< Generic nanomips
CS_MODE_NMS1 = ((1 << 21) | CS_MODE_NANOMIPS), ///< nanoMips NMS1
CS_MODE_I7200 = ((1 << 22) | CS_MODE_NANOMIPS), ///< nanoMips I7200
CS_MODE_MICRO32R3 = (CS_MODE_MICRO | CS_MODE_MIPS32R3), ///< microMips32r3
CS_MODE_MICRO32R6 = (CS_MODE_MICRO | CS_MODE_MIPS32R6), ///< microMips32r6
```
It is also possible to disable floating point support by adding `CS_MODE_MIPS_NOFLOAT`.
**`CS_MODE_MIPS_PTR64` is now required to decode 64-bit pointers**, like jumps and calls (for example: `jal $t0`).
## New features
These features are only supported by `auto-sync`-enabled architectures.
@ -250,3 +297,47 @@ Nonetheless, an alias should never be **decoded** as real instruction.
If you find an alias which is decoded as a real instruction, please let us know.
Such an instruction is ill-defined in LLVM and should be fixed upstream.
### Refactoring of cstool
`cstool` has been refactored to simplify its usage; before you needed to add extra options in the C code to enable features and recompile, but now you can easily decode instructions with different syntaxes or options, by appending after the arch one of the followings values:
```
+att ATT syntax (only: x86)
+intel Intel syntax (only: x86)
+masm Intel MASM syntax (only: x86)
+noregname Number only registers (only: Arm64, ARM, LoongArch, Mips, PowerPC)
+moto Use $ as hex prefix (only: MOS65XX)
+regalias Use register aliases, like r9 > sb (only: ARM, Arm64)
+percentage Adds % in front of the registers (only: PowerPC)
+nodollar Removes $ in front of the registers (only: Mips)
+nofloat Disables floating point support (only: Mips)
+ptr64 Enables 64-bit pointers support (only: Mips)
```
For example:
```
$ cstool -s ppc32+percentage 0c100097
0 0c 10 00 97 stwu %r24, 0x100c(0)
$ cstool -s ppc32 0c100097
0 0c 10 00 97 stwu r24, 0x100c(0)
$ cstool -s x32+att 0c1097
0 0c 10 orb $0x10, %al
2 97 xchgl %eax, %edi
$ cstool -s x32+intel 0c1097
0 0c 10 or al, 0x10
2 97 xchg edi, eax
$ cstool -s x32+masm 0c1097
0 0c 10 or al, 10h
2 97 xchg edi, eax
$ cstool -s arm+regalias 0c100097000000008fa2000034213456
0 0c 10 00 97 strls r1, [r0, -ip]
4 00 00 00 00 andeq r0, r0, r0
8 8f a2 00 00 andeq sl, r0, pc, lsl #5
10 34 21 34 56 shasxpl r2, r4, r4
$ cstool -s arm 0c100097000000008fa2000034213456
0 0c 10 00 97 strls r1, [r0, -r12]
4 00 00 00 00 andeq r0, r0, r0
8 8f a2 00 00 andeq r10, r0, pc, lsl #5
10 34 21 34 56 shasxpl r2, r4, r4
```

39
include/capstone/capstone.h
View File

@ -183,10 +183,6 @@ typedef enum cs_mode {
CS_MODE_THUMB = 1 << 4, ///< ARM's Thumb mode, including Thumb-2
CS_MODE_MCLASS = 1 << 5, ///< ARM's Cortex-M series
CS_MODE_V8 = 1 << 6, ///< ARMv8 A32 encodings for ARM
CS_MODE_MICRO = 1 << 4, ///< MicroMips mode (MIPS)
CS_MODE_MIPS3 = 1 << 5, ///< Mips III ISA
CS_MODE_MIPS32R6 = 1 << 6, ///< Mips32r6 ISA
CS_MODE_MIPS2 = 1 << 7, ///< Mips II ISA
CS_MODE_V9 = 1 << 4, ///< SparcV9 mode (Sparc)
CS_MODE_QPX = 1 << 4, ///< Quad Processing eXtensions mode (PPC)
CS_MODE_SPE = 1 << 5, ///< Signal Processing Engine mode (PPC)
@ -198,9 +194,33 @@ typedef enum cs_mode {
CS_MODE_M68K_030 = 1 << 4, ///< M68K 68030 mode
CS_MODE_M68K_040 = 1 << 5, ///< M68K 68040 mode
CS_MODE_M68K_060 = 1 << 6, ///< M68K 68060 mode
CS_MODE_BIG_ENDIAN = 1U << 31, ///< big-endian mode
CS_MODE_MIPS32 = CS_MODE_32, ///< Mips32 ISA (Mips)
CS_MODE_MIPS64 = CS_MODE_64, ///< Mips64 ISA (Mips)
CS_MODE_BIG_ENDIAN = 1U << 31, ///< big-endian mode
CS_MODE_MIPS16 = CS_MODE_16, ///< Generic mips16
CS_MODE_MIPS32 = CS_MODE_32, ///< Generic mips32
CS_MODE_MIPS64 = CS_MODE_64, ///< Generic mips64
CS_MODE_MICRO = 1 << 4, ///< microMips
CS_MODE_MIPS1 = 1 << 5, ///< Mips I ISA Support
CS_MODE_MIPS2 = 1 << 6, ///< Mips II ISA Support
CS_MODE_MIPS32R2 = 1 << 7, ///< Mips32r2 ISA Support
CS_MODE_MIPS32R3 = 1 << 8, ///< Mips32r3 ISA Support
CS_MODE_MIPS32R5 = 1 << 9, ///< Mips32r5 ISA Support
CS_MODE_MIPS32R6 = 1 << 10, ///< Mips32r6 ISA Support
CS_MODE_MIPS3 = 1 << 11, ///< MIPS III ISA Support
CS_MODE_MIPS4 = 1 << 12, ///< MIPS IV ISA Support
CS_MODE_MIPS5 = 1 << 13, ///< MIPS V ISA Support
CS_MODE_MIPS64R2 = 1 << 14, ///< Mips64r2 ISA Support
CS_MODE_MIPS64R3 = 1 << 15, ///< Mips64r3 ISA Support
CS_MODE_MIPS64R5 = 1 << 16, ///< Mips64r5 ISA Support
CS_MODE_MIPS64R6 = 1 << 17, ///< Mips64r6 ISA Support
CS_MODE_OCTEON = 1 << 18, ///< Octeon cnMIPS Support
CS_MODE_OCTEONP = 1 << 19, ///< Octeon+ cnMIPS Support
CS_MODE_NANOMIPS = 1 << 20, ///< Generic nanomips
CS_MODE_NMS1 = ((1 << 21) | CS_MODE_NANOMIPS), ///< nanoMips NMS1
CS_MODE_I7200 = ((1 << 22) | CS_MODE_NANOMIPS), ///< nanoMips I7200
CS_MODE_MIPS_NOFLOAT = 1 << 23, ///< Disable floating points ops
CS_MODE_MIPS_PTR64 = 1 << 24, ///< Mips pointers are 64-bit
CS_MODE_MICRO32R3 = (CS_MODE_MICRO | CS_MODE_MIPS32R3), ///< microMips32r3
CS_MODE_MICRO32R6 = (CS_MODE_MICRO | CS_MODE_MIPS32R6), ///< microMips32r6
CS_MODE_M680X_6301 = 1 << 1, ///< M680X Hitachi 6301,6303 mode
CS_MODE_M680X_6309 = 1 << 2, ///< M680X Hitachi 6309 mode
CS_MODE_M680X_6800 = 1 << 3, ///< M680X Motorola 6800,6802 mode
@ -210,7 +230,7 @@ typedef enum cs_mode {
CS_MODE_M680X_6809 = 1 << 7, ///< M680X Motorola 6809 mode
CS_MODE_M680X_6811 = 1 << 8, ///< M680X Motorola/Freescale/NXP 68HC11 mode
CS_MODE_M680X_CPU12 = 1 << 9, ///< M680X Motorola/Freescale/NXP CPU12
///< used on M68HC12/HCS12
///< used on M68HC12/HCS12
CS_MODE_M680X_HCS08 = 1 << 10, ///< M680X Freescale/NXP HCS08 mode
CS_MODE_BPF_CLASSIC = 0, ///< Classic BPF mode (default)
CS_MODE_BPF_EXTENDED = 1 << 0, ///< Extended BPF mode
@ -299,6 +319,7 @@ typedef enum cs_opt_value {
CS_OPT_SYNTAX_MOTOROLA = 1 << 6, ///< MOS65XX use $ as hex prefix
CS_OPT_SYNTAX_CS_REG_ALIAS = 1 << 7, ///< Prints common register alias which are not defined in LLVM (ARM: r9 = sb etc.)
CS_OPT_SYNTAX_PERCENT = 1 << 8, ///< Prints the % in front of PPC registers.
CS_OPT_SYNTAX_NO_DOLLAR = 1 << 9, ///< Does not print the $ in front of Mips registers.
CS_OPT_DETAIL_REAL = 1 << 1, ///< If enabled, always sets the real instruction detail. Even if the instruction is an alias.
} cs_opt_value;
@ -401,7 +422,7 @@ typedef struct cs_opt_skipdata {
#define MAX_IMPL_W_REGS 47
#define MAX_IMPL_R_REGS 20
#define MAX_NUM_GROUPS 8
#define MAX_NUM_GROUPS 16
/// NOTE: All information in cs_detail is only available when CS_OPT_DETAIL = CS_OPT_ON
/// Initialized as memset(., 0, offsetof(cs_detail, ARCH)+sizeof(cs_ARCH))

3
include/capstone/cs_operand.h
View File

@ -25,8 +25,7 @@ typedef enum cs_op_type {
CS_OP_RESERVED_15 = 15,
CS_OP_SPECIAL = 0x10, ///< Special operands from archs
CS_OP_BOUND = 0x40, ///< Operand is associated with a previous operand. Used by AArch64 for SME operands.
CS_OP_MEM =
0x80, ///< Memory operand. Can be ORed with another operand type.
CS_OP_MEM = 0x80, ///< Memory operand. Can be ORed with another operand type.
CS_OP_MEM_REG = CS_OP_MEM | CS_OP_REG, ///< Memory referencing register operand.
CS_OP_MEM_IMM = CS_OP_MEM | CS_OP_IMM, ///< Memory referencing immediate operand.

2402
include/capstone/mips.h
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File diff suppressed because it is too large Load Diff

4
suite/MC/Mips/micromips-alu-instructions-EB.s.cs
View File

@ -7,8 +7,8 @@
0x00,0xe6,0x49,0x50 = addu $t1, $a2, $a3
0x00,0xe6,0x49,0x90 = sub $t1, $a2, $a3
0x00,0xa3,0x21,0xd0 = subu $a0, $v1, $a1
0x00,0xe0,0x31,0x90 = sub $a2, $zero, $a3
0x00,0xe0,0x31,0xd0 = subu $a2, $zero, $a3
0x00,0xe0,0x31,0x90 = neg $a2, $a3
0x00,0xe0,0x31,0xd0 = negu $a2, $a3
0x00,0x08,0x39,0x50 = addu $a3, $t0, $zero
0x00,0xa3,0x1b,0x50 = slt $v1, $v1, $a1
0x90,0x63,0x00,0x67 = slti $v1, $v1, 103

4
suite/MC/Mips/micromips-alu-instructions.s.cs
View File

@ -7,8 +7,8 @@
0xe6,0x00,0x50,0x49 = addu $t1, $a2, $a3
0xe6,0x00,0x90,0x49 = sub $t1, $a2, $a3
0xa3,0x00,0xd0,0x21 = subu $a0, $v1, $a1
0xe0,0x00,0x90,0x31 = sub $a2, $zero, $a3
0xe0,0x00,0xd0,0x31 = subu $a2, $zero, $a3
0xe0,0x00,0x90,0x31 = neg $a2, $a3
0xe0,0x00,0xd0,0x31 = negu $a2, $a3
0x08,0x00,0x50,0x39 = addu $a3, $t0, $zero
0xa3,0x00,0x50,0x1b = slt $v1, $v1, $a1
0x63,0x90,0x67,0x00 = slti $v1, $v1, 103

20
suite/MC/Mips/micromips-branch-instructions-EB.s.cs
View File

@ -1,11 +1,11 @@
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None
0x94,0x00,0x02,0x9a = b 1332
0x94,0xc9,0x02,0x9a = beq $t1, $a2, 1332
0x40,0x46,0x02,0x9a = bgez $a2, 1332
0x40,0x66,0x02,0x9a = bgezal $a2, 1332
0x40,0x26,0x02,0x9a = bltzal $a2, 1332
0x40,0xc6,0x02,0x9a = bgtz $a2, 1332
0x40,0x86,0x02,0x9a = blez $a2, 1332
0xb4,0xc9,0x02,0x9a = bne $t1, $a2, 1332
// 0x40,0x60,0x02,0x9a = bal 1332
0x40,0x06,0x02,0x9a = bltz $a2, 1332
0x94,0x00,0x02,0x9a = b 0x538
0x94,0xc9,0x02,0x9a = beq $t1, $a2, 0x538
0x40,0x46,0x02,0x9a = bgez $a2, 0x538
0x40,0x66,0x02,0x9a = bgezal $a2, 0x538
0x40,0x26,0x02,0x9a = bltzal $a2, 0x538
0x40,0xc6,0x02,0x9a = bgtz $a2, 0x538
0x40,0x86,0x02,0x9a = blez $a2, 0x538
0xb4,0xc9,0x02,0x9a = bne $t1, $a2, 0x538
// 0x40,0x60,0x02,0x9a = bal 0x538
0x40,0x06,0x02,0x9a = bltz $a2, 0x538

20
suite/MC/Mips/micromips-branch-instructions.s.cs
View File

@ -1,11 +1,11 @@
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None
0x00,0x94,0x9a,0x02 = b 1332
0xc9,0x94,0x9a,0x02 = beq $t1, $a2, 1332
0x46,0x40,0x9a,0x02 = bgez $a2, 1332
0x66,0x40,0x9a,0x02 = bgezal $a2, 1332
0x26,0x40,0x9a,0x02 = bltzal $a2, 1332
0xc6,0x40,0x9a,0x02 = bgtz $a2, 1332
0x86,0x40,0x9a,0x02 = blez $a2, 1332
0xc9,0xb4,0x9a,0x02 = bne $t1, $a2, 1332
// 0x60,0x40,0x9a,0x02 = bal 1332
0x06,0x40,0x9a,0x02 = bltz $a2, 1332
0x00,0x94,0x9a,0x02 = b 0x538
0xc9,0x94,0x9a,0x02 = beq $t1, $a2, 0x538
0x46,0x40,0x9a,0x02 = bgez $a2, 0x538
0x66,0x40,0x9a,0x02 = bgezal $a2, 0x538
0x26,0x40,0x9a,0x02 = bltzal $a2, 0x538
0xc6,0x40,0x9a,0x02 = bgtz $a2, 0x538
0x86,0x40,0x9a,0x02 = blez $a2, 0x538
0xc9,0xb4,0x9a,0x02 = bne $t1, $a2, 0x538
// 0x60,0x40,0x9a,0x02 = bal 0x538
0x06,0x40,0x9a,0x02 = bltz $a2, 0x538

43
suite/MC/Mips/micromips-expansions.s.cs
View File

@ -1,20 +1,25 @@
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None
0xa0,0x50,0x7b,0x00 = ori $a1, $zero, 123
0xc0,0x30,0xd7,0xf6 = addiu $a2, $zero, -2345
0xa7,0x41,0x01,0x00 = lui $a3, 1
0xe7,0x50,0x02,0x00 = ori $a3, $a3, 2
0x80,0x30,0x14,0x00 = addiu $a0, $zero, 20
0xa7,0x41,0x01,0x00 = lui $a3, 1
0xe7,0x50,0x02,0x00 = ori $a3, $a3, 2
0x85,0x30,0x14,0x00 = addiu $a0, $a1, 20
0xa7,0x41,0x01,0x00 = lui $a3, 1
0xe7,0x50,0x02,0x00 = ori $a3, $a3, 2
0x07,0x01,0x50,0x39 = addu $a3, $a3, $t0
0x8a,0x00,0x50,0x51 = addu $t2, $t2, $a0
0x21,0x01,0x50,0x09 = addu $at, $at, $t1
0xaa,0x41,0x0a,0x00 = lui $t2, 10
0x8a,0x00,0x50,0x51 = addu $t2, $t2, $a0
0x4a,0xfd,0x7b,0x00 = lw $t2, 123($t2)
0xa1,0x41,0x02,0x00 = lui $at, 2
0x21,0x01,0x50,0x09 = addu $at, $at, $t1
// 0x41,0xf9,0x40,0xe2 = sw $t2, 57920($at)
0xa0,0x30,0x7b,0x00 == addiu $5, $zero, 123 # encoding: [0xa0,0x30,0x7b,0x00]
0xc0,0x30,0xd7,0xf6 == addiu $6, $zero, -2345 # encoding: [0xc0,0x30,0xd7,0xf6]
0xa7,0x41,0x01,0x00 == lui $7, 1 # encoding: [0xa7,0x41,0x01,0x00]
0xe7,0x50,0x02,0x00 == ori $7, $7, 2 # encoding: [0xe7,0x50,0x02,0x00]
0x80,0x30,0x14,0x00 == addiu $4, $zero, 20 # encoding: [0x80,0x30,0x14,0x00]
0xa7,0x41,0x01,0x00 == lui $7, 1 # encoding: [0xa7,0x41,0x01,0x00]
0xe7,0x50,0x02,0x00 == ori $7, $7, 2 # encoding: [0xe7,0x50,0x02,0x00]
0x85,0x30,0x14,0x00 == addiu $4, $5, 20 # encoding: [0x85,0x30,0x14,0x00]
0xa7,0x41,0x01,0x00 == lui $7, 1 # encoding: [0xa7,0x41,0x01,0x00]
0xe7,0x50,0x02,0x00 == ori $7, $7, 2 # encoding: [0xe7,0x50,0x02,0x00]
0x07,0x01,0x50,0x39 == addu $7, $7, $8 # encoding: [0x07,0x01,0x50,0x39]
0xaa == lui $10, %hi(symbol) # encoding: [0xaa'A',0x41'A',0x00,0x00]
0x8a,0x00,0x50,0x51 == addu $10, $10, $4 # encoding: [0x8a,0x00,0x50,0x51]
0x4a == lw $10, %lo(symbol)($10) # encoding: [0x4a'A',0xfd'A',0x00,0x00]
0xa1 == lui $1, %hi(symbol) # encoding: [0xa1'A',0x41'A',0x00,0x00]
0x21,0x01,0x50,0x09 == addu $1, $1, $9 # encoding: [0x21,0x01,0x50,0x09]
0x41 == sw $10, %lo(symbol)($1) # encoding: [0x41'A',0xf9'A',0x00,0x00]
0xaa,0x41,0x0a,0x00 == lui $10, 10 # encoding: [0xaa,0x41,0x0a,0x00]
0x8a,0x00,0x50,0x51 == addu $10, $10, $4 # encoding: [0x8a,0x00,0x50,0x51]
0x4a,0xfd,0x7b,0x00 == lw $10, 123($10) # encoding: [0x4a,0xfd,0x7b,0x00]
0xa1,0x41,0x02,0x00 == lui $1, 2 # encoding: [0xa1,0x41,0x02,0x00]
0x21,0x01,0x50,0x09 == addu $1, $1, $9 # encoding: [0x21,0x01,0x50,0x09]
0x41,0xf9,0x40,0xe2 == sw $10, -7616($1) # encoding: [0x41,0xf9,0x40,0xe2]

118
suite/MC/Mips/mips-alu-instructions.s.cs
View File

@ -1,53 +1,67 @@
# CS_ARCH_MIPS, CS_MODE_MIPS32, None
0x24,0x48,0xc7,0x00 = and $t1, $a2, $a3
0x67,0x45,0xc9,0x30 = andi $t1, $a2, 17767
0x67,0x45,0xc9,0x30 = andi $t1, $a2, 17767
0x67,0x45,0x29,0x31 = andi $t1, $t1, 17767
0x21,0x30,0xe6,0x70 = clo $a2, $a3
0x20,0x30,0xe6,0x70 = clz $a2, $a3
0x84,0x61,0x33,0x7d = ins $s3, $t1, 6, 7
0x27,0x48,0xc7,0x00 = nor $t1, $a2, $a3
0x25,0x18,0x65,0x00 = or $v1, $v1, $a1
0x67,0x45,0xa4,0x34 = ori $a0, $a1, 17767
0x67,0x45,0xc9,0x34 = ori $t1, $a2, 17767
0x80,0x00,0x6b,0x35 = ori $t3, $t3, 128
0xc2,0x49,0x26,0x00 = rotr $t1, $a2, 7
0x46,0x48,0xe6,0x00 = rotrv $t1, $a2, $a3
0xc0,0x21,0x03,0x00 = sll $a0, $v1, 7
0x04,0x10,0xa3,0x00 = sllv $v0, $v1, $a1
0x2a,0x18,0x65,0x00 = slt $v1, $v1, $a1
0x67,0x00,0x63,0x28 = slti $v1, $v1, 103
0x67,0x00,0x63,0x28 = slti $v1, $v1, 103
0x67,0x00,0x63,0x2c = sltiu $v1, $v1, 103
0x2b,0x18,0x65,0x00 = sltu $v1, $v1, $a1
0xc3,0x21,0x03,0x00 = sra $a0, $v1, 7
0x07,0x10,0xa3,0x00 = srav $v0, $v1, $a1
0xc2,0x21,0x03,0x00 = srl $a0, $v1, 7
0x06,0x10,0xa3,0x00 = srlv $v0, $v1, $a1
0x26,0x18,0x65,0x00 = xor $v1, $v1, $a1
0x67,0x45,0xc9,0x38 = xori $t1, $a2, 17767
0x67,0x45,0xc9,0x38 = xori $t1, $a2, 17767
0x0c,0x00,0x6b,0x39 = xori $t3, $t3, 12
0xa0,0x30,0x07,0x7c = wsbh $a2, $a3
0x27,0x38,0x00,0x01 = not $a3, $t0
0x20,0x48,0xc7,0x00 = add $t1, $a2, $a3
0x67,0x45,0xc9,0x20 = addi $t1, $a2, 17767
0x67,0xc5,0xc9,0x24 = addiu $t1, $a2, -15001
0x67,0x45,0xc9,0x20 = addi $t1, $a2, 17767
0x67,0x45,0x29,0x21 = addi $t1, $t1, 17767
0x67,0xc5,0xc9,0x24 = addiu $t1, $a2, -15001
0x28,0x00,0x6b,0x25 = addiu $t3, $t3, 40
0x21,0x48,0xc7,0x00 = addu $t1, $a2, $a3
0x00,0x00,0xc7,0x70 = madd $a2, $a3
0x01,0x00,0xc7,0x70 = maddu $a2, $a3
0x04,0x00,0xc7,0x70 = msub $a2, $a3
0x05,0x00,0xc7,0x70 = msubu $a2, $a3
0x18,0x00,0x65,0x00 = mult $v1, $a1
0x19,0x00,0x65,0x00 = multu $v1, $a1
0x22,0x48,0xc7,0x00 = sub $t1, $a2, $a3
0xc8,0xff,0xbd,0x23 = addi $sp, $sp, -56
0x23,0x20,0x65,0x00 = subu $a0, $v1, $a1
0xd8,0xff,0xbd,0x27 = addiu $sp, $sp, -40
0x22,0x30,0x07,0x00 = neg $a2, $a3
0x23,0x30,0x07,0x00 = negu $a2, $a3
0x21,0x38,0x00,0x01 = move $a3, $t0
0x24,0x48,0xc7,0x00 == and $9, $6, $7 # encoding: [0x24,0x48,0xc7,0x00]
0x67,0x45,0xc9,0x30 == andi $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x30]
0x67,0x45,0xc9,0x30 == andi $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x30]
0x67,0x45,0x29,0x31 == andi $9, $9, 17767 # encoding: [0x67,0x45,0x29,0x31]
0x21,0x30,0xe6,0x70 == clo $6, $7 # encoding: [0x21,0x30,0xe6,0x70]
0x20,0x30,0xe6,0x70 == clz $6, $7 # encoding: [0x20,0x30,0xe6,0x70]
0x84,0x61,0x33,0x7d == ins $19, $9, 6, 7 # encoding: [0x84,0x61,0x33,0x7d]
0x27,0x48,0xc7,0x00 == nor $9, $6, $7 # encoding: [0x27,0x48,0xc7,0x00]
0x25,0x18,0x65,0x00 == or $3, $3, $5 # encoding: [0x25,0x18,0x65,0x00]
0x67,0x45,0xa4,0x34 == ori $4, $5, 17767 # encoding: [0x67,0x45,0xa4,0x34]
0x67,0x45,0xc9,0x34 == ori $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x34]
0x80,0x00,0x6b,0x35 == ori $11, $11, 128 # encoding: [0x80,0x00,0x6b,0x35]
0xc2,0x49,0x26,0x00 == rotr $9, $6, 7 # encoding: [0xc2,0x49,0x26,0x00]
0x46,0x48,0xe6,0x00 == rotrv $9, $6, $7 # encoding: [0x46,0x48,0xe6,0x00]
0xc0,0x21,0x03,0x00 == sll $4, $3, 7 # encoding: [0xc0,0x21,0x03,0x00]
0x04,0x10,0xa3,0x00 == sllv $2, $3, $5 # encoding: [0x04,0x10,0xa3,0x00]
0x2a,0x18,0x65,0x00 == slt $3, $3, $5 # encoding: [0x2a,0x18,0x65,0x00]
0x67,0x00,0x63,0x28 == slti $3, $3, 103 # encoding: [0x67,0x00,0x63,0x28]
0x67,0x00,0x63,0x28 == slti $3, $3, 103 # encoding: [0x67,0x00,0x63,0x28]
0x67,0x00,0x63,0x2c == sltiu $3, $3, 103 # encoding: [0x67,0x00,0x63,0x2c]
0x2b,0x18,0x65,0x00 == sltu $3, $3, $5 # encoding: [0x2b,0x18,0x65,0x00]
0xc3,0x21,0x03,0x00 == sra $4, $3, 7 # encoding: [0xc3,0x21,0x03,0x00]
0x07,0x10,0xa3,0x00 == srav $2, $3, $5 # encoding: [0x07,0x10,0xa3,0x00]
0xc2,0x21,0x03,0x00 == srl $4, $3, 7 # encoding: [0xc2,0x21,0x03,0x00]
0x06,0x10,0xa3,0x00 == srlv $2, $3, $5 # encoding: [0x06,0x10,0xa3,0x00]
0x26,0x18,0x65,0x00 == xor $3, $3, $5 # encoding: [0x26,0x18,0x65,0x00]
0x67,0x45,0xc9,0x38 == xori $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x38]
0x67,0x45,0xc9,0x38 == xori $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x38]
0x0c,0x00,0x6b,0x39 == xori $11, $11, 12 # encoding: [0x0c,0x00,0x6b,0x39]
0xa0,0x30,0x07,0x7c == wsbh $6, $7 # encoding: [0xa0,0x30,0x07,0x7c]
0x27,0x38,0x00,0x01 == not $7, $8 # encoding: [0x27,0x38,0x00,0x01]
0x20,0x48,0xc7,0x00 == add $9, $6, $7 # encoding: [0x20,0x48,0xc7,0x00]
0x67,0x45,0xc9,0x20 == addi $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x20]
0x67,0xc5,0xc9,0x24 == addiu $9, $6, -15001 # encoding: [0x67,0xc5,0xc9,0x24]
0x67,0x45,0xc9,0x20 == addi $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x20]
0x67,0x45,0x29,0x21 == addi $9, $9, 17767 # encoding: [0x67,0x45,0x29,0x21]
0x67,0xc5,0xc9,0x24 == addiu $9, $6, -15001 # encoding: [0x67,0xc5,0xc9,0x24]
0x28,0x00,0x6b,0x25 == addiu $11, $11, 40 # encoding: [0x28,0x00,0x6b,0x25]
0x21,0x48,0xc7,0x00 == addu $9, $6, $7 # encoding: [0x21,0x48,0xc7,0x00]
0x00,0x00,0xc7,0x70 == madd $6, $7 # encoding: [0x00,0x00,0xc7,0x70]
0x01,0x00,0xc7,0x70 == maddu $6, $7 # encoding: [0x01,0x00,0xc7,0x70]
0x04,0x00,0xc7,0x70 == msub $6, $7 # encoding: [0x04,0x00,0xc7,0x70]
0x05,0x00,0xc7,0x70 == msubu $6, $7 # encoding: [0x05,0x00,0xc7,0x70]
0x18,0x00,0x65,0x00 == mult $3, $5 # encoding: [0x18,0x00,0x65,0x00]
0x19,0x00,0x65,0x00 == multu $3, $5 # encoding: [0x19,0x00,0x65,0x00]
0x22,0x48,0xc7,0x00 == sub $9, $6, $7 # encoding: [0x22,0x48,0xc7,0x00]
0xc8,0xff,0xbd,0x23 == addi $sp, $sp, -56 # encoding: [0xc8,0xff,0xbd,0x23]
0x23,0x20,0x65,0x00 == subu $4, $3, $5 # encoding: [0x23,0x20,0x65,0x00]
0xd8,0xff,0xbd,0x27 == addiu $sp, $sp, -40 # encoding: [0xd8,0xff,0xbd,0x27]
0x22,0x30,0x07,0x00 == neg $6, $7 # encoding: [0x22,0x30,0x07,0x00]
0x23,0x30,0x07,0x00 == negu $6, $7 # encoding: [0x23,0x30,0x07,0x00]
0x25,0x38,0x00,0x01 == move $7, $8 # encoding: [0x25,0x38,0x00,0x01]
0x3b,0xe8,0x05,0x7c == .set pop # encoding: [0x3b,0xe8,0x05,0x7c]
0x20,0x48,0x23,0x01 == add $9, $9, $3 # encoding: [0x20,0x48,0x23,0x01]
0x21,0x48,0x23,0x01 == addu $9, $9, $3 # encoding: [0x21,0x48,0x23,0x01]
0x0a,0x00,0x29,0x21 == addi $9, $9, 10 # encoding: [0x0a,0x00,0x29,0x21]
0x0a,0x00,0x29,0x25 == addiu $9, $9, 10 # encoding: [0x0a,0x00,0x29,0x25]
0x24,0x28,0xa6,0x00 == and $5, $5, $6 # encoding: [0x24,0x28,0xa6,0x00]
0x02,0x48,0x23,0x71 == mul $9, $9, $3 # encoding: [0x02,0x48,0x23,0x71]
0x25,0x10,0x44,0x00 == or $2, $2, $4 # encoding: [0x25,0x10,0x44,0x00]
0x22,0x48,0x23,0x01 == sub $9, $9, $3 # encoding: [0x22,0x48,0x23,0x01]
0x23,0x48,0x23,0x01 == subu $9, $9, $3 # encoding: [0x23,0x48,0x23,0x01]
0xf6,0xff,0x29,0x21 == addi $9, $9, -10 # encoding: [0xf6,0xff,0x29,0x21]
0xf6,0xff,0x29,0x25 == addiu $9, $9, -10 # encoding: [0xf6,0xff,0x29,0x25]
0x26,0x48,0x2a,0x01 == xor $9, $9, $10 # encoding: [0x26,0x48,0x2a,0x01]

2
suite/MC/Mips/mips-control-instructions-64.s.cs
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@ -1,4 +1,4 @@
# CS_ARCH_MIPS, CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS64R2+CS_MODE_BIG_ENDIAN, None
0x00,0x00,0x00,0x0d = break
// 0x00,0x07,0x00,0x0d = break 7, 0
0x00,0x07,0x01,0x4d = break 7, 5

2
suite/MC/Mips/mips-control-instructions.s.cs
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@ -1,4 +1,4 @@
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS32R2+CS_MODE_BIG_ENDIAN, None
0x00,0x00,0x00,0x0d = break
// 0x00,0x07,0x00,0x0d = break 7, 0
0x00,0x07,0x01,0x4d = break 7, 5

32
suite/MC/Mips/mips-coprocessor-encodings.s.cs
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@ -1,17 +1,17 @@
# CS_ARCH_MIPS, CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN, None
0x40,0xac,0x80,0x02 = dmtc0 $t4, $s0, 2
0x40,0xac,0x80,0x00 = dmtc0 $t4, $s0, 0
0x40,0x8c,0x80,0x02 = mtc0 $t4, $s0, 2
0x40,0x8c,0x80,0x00 = mtc0 $t4, $s0, 0
0x40,0x2c,0x80,0x02 = dmfc0 $t4, $s0, 2
0x40,0x2c,0x80,0x00 = dmfc0 $t4, $s0, 0
0x40,0x0c,0x80,0x02 = mfc0 $t4, $s0, 2
0x40,0x0c,0x80,0x00 = mfc0 $t4, $s0, 0
0x48,0xac,0x80,0x02 = dmtc2 $t4, $s0, 2
0x48,0xac,0x80,0x00 = dmtc2 $t4, $s0, 0
0x48,0x8c,0x80,0x02 = mtc2 $t4, $s0, 2
0x48,0x8c,0x80,0x00 = mtc2 $t4, $s0, 0
0x48,0x2c,0x80,0x02 = dmfc2 $t4, $s0, 2
0x48,0x2c,0x80,0x00 = dmfc2 $t4, $s0, 0
0x48,0x0c,0x80,0x02 = mfc2 $t4, $s0, 2
0x48,0x0c,0x80,0x00 = mfc2 $t4, $s0, 0
0x40,0xac,0x80,0x02 = dmtc0 $t4, $16, 2
0x40,0xac,0x80,0x00 = dmtc0 $t4, $16, 0
0x40,0x8c,0x80,0x02 = mtc0 $t4, $16, 2
0x40,0x8c,0x80,0x00 = mtc0 $t4, $16, 0
0x40,0x2c,0x80,0x02 = dmfc0 $t4, $16, 2
0x40,0x2c,0x80,0x00 = dmfc0 $t4, $16, 0
0x40,0x0c,0x80,0x02 = mfc0 $t4, $16, 2
0x40,0x0c,0x80,0x00 = mfc0 $t4, $16, 0
0x48,0xac,0x80,0x02 = dmtc2 $t4, $16, 2
0x48,0xac,0x80,0x00 = dmtc2 $t4, $16, 0
0x48,0x8c,0x80,0x02 = mtc2 $t4, $16, 2
0x48,0x8c,0x80,0x00 = mtc2 $t4, $16, 0
0x48,0x2c,0x80,0x02 = dmfc2 $t4, $16, 2
0x48,0x2c,0x80,0x00 = dmfc2 $t4, $16, 0
0x48,0x0c,0x80,0x02 = mfc2 $t4, $16, 2
0x48,0x0c,0x80,0x00 = mfc2 $t4, $16, 0

185
suite/MC/Mips/mips-fpu-instructions.s.cs
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@ -1,93 +1,94 @@
# CS_ARCH_MIPS, CS_MODE_MIPS32, None
0x05,0x73,0x20,0x46 = abs.d $f12, $f14
0x85,0x39,0x00,0x46 = abs.s $f6, $f7
0x00,0x62,0x2e,0x46 = add.d $f8, $f12, $f14
0x40,0x32,0x07,0x46 = add.s $f9, $f6, $f7
0x0f,0x73,0x20,0x46 = floor.w.d $f12, $f14
0x8f,0x39,0x00,0x46 = floor.w.s $f6, $f7
0x0e,0x73,0x20,0x46 = ceil.w.d $f12, $f14
0x8e,0x39,0x00,0x46 = ceil.w.s $f6, $f7
0x02,0x62,0x2e,0x46 = mul.d $f8, $f12, $f14
0x42,0x32,0x07,0x46 = mul.s $f9, $f6, $f7
0x07,0x73,0x20,0x46 = neg.d $f12, $f14
0x87,0x39,0x00,0x46 = neg.s $f6, $f7
0x0c,0x73,0x20,0x46 = round.w.d $f12, $f14
0x8c,0x39,0x00,0x46 = round.w.s $f6, $f7
0x04,0x73,0x20,0x46 = sqrt.d $f12, $f14
0x84,0x39,0x00,0x46 = sqrt.s $f6, $f7
0x01,0x62,0x2e,0x46 = sub.d $f8, $f12, $f14
0x41,0x32,0x07,0x46 = sub.s $f9, $f6, $f7
0x0d,0x73,0x20,0x46 = trunc.w.d $f12, $f14
0x8d,0x39,0x00,0x46 = trunc.w.s $f6, $f7
0x32,0x60,0x2e,0x46 = c.eq.d $f12, $f14
0x32,0x30,0x07,0x46 = c.eq.s $f6, $f7
0x30,0x60,0x2e,0x46 = c.f.d $f12, $f14
0x30,0x30,0x07,0x46 = c.f.s $f6, $f7
0x3e,0x60,0x2e,0x46 = c.le.d $f12, $f14
0x3e,0x30,0x07,0x46 = c.le.s $f6, $f7
0x3c,0x60,0x2e,0x46 = c.lt.d $f12, $f14
0x3c,0x30,0x07,0x46 = c.lt.s $f6, $f7
0x3d,0x60,0x2e,0x46 = c.nge.d $f12, $f14
0x3d,0x30,0x07,0x46 = c.nge.s $f6, $f7
0x3b,0x60,0x2e,0x46 = c.ngl.d $f12, $f14
0x3b,0x30,0x07,0x46 = c.ngl.s $f6, $f7
0x39,0x60,0x2e,0x46 = c.ngle.d $f12, $f14
0x39,0x30,0x07,0x46 = c.ngle.s $f6, $f7
0x3f,0x60,0x2e,0x46 = c.ngt.d $f12, $f14
0x3f,0x30,0x07,0x46 = c.ngt.s $f6, $f7
0x36,0x60,0x2e,0x46 = c.ole.d $f12, $f14
0x36,0x30,0x07,0x46 = c.ole.s $f6, $f7
0x34,0x60,0x2e,0x46 = c.olt.d $f12, $f14
0x34,0x30,0x07,0x46 = c.olt.s $f6, $f7
0x3a,0x60,0x2e,0x46 = c.seq.d $f12, $f14
0x3a,0x30,0x07,0x46 = c.seq.s $f6, $f7
0x38,0x60,0x2e,0x46 = c.sf.d $f12, $f14
0x38,0x30,0x07,0x46 = c.sf.s $f6, $f7
0x33,0x60,0x2e,0x46 = c.ueq.d $f12, $f14
0x33,0xe0,0x12,0x46 = c.ueq.s $f28, $f18
0x37,0x60,0x2e,0x46 = c.ule.d $f12, $f14
0x37,0x30,0x07,0x46 = c.ule.s $f6, $f7
0x35,0x60,0x2e,0x46 = c.ult.d $f12, $f14
0x35,0x30,0x07,0x46 = c.ult.s $f6, $f7
0x31,0x60,0x2e,0x46 = c.un.d $f12, $f14
0x31,0x30,0x07,0x46 = c.un.s $f6, $f7
0xa1,0x39,0x00,0x46 = cvt.d.s $f6, $f7
0x21,0x73,0x80,0x46 = cvt.d.w $f12, $f14
0x20,0x73,0x20,0x46 = cvt.s.d $f12, $f14
0xa0,0x39,0x80,0x46 = cvt.s.w $f6, $f7
0x24,0x73,0x20,0x46 = cvt.w.d $f12, $f14
0xa4,0x39,0x00,0x46 = cvt.w.s $f6, $f7
0x00,0x00,0x46,0x44 = cfc1 $a2, $0
0x00,0xf8,0xca,0x44 = ctc1 $t2, $31
0x00,0x38,0x06,0x44 = mfc1 $a2, $f7
0x10,0x28,0x00,0x00 = mfhi $a1
0x12,0x28,0x00,0x00 = mflo $a1
0x86,0x41,0x20,0x46 = mov.d $f6, $f8
0x86,0x39,0x00,0x46 = mov.s $f6, $f7
0x00,0x38,0x86,0x44 = mtc1 $a2, $f7
0x11,0x00,0xe0,0x00 = mthi $a3
0x13,0x00,0xe0,0x00 = mtlo $a3
0xc6,0x23,0xe9,0xe4 = swc1 $f9, 9158($a3)
0x00,0x38,0x06,0x40 = mfc0 $a2, $a3, 0
0x00,0x40,0x89,0x40 = mtc0 $t1, $t0, 0
0x00,0x38,0x05,0x48 = mfc2 $a1, $a3, 0
0x00,0x20,0x89,0x48 = mtc2 $t1, $a0, 0
0x02,0x38,0x06,0x40 = mfc0 $a2, $a3, 2
0x03,0x40,0x89,0x40 = mtc0 $t1, $t0, 3
0x04,0x38,0x05,0x48 = mfc2 $a1, $a3, 4
0x05,0x20,0x89,0x48 = mtc2 $t1, $a0, 5
0x01,0x10,0x20,0x00 = movf $v0, $at, $fcc0
0x01,0x10,0x21,0x00 = movt $v0, $at, $fcc0
0x01,0x20,0xb1,0x00 = movt $a0, $a1, $fcc4
0x11,0x31,0x28,0x46 = movf.d $f4, $f6, $fcc2
0x11,0x31,0x14,0x46 = movf.s $f4, $f6, $fcc5
0x05,0x00,0xa6,0x4c = luxc1 $f0, $a2($a1)
0x0d,0x20,0xb8,0x4c = suxc1 $f4, $t8($a1)
0x00,0x05,0xcc,0x4d = lwxc1 $f20, $t4($t6)
0x08,0xd0,0xd2,0x4e = swxc1 $f26, $s2($s6)
0x00,0x20,0x71,0x44 = mfhc1 $s1, $f4
0x00,0x30,0xf1,0x44 = mthc1 $s1, $f6
0x10,0x00,0xa4,0xeb = swc2 $4, 16($sp)
0x10,0x00,0xa4,0xfb = sdc2 $4, 16($sp)
0x0c,0x00,0xeb,0xcb = lwc2 $11, 12($ra)
0x0c,0x00,0xeb,0xdb = ldc2 $11, 12($ra)
0x05,0x73,0x20,0x46 == abs.d $f12, $f14 # encoding: [0x05,0x73,0x20,0x46]
0x85,0x39,0x00,0x46 == abs.s $f6, $f7 # encoding: [0x85,0x39,0x00,0x46]
0x00,0x62,0x2e,0x46 == add.d $f8, $f12, $f14 # encoding: [0x00,0x62,0x2e,0x46]
0x40,0x32,0x07,0x46 == add.s $f9, $f6, $f7 # encoding: [0x40,0x32,0x07,0x46]
0x0f,0x73,0x20,0x46 == floor.w.d $f12, $f14 # encoding: [0x0f,0x73,0x20,0x46]
0x8f,0x39,0x00,0x46 == floor.w.s $f6, $f7 # encoding: [0x8f,0x39,0x00,0x46]
0x0e,0x73,0x20,0x46 == ceil.w.d $f12, $f14 # encoding: [0x0e,0x73,0x20,0x46]
0x8e,0x39,0x00,0x46 == ceil.w.s $f6, $f7 # encoding: [0x8e,0x39,0x00,0x46]
0x02,0x62,0x2e,0x46 == mul.d $f8, $f12, $f14 # encoding: [0x02,0x62,0x2e,0x46]
0x42,0x32,0x07,0x46 == mul.s $f9, $f6, $f7 # encoding: [0x42,0x32,0x07,0x46]
0x07,0x73,0x20,0x46 == neg.d $f12, $f14 # encoding: [0x07,0x73,0x20,0x46]
0x87,0x39,0x00,0x46 == neg.s $f6, $f7 # encoding: [0x87,0x39,0x00,0x46]
0x0c,0x73,0x20,0x46 == round.w.d $f12, $f14 # encoding: [0x0c,0x73,0x20,0x46]
0x8c,0x39,0x00,0x46 == round.w.s $f6, $f7 # encoding: [0x8c,0x39,0x00,0x46]
0x04,0x73,0x20,0x46 == sqrt.d $f12, $f14 # encoding: [0x04,0x73,0x20,0x46]
0x84,0x39,0x00,0x46 == sqrt.s $f6, $f7 # encoding: [0x84,0x39,0x00,0x46]
0x01,0x62,0x2e,0x46 == sub.d $f8, $f12, $f14 # encoding: [0x01,0x62,0x2e,0x46]
0x41,0x32,0x07,0x46 == sub.s $f9, $f6, $f7 # encoding: [0x41,0x32,0x07,0x46]
0x0d,0x73,0x20,0x46 == trunc.w.d $f12, $f14 # encoding: [0x0d,0x73,0x20,0x46]
0x8d,0x39,0x00,0x46 == trunc.w.s $f6, $f7 # encoding: [0x8d,0x39,0x00,0x46]
0x32,0x60,0x2e,0x46 == c.eq.d $f12, $f14 # encoding: [0x32,0x60,0x2e,0x46]
0x32,0x30,0x07,0x46 == c.eq.s $f6, $f7 # encoding: [0x32,0x30,0x07,0x46]
0x30,0x60,0x2e,0x46 == c.f.d $f12, $f14 # encoding: [0x30,0x60,0x2e,0x46]
0x30,0x30,0x07,0x46 == c.f.s $f6, $f7 # encoding: [0x30,0x30,0x07,0x46]
0x3e,0x60,0x2e,0x46 == c.le.d $f12, $f14 # encoding: [0x3e,0x60,0x2e,0x46]
0x3e,0x30,0x07,0x46 == c.le.s $f6, $f7 # encoding: [0x3e,0x30,0x07,0x46]
0x3c,0x60,0x2e,0x46 == c.lt.d $f12, $f14 # encoding: [0x3c,0x60,0x2e,0x46]
0x3c,0x30,0x07,0x46 == c.lt.s $f6, $f7 # encoding: [0x3c,0x30,0x07,0x46]
0x3d,0x60,0x2e,0x46 == c.nge.d $f12, $f14 # encoding: [0x3d,0x60,0x2e,0x46]
0x3d,0x30,0x07,0x46 == c.nge.s $f6, $f7 # encoding: [0x3d,0x30,0x07,0x46]
0x3b,0x60,0x2e,0x46 == c.ngl.d $f12, $f14 # encoding: [0x3b,0x60,0x2e,0x46]
0x3b,0x30,0x07,0x46 == c.ngl.s $f6, $f7 # encoding: [0x3b,0x30,0x07,0x46]
0x39,0x60,0x2e,0x46 == c.ngle.d $f12, $f14 # encoding: [0x39,0x60,0x2e,0x46]
0x39,0x30,0x07,0x46 == c.ngle.s $f6, $f7 # encoding: [0x39,0x30,0x07,0x46]
0x3f,0x60,0x2e,0x46 == c.ngt.d $f12, $f14 # encoding: [0x3f,0x60,0x2e,0x46]
0x3f,0x30,0x07,0x46 == c.ngt.s $f6, $f7 # encoding: [0x3f,0x30,0x07,0x46]
0x36,0x60,0x2e,0x46 == c.ole.d $f12, $f14 # encoding: [0x36,0x60,0x2e,0x46]
0x36,0x30,0x07,0x46 == c.ole.s $f6, $f7 # encoding: [0x36,0x30,0x07,0x46]
0x34,0x60,0x2e,0x46 == c.olt.d $f12, $f14 # encoding: [0x34,0x60,0x2e,0x46]
0x34,0x30,0x07,0x46 == c.olt.s $f6, $f7 # encoding: [0x34,0x30,0x07,0x46]
0x3a,0x60,0x2e,0x46 == c.seq.d $f12, $f14 # encoding: [0x3a,0x60,0x2e,0x46]
0x3a,0x30,0x07,0x46 == c.seq.s $f6, $f7 # encoding: [0x3a,0x30,0x07,0x46]
0x38,0x60,0x2e,0x46 == c.sf.d $f12, $f14 # encoding: [0x38,0x60,0x2e,0x46]
0x38,0x30,0x07,0x46 == c.sf.s $f6, $f7 # encoding: [0x38,0x30,0x07,0x46]
0x33,0x60,0x2e,0x46 == c.ueq.d $f12, $f14 # encoding: [0x33,0x60,0x2e,0x46]
0x33,0xe0,0x12,0x46 == c.ueq.s $f28, $f18 # encoding: [0x33,0xe0,0x12,0x46]
0x37,0x60,0x2e,0x46 == c.ule.d $f12, $f14 # encoding: [0x37,0x60,0x2e,0x46]
0x37,0x30,0x07,0x46 == c.ule.s $f6, $f7 # encoding: [0x37,0x30,0x07,0x46]
0x35,0x60,0x2e,0x46 == c.ult.d $f12, $f14 # encoding: [0x35,0x60,0x2e,0x46]
0x35,0x30,0x07,0x46 == c.ult.s $f6, $f7 # encoding: [0x35,0x30,0x07,0x46]
0x31,0x60,0x2e,0x46 == c.un.d $f12, $f14 # encoding: [0x31,0x60,0x2e,0x46]
0x31,0x30,0x07,0x46 == c.un.s $f6, $f7 # encoding: [0x31,0x30,0x07,0x46]
0xa1,0x39,0x00,0x46 == cvt.d.s $f6, $f7 # encoding: [0xa1,0x39,0x00,0x46]
0x21,0x73,0x80,0x46 == cvt.d.w $f12, $f14 # encoding: [0x21,0x73,0x80,0x46]
0x20,0x73,0x20,0x46 == cvt.s.d $f12, $f14 # encoding: [0x20,0x73,0x20,0x46]
0xa0,0x39,0x80,0x46 == cvt.s.w $f6, $f7 # encoding: [0xa0,0x39,0x80,0x46]
0x24,0x73,0x20,0x46 == cvt.w.d $f12, $f14 # encoding: [0x24,0x73,0x20,0x46]
0xa4,0x39,0x00,0x46 == cvt.w.s $f6, $f7 # encoding: [0xa4,0x39,0x00,0x46]
0x00,0x00,0x46,0x44 == cfc1 $6, $0 # encoding: [0x00,0x00,0x46,0x44]
0x00,0xf8,0xca,0x44 == ctc1 $10, $31 # encoding: [0x00,0xf8,0xca,0x44]
0x00,0x38,0x06,0x44 == mfc1 $6, $f7 # encoding: [0x00,0x38,0x06,0x44]
0x10,0x28,0x00,0x00 == mfhi $5 # encoding: [0x10,0x28,0x00,0x00]
0x12,0x28,0x00,0x00 == mflo $5 # encoding: [0x12,0x28,0x00,0x00]
0x86,0x41,0x20,0x46 == mov.d $f6, $f8 # encoding: [0x86,0x41,0x20,0x46]
0x86,0x39,0x00,0x46 == mov.s $f6, $f7 # encoding: [0x86,0x39,0x00,0x46]
0x00,0x38,0x86,0x44 == mtc1 $6, $f7 # encoding: [0x00,0x38,0x86,0x44]
0x11,0x00,0xe0,0x00 == mthi $7 # encoding: [0x11,0x00,0xe0,0x00]
0x13,0x00,0xe0,0x00 == mtlo $7 # encoding: [0x13,0x00,0xe0,0x00]
0xc6,0x23,0xe9,0xe4 == swc1 $f9, 9158($7) # encoding: [0xc6,0x23,0xe9,0xe4]
0x00,0x38,0x06,0x40 == mfc0 $6, $7, 0 # encoding: [0x00,0x38,0x06,0x40]
0x00,0x40,0x89,0x40 == mtc0 $9, $8, 0 # encoding: [0x00,0x40,0x89,0x40]
0x00,0x38,0x05,0x48 == mfc2 $5, $7, 0 # encoding: [0x00,0x38,0x05,0x48]
0x00,0x20,0x89,0x48 == mtc2 $9, $4, 0 # encoding: [0x00,0x20,0x89,0x48]
0x02,0x38,0x06,0x40 == mfc0 $6, $7, 2 # encoding: [0x02,0x38,0x06,0x40]
0x03,0x40,0x89,0x40 == mtc0 $9, $8, 3 # encoding: [0x03,0x40,0x89,0x40]
0x04,0x38,0x05,0x48 == mfc2 $5, $7, 4 # encoding: [0x04,0x38,0x05,0x48]
0x05,0x20,0x89,0x48 == mtc2 $9, $4, 5 # encoding: [0x05,0x20,0x89,0x48]
0x01,0x10,0x20,0x00 == movf $2, $1, $fcc0 # encoding: [0x01,0x10,0x20,0x00]
0x01,0x10,0x21,0x00 == movt $2, $1, $fcc0 # encoding: [0x01,0x10,0x21,0x00]
0x01,0x20,0xb1,0x00 == movt $4, $5, $fcc4 # encoding: [0x01,0x20,0xb1,0x00]
0x11,0x31,0x28,0x46 == movf.d $f4, $f6, $fcc2 # encoding: [0x11,0x31,0x28,0x46]
0x11,0x31,0x14,0x46 == movf.s $f4, $f6, $fcc5 # encoding: [0x11,0x31,0x14,0x46]
0x05,0x00,0xa6,0x4c == luxc1 $f0, $6($5) # encoding: [0x05,0x00,0xa6,0x4c]
0x0d,0x20,0xb8,0x4c == suxc1 $f4, $24($5) # encoding: [0x0d,0x20,0xb8,0x4c]
0x00,0x05,0xcc,0x4d == lwxc1 $f20, $12($14) # encoding: [0x00,0x05,0xcc,0x4d]
0x08,0xd0,0xd2,0x4e == swxc1 $f26, $18($22) # encoding: [0x08,0xd0,0xd2,0x4e]
0x00,0x20,0x71,0x44 == mfhc1 $17, $f4 # encoding: [0x00,0x20,0x71,0x44]
0x00,0x30,0xf1,0x44 == mthc1 $17, $f6 # encoding: [0x00,0x30,0xf1,0x44]
0x10,0x00,0xa4,0xeb == swc2 $4, 16($sp) # encoding: [0x10,0x00,0xa4,0xeb]
0x10,0x00,0xa4,0xfb == sdc2 $4, 16($sp) # encoding: [0x10,0x00,0xa4,0xfb]
0x0c,0x00,0xeb,0xcb == lwc2 $11, 12($ra) # encoding: [0x0c,0x00,0xeb,0xcb]
0x0c,0x00,0xeb,0xdb == ldc2 $11, 12($ra) # encoding: [0x0c,0x00,0xeb,0xdb]

33
suite/MC/Mips/mips-memory-instructions.s.cs
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@ -1,17 +1,18 @@
# CS_ARCH_MIPS, CS_MODE_MIPS32, None
0x10,0x00,0xa4,0xa0 = sb $a0, 16($a1)
0x10,0x00,0xa4,0xe0 = sc $a0, 16($a1)
0x10,0x00,0xa4,0xa4 = sh $a0, 16($a1)
0x10,0x00,0xa4,0xac = sw $a0, 16($a1)
0x00,0x00,0xa7,0xac = sw $a3, ($a1)
0x10,0x00,0xa2,0xe4 = swc1 $f2, 16($a1)
0x10,0x00,0xa4,0xa8 = swl $a0, 16($a1)
0x04,0x00,0xa4,0x80 = lb $a0, 4($a1)
0x04,0x00,0xa4,0x8c = lw $a0, 4($a1)
0x04,0x00,0xa4,0x90 = lbu $a0, 4($a1)
0x04,0x00,0xa4,0x84 = lh $a0, 4($a1)
0x04,0x00,0xa4,0x94 = lhu $a0, 4($a1)
0x04,0x00,0xa4,0xc0 = ll $a0, 4($a1)
0x04,0x00,0xa4,0x8c = lw $a0, 4($a1)
0x00,0x00,0xe7,0x8c = lw $a3, ($a3)
0x10,0x00,0xa2,0x8f = lw $v0, 16($sp)
0x10,0x00,0xa4,0xa0 == sb $4, 16($5) # encoding: [0x10,0x00,0xa4,0xa0]
0x10,0x00,0xa4,0xe0 == sc $4, 16($5) # encoding: [0x10,0x00,0xa4,0xe0]
0x10,0x00,0xa4,0xa4 == sh $4, 16($5) # encoding: [0x10,0x00,0xa4,0xa4]
0x10,0x00,0xa4,0xac == sw $4, 16($5) # encoding: [0x10,0x00,0xa4,0xac]
0x00,0x00,0xa7,0xac == sw $7, 0($5) # encoding: [0x00,0x00,0xa7,0xac]
0x10,0x00,0xa2,0xe4 == swc1 $f2, 16($5) # encoding: [0x10,0x00,0xa2,0xe4]
0x10,0x00,0xa4,0xa8 == swl $4, 16($5) # encoding: [0x10,0x00,0xa4,0xa8]
0x04,0x00,0xa4,0x80 == lb $4, 4($5) # encoding: [0x04,0x00,0xa4,0x80]
0x04,0x00,0xa4,0x8c == lw $4, 4($5) # encoding: [0x04,0x00,0xa4,0x8c]
0x04,0x00,0xa4,0x90 == lbu $4, 4($5) # encoding: [0x04,0x00,0xa4,0x90]
0x04,0x00,0xa4,0x84 == lh $4, 4($5) # encoding: [0x04,0x00,0xa4,0x84]
0x04,0x00,0xa4,0x94 == lhu $4, 4($5) # encoding: [0x04,0x00,0xa4,0x94]
0x04,0x00,0xa4,0xc0 == ll $4, 4($5) # encoding: [0x04,0x00,0xa4,0xc0]
0x04,0x00,0xa4,0x8c == lw $4, 4($5) # encoding: [0x04,0x00,0xa4,0x8c]
0x00,0x00,0xe7,0x8c == lw $7, 0($7) # encoding: [0x00,0x00,0xe7,0x8c]
0x10,0x00,0xa2,0x8f == lw $2, 16($sp) # encoding: [0x10,0x00,0xa2,0x8f]

111
suite/MC/Mips/mips64-alu-instructions.s.cs
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@ -1,47 +1,66 @@
# CS_ARCH_MIPS, CS_MODE_MIPS64, None
0x24,0x48,0xc7,0x00 = and $t1, $a2, $a3
0x67,0x45,0xc9,0x30 = andi $t1, $a2, 17767
0x67,0x45,0xc9,0x30 = andi $t1, $a2, 17767
0x21,0x30,0xe6,0x70 = clo $a2, $a3
0x20,0x30,0xe6,0x70 = clz $a2, $a3
0x84,0x61,0x33,0x7d = ins $s3, $t1, 6, 7
0x27,0x48,0xc7,0x00 = nor $t1, $a2, $a3
0x25,0x18,0x65,0x00 = or $v1, $v1, $a1
0x67,0x45,0xa4,0x34 = ori $a0, $a1, 17767
0x67,0x45,0xc9,0x34 = ori $t1, $a2, 17767
0xc2,0x49,0x26,0x00 = rotr $t1, $a2, 7
0x46,0x48,0xe6,0x00 = rotrv $t1, $a2, $a3
0xc0,0x21,0x03,0x00 = sll $a0, $v1, 7
0x04,0x10,0xa3,0x00 = sllv $v0, $v1, $a1
0x2a,0x18,0x65,0x00 = slt $v1, $v1, $a1
0x67,0x00,0x63,0x28 = slti $v1, $v1, 103
0x67,0x00,0x63,0x28 = slti $v1, $v1, 103
0x67,0x00,0x63,0x2c = sltiu $v1, $v1, 103
0x2b,0x18,0x65,0x00 = sltu $v1, $v1, $a1
0xc3,0x21,0x03,0x00 = sra $a0, $v1, 7
0x07,0x10,0xa3,0x00 = srav $v0, $v1, $a1
0xc2,0x21,0x03,0x00 = srl $a0, $v1, 7
0x06,0x10,0xa3,0x00 = srlv $v0, $v1, $a1
0x26,0x18,0x65,0x00 = xor $v1, $v1, $a1
0x67,0x45,0xc9,0x38 = xori $t1, $a2, 17767
0x67,0x45,0xc9,0x38 = xori $t1, $a2, 17767
0xa0,0x30,0x07,0x7c = wsbh $a2, $a3
0x27,0x38,0x00,0x01 = not $a3, $t0
0x2c,0x48,0xc7,0x00 = dadd $t1, $a2, $a3
0x67,0x45,0xc9,0x60 = daddi $t1, $a2, 17767
0x67,0xc5,0xc9,0x64 = daddiu $t1, $a2, -15001
0x67,0x45,0xc9,0x60 = daddi $t1, $a2, 17767
0x67,0x45,0x29,0x61 = daddi $t1, $t1, 17767
0x67,0xc5,0xc9,0x64 = daddiu $t1, $a2, -15001
0x67,0xc5,0x29,0x65 = daddiu $t1, $t1, -15001
0x2d,0x48,0xc7,0x00 = daddu $t1, $a2, $a3
0x3a,0x4d,0x26,0x00 = drotr $t1, $a2, 20
// 0x3e,0x4d,0x26,0x00 = drotr32 $t1, $a2, 52
0x00,0x00,0xc7,0x70 = madd $a2, $a3
0x01,0x00,0xc7,0x70 = maddu $a2, $a3
0x04,0x00,0xc7,0x70 = msub $a2, $a3
0x05,0x00,0xc7,0x70 = msubu $a2, $a3
0x18,0x00,0x65,0x00 = mult $v1, $a1
0x19,0x00,0x65,0x00 = multu $v1, $a1
0x2f,0x20,0x65,0x00 = dsubu $a0, $v1, $a1
0x2d,0x38,0x00,0x01 = move $a3, $t0
0x24,0x48,0xc7,0x00 == and $9, $6, $7 # encoding: [0x24,0x48,0xc7,0x00]
0x67,0x45,0xc9,0x30 == andi $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x30]
0x67,0x45,0xc9,0x30 == andi $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x30]
0x21,0x30,0xe6,0x70 == clo $6, $7 # encoding: [0x21,0x30,0xe6,0x70]
0x20,0x30,0xe6,0x70 == clz $6, $7 # encoding: [0x20,0x30,0xe6,0x70]
0x84,0x61,0x33,0x7d == ins $19, $9, 6, 7 # encoding: [0x84,0x61,0x33,0x7d]
0x27,0x48,0xc7,0x00 == nor $9, $6, $7 # encoding: [0x27,0x48,0xc7,0x00]
0x25,0x18,0x65,0x00 == or $3, $3, $5 # encoding: [0x25,0x18,0x65,0x00]
0x67,0x45,0xa4,0x34 == ori $4, $5, 17767 # encoding: [0x67,0x45,0xa4,0x34]
0x67,0x45,0xc9,0x34 == ori $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x34]
0xc2,0x49,0x26,0x00 == rotr $9, $6, 7 # encoding: [0xc2,0x49,0x26,0x00]
0x46,0x48,0xe6,0x00 == rotrv $9, $6, $7 # encoding: [0x46,0x48,0xe6,0x00]
0xc0,0x21,0x03,0x00 == sll $4, $3, 7 # encoding: [0xc0,0x21,0x03,0x00]
0x04,0x10,0xa3,0x00 == sllv $2, $3, $5 # encoding: [0x04,0x10,0xa3,0x00]
0x2a,0x18,0x65,0x00 == slt $3, $3, $5 # encoding: [0x2a,0x18,0x65,0x00]
0x67,0x00,0x63,0x28 == slti $3, $3, 103 # encoding: [0x67,0x00,0x63,0x28]
0x67,0x00,0x63,0x28 == slti $3, $3, 103 # encoding: [0x67,0x00,0x63,0x28]
0x67,0x00,0x63,0x2c == sltiu $3, $3, 103 # encoding: [0x67,0x00,0x63,0x2c]
0x2b,0x18,0x65,0x00 == sltu $3, $3, $5 # encoding: [0x2b,0x18,0x65,0x00]
0xc3,0x21,0x03,0x00 == sra $4, $3, 7 # encoding: [0xc3,0x21,0x03,0x00]
0x07,0x10,0xa3,0x00 == srav $2, $3, $5 # encoding: [0x07,0x10,0xa3,0x00]
0xc2,0x21,0x03,0x00 == srl $4, $3, 7 # encoding: [0xc2,0x21,0x03,0x00]
0x06,0x10,0xa3,0x00 == srlv $2, $3, $5 # encoding: [0x06,0x10,0xa3,0x00]
0x26,0x18,0x65,0x00 == xor $3, $3, $5 # encoding: [0x26,0x18,0x65,0x00]
0x67,0x45,0xc9,0x38 == xori $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x38]
0x67,0x45,0xc9,0x38 == xori $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x38]
0xa0,0x30,0x07,0x7c == wsbh $6, $7 # encoding: [0xa0,0x30,0x07,0x7c]
0x27,0x38,0x00,0x01 == not $7, $8 # encoding: [0x27,0x38,0x00,0x01]
0x2c,0x48,0xc7,0x00 == dadd $9, $6, $7 # encoding: [0x2c,0x48,0xc7,0x00]
0x67,0x45,0xc9,0x60 == daddi $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x60]
0x67,0xc5,0xc9,0x64 == daddiu $9, $6, -15001 # encoding: [0x67,0xc5,0xc9,0x64]
0x67,0x45,0xc9,0x60 == daddi $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x60]
0x67,0x45,0x29,0x61 == daddi $9, $9, 17767 # encoding: [0x67,0x45,0x29,0x61]
0x67,0xc5,0xc9,0x64 == daddiu $9, $6, -15001 # encoding: [0x67,0xc5,0xc9,0x64]
0x67,0xc5,0x29,0x65 == daddiu $9, $9, -15001 # encoding: [0x67,0xc5,0x29,0x65]
0x2d,0x48,0xc7,0x00 == daddu $9, $6, $7 # encoding: [0x2d,0x48,0xc7,0x00]
0x3a,0x4d,0x26,0x00 == drotr $9, $6, 20 # encoding: [0x3a,0x4d,0x26,0x00]
0x3e,0x4d,0x26,0x00 == drotr32 $9, $6, 20 # encoding: [0x3e,0x4d,0x26,0x00]
0x00,0x00,0xc7,0x70 == madd $6, $7 # encoding: [0x00,0x00,0xc7,0x70]
0x01,0x00,0xc7,0x70 == maddu $6, $7 # encoding: [0x01,0x00,0xc7,0x70]
0x04,0x00,0xc7,0x70 == msub $6, $7 # encoding: [0x04,0x00,0xc7,0x70]
0x05,0x00,0xc7,0x70 == msubu $6, $7 # encoding: [0x05,0x00,0xc7,0x70]
0x18,0x00,0x65,0x00 == mult $3, $5 # encoding: [0x18,0x00,0x65,0x00]
0x19,0x00,0x65,0x00 == multu $3, $5 # encoding: [0x19,0x00,0x65,0x00]
0x2e,0x48,0xc7,0x00 == dsub $9, $6, $7 # encoding: [0x2e,0x48,0xc7,0x00]
0x2f,0x20,0x65,0x00 == dsubu $4, $3, $5 # encoding: [0x2f,0x20,0x65,0x00]
0x99,0xba,0xc9,0x64 == daddiu $9, $6, -17767 # encoding: [0x99,0xba,0xc9,0x64]
0x25,0x38,0x00,0x01 == move $7, $8 # encoding: [0x25,0x38,0x00,0x01]
0x3b,0xe8,0x05,0x7c == .set pop # encoding: [0x3b,0xe8,0x05,0x7c]
0x24,0x48,0x23,0x01 == and $9, $9, $3 # encoding: [0x24,0x48,0x23,0x01]
0x2c,0x48,0x23,0x01 == dadd $9, $9, $3 # encoding: [0x2c,0x48,0x23,0x01]
0x2d,0x48,0x23,0x01 == daddu $9, $9, $3 # encoding: [0x2d,0x48,0x23,0x01]
0x0a,0x00,0x29,0x61 == daddi $9, $9, 10 # encoding: [0x0a,0x00,0x29,0x61]
0x0a,0x00,0x29,0x65 == daddiu $9, $9, 10 # encoding: [0x0a,0x00,0x29,0x65]
0x2e,0x48,0x23,0x01 == dsub $9, $9, $3 # encoding: [0x2e,0x48,0x23,0x01]
0x2f,0x48,0x23,0x01 == dsubu $9, $9, $3 # encoding: [0x2f,0x48,0x23,0x01]
0xf6,0xff,0x29,0x61 == daddi $9, $9, -10 # encoding: [0xf6,0xff,0x29,0x61]
0xf6,0xff,0x29,0x65 == daddiu $9, $9, -10 # encoding: [0xf6,0xff,0x29,0x65]
0x25,0x48,0x23,0x01 == or $9, $9, $3 # encoding: [0x25,0x48,0x23,0x01]
0x26,0x48,0x23,0x01 == xor $9, $9, $3 # encoding: [0x26,0x48,0x23,0x01]
0x20,0x00,0x69,0x64 == daddiu $9, $3, 32 # encoding: [0x20,0x00,0x69,0x64]
0x20,0x00,0x69,0x64 == daddiu $9, $3, 32 # encoding: [0x20,0x00,0x69,0x64]
0xe0,0xff,0x69,0x64 == daddiu $9, $3, -32 # encoding: [0xe0,0xff,0x69,0x64]
0xe0,0xff,0x69,0x64 == daddiu $9, $3, -32 # encoding: [0xe0,0xff,0x69,0x64]

5
suite/MC/Mips/mips64-instructions.s.cs
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@ -1,3 +1,4 @@
# CS_ARCH_MIPS, CS_MODE_MIPS64, None
0x81,0x00,0x42,0x4d = ldxc1 $f2, $v0($t2)
0x09,0x40,0x24,0x4f = sdxc1 $f8, $a0($t9)
0x81,0x00,0x42,0x4d == ldxc1 $f2, $2($10) # encoding: [0x81,0x00,0x42,0x4d]
0x09,0x40,0x24,0x4f == sdxc1 $f8, $4($25) # encoding: [0x09,0x40,0x24,0x4f]

33
suite/MC/Mips/mips64-register-names-n32-n64.s.cs Normal file
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@ -0,0 +1,33 @@
# CS_ARCH_MIPS, CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN, None
0x64,0x00,0x00,0x00 == daddiu $zero, $zero, 0 # encoding: [0x64,0x00,0x00,0x00]
0x64,0x01,0x00,0x00 == daddiu $at, $zero, 0 # encoding: [0x64,0x01,0x00,0x00]
0x64,0x02,0x00,0x00 == daddiu $v0, $zero, 0 # encoding: [0x64,0x02,0x00,0x00]
0x64,0x03,0x00,0x00 == daddiu $v1, $zero, 0 # encoding: [0x64,0x03,0x00,0x00]
0x64,0x04,0x00,0x00 == daddiu $a0, $zero, 0 # encoding: [0x64,0x04,0x00,0x00]
0x64,0x05,0x00,0x00 == daddiu $a1, $zero, 0 # encoding: [0x64,0x05,0x00,0x00]
0x64,0x06,0x00,0x00 == daddiu $a2, $zero, 0 # encoding: [0x64,0x06,0x00,0x00]
0x64,0x07,0x00,0x00 == daddiu $a2, $zero, 0 # encoding: [0x64,0x07,0x00,0x00]
0x64,0x08,0x00,0x00 == daddiu $a4, $zero, 0 # encoding: [0x64,0x08,0x00,0x00]
0x64,0x09,0x00,0x00 == daddiu $a5, $zero, 0 # encoding: [0x64,0x09,0x00,0x00]
0x64,0x0a,0x00,0x00 == daddiu $a6, $zero, 0 # encoding: [0x64,0x0a,0x00,0x00]
0x64,0x0b,0x00,0x00 == daddiu $a7, $zero, 0 # encoding: [0x64,0x0b,0x00,0x00]
0x64,0x0c,0x00,0x00 == daddiu $t4, $zero, 0 # encoding: [0x64,0x0c,0x00,0x00]
0x64,0x0d,0x00,0x00 == daddiu $t5, $zero, 0 # encoding: [0x64,0x0d,0x00,0x00]
0x64,0x0e,0x00,0x00 == daddiu $t6, $zero, 0 # encoding: [0x64,0x0e,0x00,0x00]
0x64,0x0f,0x00,0x00 == daddiu $t7, $zero, 0 # encoding: [0x64,0x0f,0x00,0x00]
0x64,0x10,0x00,0x00 == daddiu $s0, $zero, 0 # encoding: [0x64,0x10,0x00,0x00]
0x64,0x11,0x00,0x00 == daddiu $s1, $zero, 0 # encoding: [0x64,0x11,0x00,0x00]
0x64,0x12,0x00,0x00 == daddiu $s2, $zero, 0 # encoding: [0x64,0x12,0x00,0x00]
0x64,0x13,0x00,0x00 == daddiu $s3, $zero, 0 # encoding: [0x64,0x13,0x00,0x00]
0x64,0x14,0x00,0x00 == daddiu $s4, $zero, 0 # encoding: [0x64,0x14,0x00,0x00]
0x64,0x15,0x00,0x00 == daddiu $s5, $zero, 0 # encoding: [0x64,0x15,0x00,0x00]
0x64,0x16,0x00,0x00 == daddiu $s6, $zero, 0 # encoding: [0x64,0x16,0x00,0x00]
0x64,0x17,0x00,0x00 == daddiu $s7, $zero, 0 # encoding: [0x64,0x17,0x00,0x00]
0x64,0x18,0x00,0x00 == daddiu $t8, $zero, 0 # encoding: [0x64,0x18,0x00,0x00]
0x64,0x19,0x00,0x00 == daddiu $t9, $zero, 0 # encoding: [0x64,0x19,0x00,0x00]
0x64,0x1a,0x00,0x00 == daddiu $kt0, $zero, 0 # encoding: [0x64,0x1a,0x00,0x00]
0x64,0x1b,0x00,0x00 == daddiu $kt1, $zero, 0 # encoding: [0x64,0x1b,0x00,0x00]
0x64,0x1c,0x00,0x00 == daddiu $gp, $zero, 0 # encoding: [0x64,0x1c,0x00,0x00]
0x64,0x1d,0x00,0x00 == daddiu $sp, $zero, 0 # encoding: [0x64,0x1d,0x00,0x00]
0x64,0x1e,0x00,0x00 == daddiu $s8, $zero, 0 # encoding: [0x64,0x1e,0x00,0x00]
0x64,0x1f,0x00,0x00 == daddiu $ra, $zero, 0 # encoding: [0x64,0x1f,0x00,0x00]

31
suite/MC/Mips/mips_directives.s.cs
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@ -1,12 +1,21 @@
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
0x10,0x00,0x01,0x4d = b 1336
0x08,0x00,0x01,0x4c = j 1328
0x0c,0x00,0x01,0x4c = jal 1328
0x10,0x00,0x01,0x4d = b 1336
0x00,0x00,0x00,0x00 = nop
0x08,0x00,0x01,0x4c = j 1328
0x00,0x00,0x00,0x00 = nop
0x0c,0x00,0x01,0x4c = jal 1328
0x00,0x00,0x00,0x00 = nop
0x46,0x00,0x39,0x85 = abs.s $f6, $f7
0x01,0xef,0x18,0x24 = and $v1, $t7, $t7
0x10,0x00,0x01,0x4d == b 1332 # encoding: [0x10,0x00,0x01,0x4d]
0x08,0x00,0x01,0x4c == j 1328 # encoding: [0x08,0x00,0x01,0x4c]
0x0c,0x00,0x01,0x4c == jal 1328 # encoding: [0x0c,0x00,0x01,0x4c]
0x10,0x00,0x01,0x4d == b 1332 # encoding: [0x10,0x00,0x01,0x4d]
0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00]
0x08,0x00,0x01,0x4c == j 1328 # encoding: [0x08,0x00,0x01,0x4c]
0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00]
0x0c,0x00,0x01,0x4c == jal 1328 # encoding: [0x0c,0x00,0x01,0x4c]
0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00]
0x46,0x00,0x39,0x85 == abs.s $f6, $f7 # encoding: [0x46,0x00,0x39,0x85]
0x3c,0x01, == lui $1, %hi($tmp7) # encoding: [0x3c,0x01,A,A]
0x4c,0xa0,0x00,0x01 == ldxc1 $f0, $zero($5) # encoding: [0x4c,0xa0,0x00,0x01]
0x4c,0xa6,0x00,0x05 == luxc1 $f0, $6($5) # encoding: [0x4c,0xa6,0x00,0x05]
0x4c,0xa2,0x01,0x80 == lwxc1 $f6, $2($5) # encoding: [0x4c,0xa2,0x01,0x80]
0x00,0x26,0x4f,0xba == drotr $9, $6, 30 # encoding: [0x00,0x26,0x4f,0xba]
0x7d,0x6a,0x39,0x8a == lbux $7, $10($11) # encoding: [0x7d,0x6a,0x39,0x8a]
0x7c,0xe6,0x29,0x0a == lhx $5, $6($7) # encoding: [0x7c,0xe6,0x29,0x0a]
0x7d,0x47,0x10,0x31 == append $7, $10, 2 # encoding: [0x7d,0x47,0x10,0x31]
0x7c,0xc5,0x1c,0x31 == balign $5, $6, 3 # encoding: [0x7c,0xc5,0x1c,0x31]

23
suite/MC/Mips/nabi-regs.s.cs
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@ -1,12 +1,13 @@
# CS_ARCH_MIPS, CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN, None
0x02,0x04,0x80,0x20 = add $s0, $s0, $a0
0x02,0x06,0x80,0x20 = add $s0, $s0, $a2
0x02,0x07,0x80,0x20 = add $s0, $s0, $a3
0x02,0x08,0x80,0x20 = add $s0, $s0, $t0
0x02,0x09,0x80,0x20 = add $s0, $s0, $t1
0x02,0x0a,0x80,0x20 = add $s0, $s0, $t2
0x02,0x0b,0x80,0x20 = add $s0, $s0, $t3
0x02,0x0c,0x80,0x20 = add $s0, $s0, $t4
0x02,0x0d,0x80,0x20 = add $s0, $s0, $t5
0x02,0x0e,0x80,0x20 = add $s0, $s0, $t6
0x02,0x0f,0x80,0x20 = add $s0, $s0, $t7
0x02,0x04,0x80,0x20 == add $16, $16, $4 # encoding: [0x02,0x04,0x80,0x20]
0x02,0x06,0x80,0x20 == add $16, $16, $6 # encoding: [0x02,0x06,0x80,0x20]
0x02,0x07,0x80,0x20 == add $16, $16, $7 # encoding: [0x02,0x07,0x80,0x20]
0x02,0x08,0x80,0x20 == add $16, $16, $8 # encoding: [0x02,0x08,0x80,0x20]
0x02,0x09,0x80,0x20 == add $16, $16, $9 # encoding: [0x02,0x09,0x80,0x20]
0x02,0x0a,0x80,0x20 == add $16, $16, $10 # encoding: [0x02,0x0a,0x80,0x20]
0x02,0x0b,0x80,0x20 == add $16, $16, $11 # encoding: [0x02,0x0b,0x80,0x20]
0x02,0x0c,0x80,0x20 == add $16, $16, $12 # encoding: [0x02,0x0c,0x80,0x20]
0x02,0x0d,0x80,0x20 == add $16, $16, $13 # encoding: [0x02,0x0d,0x80,0x20]
0x02,0x0e,0x80,0x20 == add $16, $16, $14 # encoding: [0x02,0x0e,0x80,0x20]
0x02,0x0f,0x80,0x20 == add $16, $16, $15 # encoding: [0x02,0x0f,0x80,0x20]

31
suite/MC/Mips/test_2r.s.cs
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@ -1,16 +1,17 @@
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
0x7b,0x00,0x4f,0x9e = fill.b $w30, $t1
0x7b,0x01,0xbf,0xde = fill.h $w31, $s7
0x7b,0x02,0xc4,0x1e = fill.w $w16, $t8
0x7b,0x08,0x05,0x5e = nloc.b $w21, $w0
0x7b,0x09,0xfc,0x9e = nloc.h $w18, $w31
0x7b,0x0a,0xb8,0x9e = nloc.w $w2, $w23
0x7b,0x0b,0x51,0x1e = nloc.d $w4, $w10
0x7b,0x0c,0x17,0xde = nlzc.b $w31, $w2
0x7b,0x0d,0xb6,0xde = nlzc.h $w27, $w22
0x7b,0x0e,0xea,0x9e = nlzc.w $w10, $w29
0x7b,0x0f,0x4e,0x5e = nlzc.d $w25, $w9
0x7b,0x04,0x95,0x1e = pcnt.b $w20, $w18
0x7b,0x05,0x40,0x1e = pcnt.h $w0, $w8
0x7b,0x06,0x4d,0xde = pcnt.w $w23, $w9
0x7b,0x07,0xc5,0x5e = pcnt.d $w21, $w24
0x7b,0x00,0x4f,0x9e == fill.b $w30, $9 # encoding: [0x7b,0x00,0x4f,0x9e]
0x7b,0x01,0xbf,0xde == fill.h $w31, $23 # encoding: [0x7b,0x01,0xbf,0xde]
0x7b,0x02,0xc4,0x1e == fill.w $w16, $24 # encoding: [0x7b,0x02,0xc4,0x1e]
0x7b,0x08,0x05,0x5e == nloc.b $w21, $w0 # encoding: [0x7b,0x08,0x05,0x5e]
0x7b,0x09,0xfc,0x9e == nloc.h $w18, $w31 # encoding: [0x7b,0x09,0xfc,0x9e]
0x7b,0x0a,0xb8,0x9e == nloc.w $w2, $w23 # encoding: [0x7b,0x0a,0xb8,0x9e]
0x7b,0x0b,0x51,0x1e == nloc.d $w4, $w10 # encoding: [0x7b,0x0b,0x51,0x1e]
0x7b,0x0c,0x17,0xde == nlzc.b $w31, $w2 # encoding: [0x7b,0x0c,0x17,0xde]
0x7b,0x0d,0xb6,0xde == nlzc.h $w27, $w22 # encoding: [0x7b,0x0d,0xb6,0xde]
0x7b,0x0e,0xea,0x9e == nlzc.w $w10, $w29 # encoding: [0x7b,0x0e,0xea,0x9e]
0x7b,0x0f,0x4e,0x5e == nlzc.d $w25, $w9 # encoding: [0x7b,0x0f,0x4e,0x5e]
0x7b,0x04,0x95,0x1e == pcnt.b $w20, $w18 # encoding: [0x7b,0x04,0x95,0x1e]
0x7b,0x05,0x40,0x1e == pcnt.h $w0, $w8 # encoding: [0x7b,0x05,0x40,0x1e]
0x7b,0x06,0x4d,0xde == pcnt.w $w23, $w9 # encoding: [0x7b,0x06,0x4d,0xde]
0x7b,0x07,0xc5,0x5e == pcnt.d $w21, $w24 # encoding: [0x7b,0x07,0xc5,0x5e]

65
suite/MC/Mips/test_2rf.s.cs
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@ -1,33 +1,34 @@
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
0x7b,0x20,0x66,0x9e = fclass.w $w26, $w12
0x7b,0x21,0x8e,0x1e = fclass.d $w24, $w17
0x7b,0x30,0x02,0x1e = fexupl.w $w8, $w0
0x7b,0x31,0xec,0x5e = fexupl.d $w17, $w29
0x7b,0x32,0x23,0x5e = fexupr.w $w13, $w4
0x7b,0x33,0x11,0x5e = fexupr.d $w5, $w2
0x7b,0x3c,0xed,0x1e = ffint_s.w $w20, $w29
0x7b,0x3d,0x7b,0x1e = ffint_s.d $w12, $w15
0x7b,0x3e,0xd9,0xde = ffint_u.w $w7, $w27
0x7b,0x3f,0x84,0xde = ffint_u.d $w19, $w16
0x7b,0x34,0x6f,0xde = ffql.w $w31, $w13
0x7b,0x35,0x6b,0x1e = ffql.d $w12, $w13
0x7b,0x36,0xf6,0xde = ffqr.w $w27, $w30
0x7b,0x37,0x7f,0x9e = ffqr.d $w30, $w15
0x7b,0x2e,0xfe,0x5e = flog2.w $w25, $w31
0x7b,0x2f,0x54,0x9e = flog2.d $w18, $w10
0x7b,0x2c,0x79,0xde = frint.w $w7, $w15
0x7b,0x2d,0xb5,0x5e = frint.d $w21, $w22
0x7b,0x2a,0x04,0xde = frcp.w $w19, $w0
0x7b,0x2b,0x71,0x1e = frcp.d $w4, $w14
0x7b,0x28,0x8b,0x1e = frsqrt.w $w12, $w17
0x7b,0x29,0x5d,0xde = frsqrt.d $w23, $w11
0x7b,0x26,0x58,0x1e = fsqrt.w $w0, $w11
0x7b,0x27,0x63,0xde = fsqrt.d $w15, $w12
0x7b,0x38,0x2f,0x9e = ftint_s.w $w30, $w5
0x7b,0x39,0xb9,0x5e = ftint_s.d $w5, $w23
0x7b,0x3a,0x75,0x1e = ftint_u.w $w20, $w14
0x7b,0x3b,0xad,0xde = ftint_u.d $w23, $w21
0x7b,0x22,0x8f,0x5e = ftrunc_s.w $w29, $w17
0x7b,0x23,0xdb,0x1e = ftrunc_s.d $w12, $w27
0x7b,0x24,0x7c,0x5e = ftrunc_u.w $w17, $w15
0x7b,0x25,0xd9,0x5e = ftrunc_u.d $w5, $w27
0x7b,0x20,0x66,0x9e == fclass.w $w26, $w12 # encoding: [0x7b,0x20,0x66,0x9e]
0x7b,0x21,0x8e,0x1e == fclass.d $w24, $w17 # encoding: [0x7b,0x21,0x8e,0x1e]
0x7b,0x30,0x02,0x1e == fexupl.w $w8, $w0 # encoding: [0x7b,0x30,0x02,0x1e]
0x7b,0x31,0xec,0x5e == fexupl.d $w17, $w29 # encoding: [0x7b,0x31,0xec,0x5e]
0x7b,0x32,0x23,0x5e == fexupr.w $w13, $w4 # encoding: [0x7b,0x32,0x23,0x5e]
0x7b,0x33,0x11,0x5e == fexupr.d $w5, $w2 # encoding: [0x7b,0x33,0x11,0x5e]
0x7b,0x3c,0xed,0x1e == ffint_s.w $w20, $w29 # encoding: [0x7b,0x3c,0xed,0x1e]
0x7b,0x3d,0x7b,0x1e == ffint_s.d $w12, $w15 # encoding: [0x7b,0x3d,0x7b,0x1e]
0x7b,0x3e,0xd9,0xde == ffint_u.w $w7, $w27 # encoding: [0x7b,0x3e,0xd9,0xde]
0x7b,0x3f,0x84,0xde == ffint_u.d $w19, $w16 # encoding: [0x7b,0x3f,0x84,0xde]
0x7b,0x34,0x6f,0xde == ffql.w $w31, $w13 # encoding: [0x7b,0x34,0x6f,0xde]
0x7b,0x35,0x6b,0x1e == ffql.d $w12, $w13 # encoding: [0x7b,0x35,0x6b,0x1e]
0x7b,0x36,0xf6,0xde == ffqr.w $w27, $w30 # encoding: [0x7b,0x36,0xf6,0xde]
0x7b,0x37,0x7f,0x9e == ffqr.d $w30, $w15 # encoding: [0x7b,0x37,0x7f,0x9e]
0x7b,0x2e,0xfe,0x5e == flog2.w $w25, $w31 # encoding: [0x7b,0x2e,0xfe,0x5e]
0x7b,0x2f,0x54,0x9e == flog2.d $w18, $w10 # encoding: [0x7b,0x2f,0x54,0x9e]
0x7b,0x2c,0x79,0xde == frint.w $w7, $w15 # encoding: [0x7b,0x2c,0x79,0xde]
0x7b,0x2d,0xb5,0x5e == frint.d $w21, $w22 # encoding: [0x7b,0x2d,0xb5,0x5e]
0x7b,0x2a,0x04,0xde == frcp.w $w19, $w0 # encoding: [0x7b,0x2a,0x04,0xde]
0x7b,0x2b,0x71,0x1e == frcp.d $w4, $w14 # encoding: [0x7b,0x2b,0x71,0x1e]
0x7b,0x28,0x8b,0x1e == frsqrt.w $w12, $w17 # encoding: [0x7b,0x28,0x8b,0x1e]
0x7b,0x29,0x5d,0xde == frsqrt.d $w23, $w11 # encoding: [0x7b,0x29,0x5d,0xde]
0x7b,0x26,0x58,0x1e == fsqrt.w $w0, $w11 # encoding: [0x7b,0x26,0x58,0x1e]
0x7b,0x27,0x63,0xde == fsqrt.d $w15, $w12 # encoding: [0x7b,0x27,0x63,0xde]
0x7b,0x38,0x2f,0x9e == ftint_s.w $w30, $w5 # encoding: [0x7b,0x38,0x2f,0x9e]
0x7b,0x39,0xb9,0x5e == ftint_s.d $w5, $w23 # encoding: [0x7b,0x39,0xb9,0x5e]
0x7b,0x3a,0x75,0x1e == ftint_u.w $w20, $w14 # encoding: [0x7b,0x3a,0x75,0x1e]
0x7b,0x3b,0xad,0xde == ftint_u.d $w23, $w21 # encoding: [0x7b,0x3b,0xad,0xde]
0x7b,0x22,0x8f,0x5e == ftrunc_s.w $w29, $w17 # encoding: [0x7b,0x22,0x8f,0x5e]
0x7b,0x23,0xdb,0x1e == ftrunc_s.d $w12, $w27 # encoding: [0x7b,0x23,0xdb,0x1e]
0x7b,0x24,0x7c,0x5e == ftrunc_u.w $w17, $w15 # encoding: [0x7b,0x24,0x7c,0x5e]
0x7b,0x25,0xd9,0x5e == ftrunc_u.d $w5, $w27 # encoding: [0x7b,0x25,0xd9,0x5e]

485
suite/MC/Mips/test_3r.s.cs
View File

@ -1,243 +1,244 @@
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
0x78,0x04,0x4e,0x90 = add_a.b $w26, $w9, $w4
0x78,0x3f,0xdd,0xd0 = add_a.h $w23, $w27, $w31
0x78,0x56,0x32,0xd0 = add_a.w $w11, $w6, $w22
0x78,0x60,0x51,0x90 = add_a.d $w6, $w10, $w0
0x78,0x93,0xc4,0xd0 = adds_a.b $w19, $w24, $w19
0x78,0xa4,0x36,0x50 = adds_a.h $w25, $w6, $w4
0x78,0xdb,0x8e,0x50 = adds_a.w $w25, $w17, $w27
0x78,0xfa,0x93,0xd0 = adds_a.d $w15, $w18, $w26
0x79,0x13,0x5f,0x50 = adds_s.b $w29, $w11, $w19
0x79,0x3a,0xb9,0x50 = adds_s.h $w5, $w23, $w26
0x79,0x4d,0x74,0x10 = adds_s.w $w16, $w14, $w13
0x79,0x7c,0x70,0x90 = adds_s.d $w2, $w14, $w28
0x79,0x8e,0x88,0xd0 = adds_u.b $w3, $w17, $w14
0x79,0xa4,0xf2,0x90 = adds_u.h $w10, $w30, $w4
0x79,0xd4,0x93,0xd0 = adds_u.w $w15, $w18, $w20
0x79,0xe9,0x57,0x90 = adds_u.d $w30, $w10, $w9
0x78,0x15,0xa6,0x0e = addv.b $w24, $w20, $w21
0x78,0x3b,0x69,0x0e = addv.h $w4, $w13, $w27
0x78,0x4e,0x5c,0xce = addv.w $w19, $w11, $w14
0x78,0x7f,0xa8,0x8e = addv.d $w2, $w21, $w31
0x7a,0x03,0x85,0xd1 = asub_s.b $w23, $w16, $w3
0x7a,0x39,0x8d,0x91 = asub_s.h $w22, $w17, $w25
0x7a,0x49,0x0e,0x11 = asub_s.w $w24, $w1, $w9
0x7a,0x6c,0x63,0x51 = asub_s.d $w13, $w12, $w12
0x7a,0x8b,0xea,0x91 = asub_u.b $w10, $w29, $w11
0x7a,0xaf,0x4c,0x91 = asub_u.h $w18, $w9, $w15
0x7a,0xdf,0x9a,0x91 = asub_u.w $w10, $w19, $w31
0x7a,0xe0,0x54,0x51 = asub_u.d $w17, $w10, $w0
0x7a,0x01,0x28,0x90 = ave_s.b $w2, $w5, $w1
0x7a,0x29,0x9c,0x10 = ave_s.h $w16, $w19, $w9
0x7a,0x45,0xfc,0x50 = ave_s.w $w17, $w31, $w5
0x7a,0x6a,0xce,0xd0 = ave_s.d $w27, $w25, $w10
0x7a,0x89,0x9c,0x10 = ave_u.b $w16, $w19, $w9
0x7a,0xab,0xe7,0x10 = ave_u.h $w28, $w28, $w11
0x7a,0xcb,0x62,0xd0 = ave_u.w $w11, $w12, $w11
0x7a,0xfc,0x9f,0x90 = ave_u.d $w30, $w19, $w28
0x7b,0x02,0x86,0x90 = aver_s.b $w26, $w16, $w2
0x7b,0x3b,0xdf,0xd0 = aver_s.h $w31, $w27, $w27
0x7b,0x59,0x97,0x10 = aver_s.w $w28, $w18, $w25
0x7b,0x7b,0xaf,0x50 = aver_s.d $w29, $w21, $w27
0x7b,0x83,0xd7,0x50 = aver_u.b $w29, $w26, $w3
0x7b,0xa9,0x94,0x90 = aver_u.h $w18, $w18, $w9
0x7b,0xdd,0xcc,0x50 = aver_u.w $w17, $w25, $w29
0x7b,0xf3,0xb5,0x90 = aver_u.d $w22, $w22, $w19
0x79,0x9d,0x78,0x8d = bclr.b $w2, $w15, $w29
0x79,0xbc,0xac,0x0d = bclr.h $w16, $w21, $w28
0x79,0xc9,0x14,0xcd = bclr.w $w19, $w2, $w9
0x79,0xe4,0xfe,0xcd = bclr.d $w27, $w31, $w4
0x7b,0x18,0x81,0x4d = binsl.b $w5, $w16, $w24
0x7b,0x2a,0x2f,0x8d = binsl.h $w30, $w5, $w10
0x7b,0x4d,0x7b,0x8d = binsl.w $w14, $w15, $w13
0x7b,0x6c,0xa5,0xcd = binsl.d $w23, $w20, $w12
0x7b,0x82,0x5d,0x8d = binsr.b $w22, $w11, $w2
0x7b,0xa6,0xd0,0x0d = binsr.h $w0, $w26, $w6
0x7b,0xdc,0x1e,0x8d = binsr.w $w26, $w3, $w28
0x7b,0xf5,0x00,0x0d = binsr.d $w0, $w0, $w21
0x7a,0x98,0x58,0x0d = bneg.b $w0, $w11, $w24
0x7a,0xa4,0x87,0x0d = bneg.h $w28, $w16, $w4
0x7a,0xd3,0xd0,0xcd = bneg.w $w3, $w26, $w19
0x7a,0xef,0xeb,0x4d = bneg.d $w13, $w29, $w15
0x7a,0x1f,0x2f,0xcd = bset.b $w31, $w5, $w31
0x7a,0x26,0x63,0x8d = bset.h $w14, $w12, $w6
0x7a,0x4c,0x4f,0xcd = bset.w $w31, $w9, $w12
0x7a,0x65,0xb1,0x4d = bset.d $w5, $w22, $w5
0x78,0x12,0xff,0xcf = ceq.b $w31, $w31, $w18
0x78,0x29,0xda,0x8f = ceq.h $w10, $w27, $w9
0x78,0x4e,0x2a,0x4f = ceq.w $w9, $w5, $w14
0x78,0x60,0x89,0x4f = ceq.d $w5, $w17, $w0
0x7a,0x09,0x25,0xcf = cle_s.b $w23, $w4, $w9
0x7a,0x33,0xdd,0x8f = cle_s.h $w22, $w27, $w19
0x7a,0x4a,0xd7,0x8f = cle_s.w $w30, $w26, $w10
0x7a,0x6a,0x2c,0x8f = cle_s.d $w18, $w5, $w10
0x7a,0x80,0xc8,0x4f = cle_u.b $w1, $w25, $w0
0x7a,0xbd,0x01,0xcf = cle_u.h $w7, $w0, $w29
0x7a,0xc1,0x96,0x4f = cle_u.w $w25, $w18, $w1
0x7a,0xfe,0x01,0x8f = cle_u.d $w6, $w0, $w30
0x79,0x15,0x16,0x4f = clt_s.b $w25, $w2, $w21
0x79,0x29,0x98,0x8f = clt_s.h $w2, $w19, $w9
0x79,0x50,0x45,0xcf = clt_s.w $w23, $w8, $w16
0x79,0x6c,0xf1,0xcf = clt_s.d $w7, $w30, $w12
0x79,0x8d,0xf8,0x8f = clt_u.b $w2, $w31, $w13
0x79,0xb7,0xfc,0x0f = clt_u.h $w16, $w31, $w23
0x79,0xc9,0xc0,0xcf = clt_u.w $w3, $w24, $w9
0x79,0xe1,0x01,0xcf = clt_u.d $w7, $w0, $w1
0x7a,0x12,0x1f,0x52 = div_s.b $w29, $w3, $w18
0x7a,0x2d,0x84,0x52 = div_s.h $w17, $w16, $w13
0x7a,0x5e,0xc9,0x12 = div_s.w $w4, $w25, $w30
0x7a,0x74,0x4f,0xd2 = div_s.d $w31, $w9, $w20
0x7a,0x8a,0xe9,0x92 = div_u.b $w6, $w29, $w10
0x7a,0xae,0xae,0x12 = div_u.h $w24, $w21, $w14
0x7a,0xd9,0x77,0x52 = div_u.w $w29, $w14, $w25
0x7a,0xf5,0x0f,0xd2 = div_u.d $w31, $w1, $w21
0x78,0x39,0xb5,0xd3 = dotp_s.h $w23, $w22, $w25
0x78,0x45,0x75,0x13 = dotp_s.w $w20, $w14, $w5
0x78,0x76,0x14,0x53 = dotp_s.d $w17, $w2, $w22
0x78,0xa6,0x13,0x53 = dotp_u.h $w13, $w2, $w6
0x78,0xd5,0xb3,0xd3 = dotp_u.w $w15, $w22, $w21
0x78,0xfa,0x81,0x13 = dotp_u.d $w4, $w16, $w26
0x79,0x36,0xe0,0x53 = dpadd_s.h $w1, $w28, $w22
0x79,0x4c,0x0a,0x93 = dpadd_s.w $w10, $w1, $w12
0x79,0x7b,0xa8,0xd3 = dpadd_s.d $w3, $w21, $w27
0x79,0xb4,0x2c,0x53 = dpadd_u.h $w17, $w5, $w20
0x79,0xd0,0x46,0x13 = dpadd_u.w $w24, $w8, $w16
0x79,0xf0,0xeb,0xd3 = dpadd_u.d $w15, $w29, $w16
0x7a,0x2c,0x59,0x13 = dpsub_s.h $w4, $w11, $w12
0x7a,0x46,0x39,0x13 = dpsub_s.w $w4, $w7, $w6
0x7a,0x7c,0x67,0xd3 = dpsub_s.d $w31, $w12, $w28
0x7a,0xb1,0xc9,0x13 = dpsub_u.h $w4, $w25, $w17
0x7a,0xd0,0xcc,0xd3 = dpsub_u.w $w19, $w25, $w16
0x7a,0xfa,0x51,0xd3 = dpsub_u.d $w7, $w10, $w26
0x7a,0x22,0xc7,0x15 = hadd_s.h $w28, $w24, $w2
0x7a,0x4b,0x8e,0x15 = hadd_s.w $w24, $w17, $w11
0x7a,0x74,0x7c,0x55 = hadd_s.d $w17, $w15, $w20
0x7a,0xb1,0xeb,0x15 = hadd_u.h $w12, $w29, $w17
0x7a,0xc6,0x2a,0x55 = hadd_u.w $w9, $w5, $w6
0x7a,0xe6,0xa0,0x55 = hadd_u.d $w1, $w20, $w6
0x7b,0x3d,0x74,0x15 = hsub_s.h $w16, $w14, $w29
0x7b,0x4b,0x6a,0x55 = hsub_s.w $w9, $w13, $w11
0x7b,0x6e,0x97,0x95 = hsub_s.d $w30, $w18, $w14
0x7b,0xae,0x61,0xd5 = hsub_u.h $w7, $w12, $w14
0x7b,0xc5,0x2d,0x55 = hsub_u.w $w21, $w5, $w5
0x7b,0xff,0x62,0xd5 = hsub_u.d $w11, $w12, $w31
0x7b,0x1e,0x84,0x94 = ilvev.b $w18, $w16, $w30
0x7b,0x2d,0x03,0x94 = ilvev.h $w14, $w0, $w13
0x7b,0x56,0xcb,0x14 = ilvev.w $w12, $w25, $w22
0x7b,0x63,0xdf,0x94 = ilvev.d $w30, $w27, $w3
0x7a,0x15,0x1f,0x54 = ilvl.b $w29, $w3, $w21
0x7a,0x31,0x56,0xd4 = ilvl.h $w27, $w10, $w17
0x7a,0x40,0x09,0x94 = ilvl.w $w6, $w1, $w0
0x7a,0x78,0x80,0xd4 = ilvl.d $w3, $w16, $w24
0x7b,0x94,0x2a,0xd4 = ilvod.b $w11, $w5, $w20
0x7b,0xbf,0x6c,0x94 = ilvod.h $w18, $w13, $w31
0x7b,0xd8,0x87,0x54 = ilvod.w $w29, $w16, $w24
0x7b,0xfd,0x65,0x94 = ilvod.d $w22, $w12, $w29
0x7a,0x86,0xf1,0x14 = ilvr.b $w4, $w30, $w6
0x7a,0xbd,0x9f,0x14 = ilvr.h $w28, $w19, $w29
0x7a,0xd5,0xa4,0x94 = ilvr.w $w18, $w20, $w21
0x7a,0xec,0xf5,0xd4 = ilvr.d $w23, $w30, $w12
0x78,0x9d,0xfc,0x52 = maddv.b $w17, $w31, $w29
0x78,0xa9,0xc1,0xd2 = maddv.h $w7, $w24, $w9
0x78,0xd4,0xb5,0x92 = maddv.w $w22, $w22, $w20
0x78,0xf4,0xd7,0x92 = maddv.d $w30, $w26, $w20
0x7b,0x17,0x5d,0xce = max_a.b $w23, $w11, $w23
0x7b,0x3e,0x2d,0x0e = max_a.h $w20, $w5, $w30
0x7b,0x5e,0x91,0xce = max_a.w $w7, $w18, $w30
0x7b,0x7f,0x42,0x0e = max_a.d $w8, $w8, $w31
0x79,0x13,0x0a,0x8e = max_s.b $w10, $w1, $w19
0x79,0x31,0xeb,0xce = max_s.h $w15, $w29, $w17
0x79,0x4e,0xeb,0xce = max_s.w $w15, $w29, $w14
0x79,0x63,0xc6,0x4e = max_s.d $w25, $w24, $w3
0x79,0x85,0xc3,0x0e = max_u.b $w12, $w24, $w5
0x79,0xa7,0x31,0x4e = max_u.h $w5, $w6, $w7
0x79,0xc7,0x24,0x0e = max_u.w $w16, $w4, $w7
0x79,0xf8,0x66,0x8e = max_u.d $w26, $w12, $w24
0x7b,0x81,0xd1,0x0e = min_a.b $w4, $w26, $w1
0x7b,0xbf,0x6b,0x0e = min_a.h $w12, $w13, $w31
0x7b,0xc0,0xa7,0x0e = min_a.w $w28, $w20, $w0
0x7b,0xf3,0xa3,0x0e = min_a.d $w12, $w20, $w19
0x7a,0x0e,0x1c,0xce = min_s.b $w19, $w3, $w14
0x7a,0x28,0xae,0xce = min_s.h $w27, $w21, $w8
0x7a,0x5e,0x70,0x0e = min_s.w $w0, $w14, $w30
0x7a,0x75,0x41,0x8e = min_s.d $w6, $w8, $w21
0x7a,0x88,0xd5,0x8e = min_u.b $w22, $w26, $w8
0x7a,0xac,0xd9,0xce = min_u.h $w7, $w27, $w12
0x7a,0xce,0xa2,0x0e = min_u.w $w8, $w20, $w14
0x7a,0xef,0x76,0x8e = min_u.d $w26, $w14, $w15
0x7b,0x1a,0x0c,0x92 = mod_s.b $w18, $w1, $w26
0x7b,0x3c,0xf7,0xd2 = mod_s.h $w31, $w30, $w28
0x7b,0x4d,0x30,0x92 = mod_s.w $w2, $w6, $w13
0x7b,0x76,0xdd,0x52 = mod_s.d $w21, $w27, $w22
0x7b,0x8d,0x3c,0x12 = mod_u.b $w16, $w7, $w13
0x7b,0xa7,0x46,0x12 = mod_u.h $w24, $w8, $w7
0x7b,0xd1,0x17,0x92 = mod_u.w $w30, $w2, $w17
0x7b,0xf9,0x17,0xd2 = mod_u.d $w31, $w2, $w25
0x79,0x0c,0x2b,0x92 = msubv.b $w14, $w5, $w12
0x79,0x3e,0x39,0x92 = msubv.h $w6, $w7, $w30
0x79,0x55,0x13,0x52 = msubv.w $w13, $w2, $w21
0x79,0x7b,0x74,0x12 = msubv.d $w16, $w14, $w27
0x78,0x0d,0x1d,0x12 = mulv.b $w20, $w3, $w13
0x78,0x2e,0xd6,0xd2 = mulv.h $w27, $w26, $w14
0x78,0x43,0xea,0x92 = mulv.w $w10, $w29, $w3
0x78,0x7d,0x99,0xd2 = mulv.d $w7, $w19, $w29
0x79,0x07,0xd9,0x54 = pckev.b $w5, $w27, $w7
0x79,0x3b,0x20,0x54 = pckev.h $w1, $w4, $w27
0x79,0x40,0xa7,0x94 = pckev.w $w30, $w20, $w0
0x79,0x6f,0x09,0x94 = pckev.d $w6, $w1, $w15
0x79,0x9e,0xe4,0x94 = pckod.b $w18, $w28, $w30
0x79,0xa8,0x2e,0x94 = pckod.h $w26, $w5, $w8
0x79,0xc2,0x22,0x54 = pckod.w $w9, $w4, $w2
0x79,0xf4,0xb7,0x94 = pckod.d $w30, $w22, $w20
0x78,0x0c,0xb9,0x54 = sld.b $w5, $w23[$t4]
0x78,0x23,0xb8,0x54 = sld.h $w1, $w23[$v1]
0x78,0x49,0x45,0x14 = sld.w $w20, $w8[$t1]
0x78,0x7e,0xb9,0xd4 = sld.d $w7, $w23[$fp]
0x78,0x11,0x00,0xcd = sll.b $w3, $w0, $w17
0x78,0x23,0xdc,0x4d = sll.h $w17, $w27, $w3
0x78,0x46,0x3c,0x0d = sll.w $w16, $w7, $w6
0x78,0x7a,0x02,0x4d = sll.d $w9, $w0, $w26
0x78,0x81,0x0f,0x14 = splat.b $w28, $w1[$at]
0x78,0xab,0x58,0x94 = splat.h $w2, $w11[$t3]
0x78,0xcb,0x05,0x94 = splat.w $w22, $w0[$t3]
0x78,0xe2,0x00,0x14 = splat.d $w0, $w0[$v0]
0x78,0x91,0x27,0x0d = sra.b $w28, $w4, $w17
0x78,0xa3,0x4b,0x4d = sra.h $w13, $w9, $w3
0x78,0xd3,0xae,0xcd = sra.w $w27, $w21, $w19
0x78,0xf7,0x47,0x8d = sra.d $w30, $w8, $w23
0x78,0x92,0x94,0xd5 = srar.b $w19, $w18, $w18
0x78,0xa8,0xb9,0xd5 = srar.h $w7, $w23, $w8
0x78,0xc2,0x60,0x55 = srar.w $w1, $w12, $w2
0x78,0xee,0x3d,0x55 = srar.d $w21, $w7, $w14
0x79,0x13,0x1b,0x0d = srl.b $w12, $w3, $w19
0x79,0x34,0xfd,0xcd = srl.h $w23, $w31, $w20
0x79,0x4b,0xdc,0x8d = srl.w $w18, $w27, $w11
0x79,0x7a,0x60,0xcd = srl.d $w3, $w12, $w26
0x79,0x0b,0xab,0xd5 = srlr.b $w15, $w21, $w11
0x79,0x33,0x6d,0x55 = srlr.h $w21, $w13, $w19
0x79,0x43,0xf1,0x95 = srlr.w $w6, $w30, $w3
0x79,0x6e,0x10,0x55 = srlr.d $w1, $w2, $w14
0x78,0x01,0x7e,0x51 = subs_s.b $w25, $w15, $w1
0x78,0x36,0xcf,0x11 = subs_s.h $w28, $w25, $w22
0x78,0x55,0x62,0x91 = subs_s.w $w10, $w12, $w21
0x78,0x72,0xa1,0x11 = subs_s.d $w4, $w20, $w18
0x78,0x99,0x35,0x51 = subs_u.b $w21, $w6, $w25
0x78,0xa7,0x50,0xd1 = subs_u.h $w3, $w10, $w7
0x78,0xca,0x7a,0x51 = subs_u.w $w9, $w15, $w10
0x78,0xea,0x99,0xd1 = subs_u.d $w7, $w19, $w10
0x79,0x0c,0x39,0x91 = subsus_u.b $w6, $w7, $w12
0x79,0x33,0xe9,0x91 = subsus_u.h $w6, $w29, $w19
0x79,0x47,0x79,0xd1 = subsus_u.w $w7, $w15, $w7
0x79,0x6f,0x1a,0x51 = subsus_u.d $w9, $w3, $w15
0x79,0x9f,0x1d,0x91 = subsuu_s.b $w22, $w3, $w31
0x79,0xb6,0xbc,0xd1 = subsuu_s.h $w19, $w23, $w22
0x79,0xcd,0x52,0x51 = subsuu_s.w $w9, $w10, $w13
0x79,0xe0,0x31,0x51 = subsuu_s.d $w5, $w6, $w0
0x78,0x93,0x69,0x8e = subv.b $w6, $w13, $w19
0x78,0xac,0xc9,0x0e = subv.h $w4, $w25, $w12
0x78,0xcb,0xde,0xce = subv.w $w27, $w27, $w11
0x78,0xea,0xc2,0x4e = subv.d $w9, $w24, $w10
0x78,0x05,0x80,0xd5 = vshf.b $w3, $w16, $w5
0x78,0x28,0x9d,0x15 = vshf.h $w20, $w19, $w8
0x78,0x59,0xf4,0x15 = vshf.w $w16, $w30, $w25
0x78,0x6f,0x5c,0xd5 = vshf.d $w19, $w11, $w15
0x78,0x04,0x4e,0x90 == add_a.b $w26, $w9, $w4 # encoding: [0x78,0x04,0x4e,0x90]
0x78,0x3f,0xdd,0xd0 == add_a.h $w23, $w27, $w31 # encoding: [0x78,0x3f,0xdd,0xd0]
0x78,0x56,0x32,0xd0 == add_a.w $w11, $w6, $w22 # encoding: [0x78,0x56,0x32,0xd0]
0x78,0x60,0x51,0x90 == add_a.d $w6, $w10, $w0 # encoding: [0x78,0x60,0x51,0x90]
0x78,0x93,0xc4,0xd0 == adds_a.b $w19, $w24, $w19 # encoding: [0x78,0x93,0xc4,0xd0]
0x78,0xa4,0x36,0x50 == adds_a.h $w25, $w6, $w4 # encoding: [0x78,0xa4,0x36,0x50]
0x78,0xdb,0x8e,0x50 == adds_a.w $w25, $w17, $w27 # encoding: [0x78,0xdb,0x8e,0x50]
0x78,0xfa,0x93,0xd0 == adds_a.d $w15, $w18, $w26 # encoding: [0x78,0xfa,0x93,0xd0]
0x79,0x13,0x5f,0x50 == adds_s.b $w29, $w11, $w19 # encoding: [0x79,0x13,0x5f,0x50]
0x79,0x3a,0xb9,0x50 == adds_s.h $w5, $w23, $w26 # encoding: [0x79,0x3a,0xb9,0x50]
0x79,0x4d,0x74,0x10 == adds_s.w $w16, $w14, $w13 # encoding: [0x79,0x4d,0x74,0x10]
0x79,0x7c,0x70,0x90 == adds_s.d $w2, $w14, $w28 # encoding: [0x79,0x7c,0x70,0x90]
0x79,0x8e,0x88,0xd0 == adds_u.b $w3, $w17, $w14 # encoding: [0x79,0x8e,0x88,0xd0]
0x79,0xa4,0xf2,0x90 == adds_u.h $w10, $w30, $w4 # encoding: [0x79,0xa4,0xf2,0x90]
0x79,0xd4,0x93,0xd0 == adds_u.w $w15, $w18, $w20 # encoding: [0x79,0xd4,0x93,0xd0]
0x79,0xe9,0x57,0x90 == adds_u.d $w30, $w10, $w9 # encoding: [0x79,0xe9,0x57,0x90]
0x78,0x15,0xa6,0x0e == addv.b $w24, $w20, $w21 # encoding: [0x78,0x15,0xa6,0x0e]
0x78,0x3b,0x69,0x0e == addv.h $w4, $w13, $w27 # encoding: [0x78,0x3b,0x69,0x0e]
0x78,0x4e,0x5c,0xce == addv.w $w19, $w11, $w14 # encoding: [0x78,0x4e,0x5c,0xce]
0x78,0x7f,0xa8,0x8e == addv.d $w2, $w21, $w31 # encoding: [0x78,0x7f,0xa8,0x8e]
0x7a,0x03,0x85,0xd1 == asub_s.b $w23, $w16, $w3 # encoding: [0x7a,0x03,0x85,0xd1]
0x7a,0x39,0x8d,0x91 == asub_s.h $w22, $w17, $w25 # encoding: [0x7a,0x39,0x8d,0x91]
0x7a,0x49,0x0e,0x11 == asub_s.w $w24, $w1, $w9 # encoding: [0x7a,0x49,0x0e,0x11]
0x7a,0x6c,0x63,0x51 == asub_s.d $w13, $w12, $w12 # encoding: [0x7a,0x6c,0x63,0x51]
0x7a,0x8b,0xea,0x91 == asub_u.b $w10, $w29, $w11 # encoding: [0x7a,0x8b,0xea,0x91]
0x7a,0xaf,0x4c,0x91 == asub_u.h $w18, $w9, $w15 # encoding: [0x7a,0xaf,0x4c,0x91]
0x7a,0xdf,0x9a,0x91 == asub_u.w $w10, $w19, $w31 # encoding: [0x7a,0xdf,0x9a,0x91]
0x7a,0xe0,0x54,0x51 == asub_u.d $w17, $w10, $w0 # encoding: [0x7a,0xe0,0x54,0x51]
0x7a,0x01,0x28,0x90 == ave_s.b $w2, $w5, $w1 # encoding: [0x7a,0x01,0x28,0x90]
0x7a,0x29,0x9c,0x10 == ave_s.h $w16, $w19, $w9 # encoding: [0x7a,0x29,0x9c,0x10]
0x7a,0x45,0xfc,0x50 == ave_s.w $w17, $w31, $w5 # encoding: [0x7a,0x45,0xfc,0x50]
0x7a,0x6a,0xce,0xd0 == ave_s.d $w27, $w25, $w10 # encoding: [0x7a,0x6a,0xce,0xd0]
0x7a,0x89,0x9c,0x10 == ave_u.b $w16, $w19, $w9 # encoding: [0x7a,0x89,0x9c,0x10]
0x7a,0xab,0xe7,0x10 == ave_u.h $w28, $w28, $w11 # encoding: [0x7a,0xab,0xe7,0x10]
0x7a,0xcb,0x62,0xd0 == ave_u.w $w11, $w12, $w11 # encoding: [0x7a,0xcb,0x62,0xd0]
0x7a,0xfc,0x9f,0x90 == ave_u.d $w30, $w19, $w28 # encoding: [0x7a,0xfc,0x9f,0x90]
0x7b,0x02,0x86,0x90 == aver_s.b $w26, $w16, $w2 # encoding: [0x7b,0x02,0x86,0x90]
0x7b,0x3b,0xdf,0xd0 == aver_s.h $w31, $w27, $w27 # encoding: [0x7b,0x3b,0xdf,0xd0]
0x7b,0x59,0x97,0x10 == aver_s.w $w28, $w18, $w25 # encoding: [0x7b,0x59,0x97,0x10]
0x7b,0x7b,0xaf,0x50 == aver_s.d $w29, $w21, $w27 # encoding: [0x7b,0x7b,0xaf,0x50]
0x7b,0x83,0xd7,0x50 == aver_u.b $w29, $w26, $w3 # encoding: [0x7b,0x83,0xd7,0x50]
0x7b,0xa9,0x94,0x90 == aver_u.h $w18, $w18, $w9 # encoding: [0x7b,0xa9,0x94,0x90]
0x7b,0xdd,0xcc,0x50 == aver_u.w $w17, $w25, $w29 # encoding: [0x7b,0xdd,0xcc,0x50]
0x7b,0xf3,0xb5,0x90 == aver_u.d $w22, $w22, $w19 # encoding: [0x7b,0xf3,0xb5,0x90]
0x79,0x9d,0x78,0x8d == bclr.b $w2, $w15, $w29 # encoding: [0x79,0x9d,0x78,0x8d]
0x79,0xbc,0xac,0x0d == bclr.h $w16, $w21, $w28 # encoding: [0x79,0xbc,0xac,0x0d]
0x79,0xc9,0x14,0xcd == bclr.w $w19, $w2, $w9 # encoding: [0x79,0xc9,0x14,0xcd]
0x79,0xe4,0xfe,0xcd == bclr.d $w27, $w31, $w4 # encoding: [0x79,0xe4,0xfe,0xcd]
0x7b,0x18,0x81,0x4d == binsl.b $w5, $w16, $w24 # encoding: [0x7b,0x18,0x81,0x4d]
0x7b,0x2a,0x2f,0x8d == binsl.h $w30, $w5, $w10 # encoding: [0x7b,0x2a,0x2f,0x8d]
0x7b,0x4d,0x7b,0x8d == binsl.w $w14, $w15, $w13 # encoding: [0x7b,0x4d,0x7b,0x8d]
0x7b,0x6c,0xa5,0xcd == binsl.d $w23, $w20, $w12 # encoding: [0x7b,0x6c,0xa5,0xcd]
0x7b,0x82,0x5d,0x8d == binsr.b $w22, $w11, $w2 # encoding: [0x7b,0x82,0x5d,0x8d]
0x7b,0xa6,0xd0,0x0d == binsr.h $w0, $w26, $w6 # encoding: [0x7b,0xa6,0xd0,0x0d]
0x7b,0xdc,0x1e,0x8d == binsr.w $w26, $w3, $w28 # encoding: [0x7b,0xdc,0x1e,0x8d]
0x7b,0xf5,0x00,0x0d == binsr.d $w0, $w0, $w21 # encoding: [0x7b,0xf5,0x00,0x0d]
0x7a,0x98,0x58,0x0d == bneg.b $w0, $w11, $w24 # encoding: [0x7a,0x98,0x58,0x0d]
0x7a,0xa4,0x87,0x0d == bneg.h $w28, $w16, $w4 # encoding: [0x7a,0xa4,0x87,0x0d]
0x7a,0xd3,0xd0,0xcd == bneg.w $w3, $w26, $w19 # encoding: [0x7a,0xd3,0xd0,0xcd]
0x7a,0xef,0xeb,0x4d == bneg.d $w13, $w29, $w15 # encoding: [0x7a,0xef,0xeb,0x4d]
0x7a,0x1f,0x2f,0xcd == bset.b $w31, $w5, $w31 # encoding: [0x7a,0x1f,0x2f,0xcd]
0x7a,0x26,0x63,0x8d == bset.h $w14, $w12, $w6 # encoding: [0x7a,0x26,0x63,0x8d]
0x7a,0x4c,0x4f,0xcd == bset.w $w31, $w9, $w12 # encoding: [0x7a,0x4c,0x4f,0xcd]
0x7a,0x65,0xb1,0x4d == bset.d $w5, $w22, $w5 # encoding: [0x7a,0x65,0xb1,0x4d]
0x78,0x12,0xff,0xcf == ceq.b $w31, $w31, $w18 # encoding: [0x78,0x12,0xff,0xcf]
0x78,0x29,0xda,0x8f == ceq.h $w10, $w27, $w9 # encoding: [0x78,0x29,0xda,0x8f]
0x78,0x4e,0x2a,0x4f == ceq.w $w9, $w5, $w14 # encoding: [0x78,0x4e,0x2a,0x4f]
0x78,0x60,0x89,0x4f == ceq.d $w5, $w17, $w0 # encoding: [0x78,0x60,0x89,0x4f]
0x7a,0x09,0x25,0xcf == cle_s.b $w23, $w4, $w9 # encoding: [0x7a,0x09,0x25,0xcf]
0x7a,0x33,0xdd,0x8f == cle_s.h $w22, $w27, $w19 # encoding: [0x7a,0x33,0xdd,0x8f]
0x7a,0x4a,0xd7,0x8f == cle_s.w $w30, $w26, $w10 # encoding: [0x7a,0x4a,0xd7,0x8f]
0x7a,0x6a,0x2c,0x8f == cle_s.d $w18, $w5, $w10 # encoding: [0x7a,0x6a,0x2c,0x8f]
0x7a,0x80,0xc8,0x4f == cle_u.b $w1, $w25, $w0 # encoding: [0x7a,0x80,0xc8,0x4f]
0x7a,0xbd,0x01,0xcf == cle_u.h $w7, $w0, $w29 # encoding: [0x7a,0xbd,0x01,0xcf]
0x7a,0xc1,0x96,0x4f == cle_u.w $w25, $w18, $w1 # encoding: [0x7a,0xc1,0x96,0x4f]
0x7a,0xfe,0x01,0x8f == cle_u.d $w6, $w0, $w30 # encoding: [0x7a,0xfe,0x01,0x8f]
0x79,0x15,0x16,0x4f == clt_s.b $w25, $w2, $w21 # encoding: [0x79,0x15,0x16,0x4f]
0x79,0x29,0x98,0x8f == clt_s.h $w2, $w19, $w9 # encoding: [0x79,0x29,0x98,0x8f]
0x79,0x50,0x45,0xcf == clt_s.w $w23, $w8, $w16 # encoding: [0x79,0x50,0x45,0xcf]
0x79,0x6c,0xf1,0xcf == clt_s.d $w7, $w30, $w12 # encoding: [0x79,0x6c,0xf1,0xcf]
0x79,0x8d,0xf8,0x8f == clt_u.b $w2, $w31, $w13 # encoding: [0x79,0x8d,0xf8,0x8f]
0x79,0xb7,0xfc,0x0f == clt_u.h $w16, $w31, $w23 # encoding: [0x79,0xb7,0xfc,0x0f]
0x79,0xc9,0xc0,0xcf == clt_u.w $w3, $w24, $w9 # encoding: [0x79,0xc9,0xc0,0xcf]
0x79,0xe1,0x01,0xcf == clt_u.d $w7, $w0, $w1 # encoding: [0x79,0xe1,0x01,0xcf]
0x7a,0x12,0x1f,0x52 == div_s.b $w29, $w3, $w18 # encoding: [0x7a,0x12,0x1f,0x52]
0x7a,0x2d,0x84,0x52 == div_s.h $w17, $w16, $w13 # encoding: [0x7a,0x2d,0x84,0x52]
0x7a,0x5e,0xc9,0x12 == div_s.w $w4, $w25, $w30 # encoding: [0x7a,0x5e,0xc9,0x12]
0x7a,0x74,0x4f,0xd2 == div_s.d $w31, $w9, $w20 # encoding: [0x7a,0x74,0x4f,0xd2]
0x7a,0x8a,0xe9,0x92 == div_u.b $w6, $w29, $w10 # encoding: [0x7a,0x8a,0xe9,0x92]
0x7a,0xae,0xae,0x12 == div_u.h $w24, $w21, $w14 # encoding: [0x7a,0xae,0xae,0x12]
0x7a,0xd9,0x77,0x52 == div_u.w $w29, $w14, $w25 # encoding: [0x7a,0xd9,0x77,0x52]
0x7a,0xf5,0x0f,0xd2 == div_u.d $w31, $w1, $w21 # encoding: [0x7a,0xf5,0x0f,0xd2]
0x78,0x39,0xb5,0xd3 == dotp_s.h $w23, $w22, $w25 # encoding: [0x78,0x39,0xb5,0xd3]
0x78,0x45,0x75,0x13 == dotp_s.w $w20, $w14, $w5 # encoding: [0x78,0x45,0x75,0x13]
0x78,0x76,0x14,0x53 == dotp_s.d $w17, $w2, $w22 # encoding: [0x78,0x76,0x14,0x53]
0x78,0xa6,0x13,0x53 == dotp_u.h $w13, $w2, $w6 # encoding: [0x78,0xa6,0x13,0x53]
0x78,0xd5,0xb3,0xd3 == dotp_u.w $w15, $w22, $w21 # encoding: [0x78,0xd5,0xb3,0xd3]
0x78,0xfa,0x81,0x13 == dotp_u.d $w4, $w16, $w26 # encoding: [0x78,0xfa,0x81,0x13]
0x79,0x36,0xe0,0x53 == dpadd_s.h $w1, $w28, $w22 # encoding: [0x79,0x36,0xe0,0x53]
0x79,0x4c,0x0a,0x93 == dpadd_s.w $w10, $w1, $w12 # encoding: [0x79,0x4c,0x0a,0x93]
0x79,0x7b,0xa8,0xd3 == dpadd_s.d $w3, $w21, $w27 # encoding: [0x79,0x7b,0xa8,0xd3]
0x79,0xb4,0x2c,0x53 == dpadd_u.h $w17, $w5, $w20 # encoding: [0x79,0xb4,0x2c,0x53]
0x79,0xd0,0x46,0x13 == dpadd_u.w $w24, $w8, $w16 # encoding: [0x79,0xd0,0x46,0x13]
0x79,0xf0,0xeb,0xd3 == dpadd_u.d $w15, $w29, $w16 # encoding: [0x79,0xf0,0xeb,0xd3]
0x7a,0x2c,0x59,0x13 == dpsub_s.h $w4, $w11, $w12 # encoding: [0x7a,0x2c,0x59,0x13]
0x7a,0x46,0x39,0x13 == dpsub_s.w $w4, $w7, $w6 # encoding: [0x7a,0x46,0x39,0x13]
0x7a,0x7c,0x67,0xd3 == dpsub_s.d $w31, $w12, $w28 # encoding: [0x7a,0x7c,0x67,0xd3]
0x7a,0xb1,0xc9,0x13 == dpsub_u.h $w4, $w25, $w17 # encoding: [0x7a,0xb1,0xc9,0x13]
0x7a,0xd0,0xcc,0xd3 == dpsub_u.w $w19, $w25, $w16 # encoding: [0x7a,0xd0,0xcc,0xd3]
0x7a,0xfa,0x51,0xd3 == dpsub_u.d $w7, $w10, $w26 # encoding: [0x7a,0xfa,0x51,0xd3]
0x7a,0x22,0xc7,0x15 == hadd_s.h $w28, $w24, $w2 # encoding: [0x7a,0x22,0xc7,0x15]
0x7a,0x4b,0x8e,0x15 == hadd_s.w $w24, $w17, $w11 # encoding: [0x7a,0x4b,0x8e,0x15]
0x7a,0x74,0x7c,0x55 == hadd_s.d $w17, $w15, $w20 # encoding: [0x7a,0x74,0x7c,0x55]
0x7a,0xb1,0xeb,0x15 == hadd_u.h $w12, $w29, $w17 # encoding: [0x7a,0xb1,0xeb,0x15]
0x7a,0xc6,0x2a,0x55 == hadd_u.w $w9, $w5, $w6 # encoding: [0x7a,0xc6,0x2a,0x55]
0x7a,0xe6,0xa0,0x55 == hadd_u.d $w1, $w20, $w6 # encoding: [0x7a,0xe6,0xa0,0x55]
0x7b,0x3d,0x74,0x15 == hsub_s.h $w16, $w14, $w29 # encoding: [0x7b,0x3d,0x74,0x15]
0x7b,0x4b,0x6a,0x55 == hsub_s.w $w9, $w13, $w11 # encoding: [0x7b,0x4b,0x6a,0x55]
0x7b,0x6e,0x97,0x95 == hsub_s.d $w30, $w18, $w14 # encoding: [0x7b,0x6e,0x97,0x95]
0x7b,0xae,0x61,0xd5 == hsub_u.h $w7, $w12, $w14 # encoding: [0x7b,0xae,0x61,0xd5]
0x7b,0xc5,0x2d,0x55 == hsub_u.w $w21, $w5, $w5 # encoding: [0x7b,0xc5,0x2d,0x55]
0x7b,0xff,0x62,0xd5 == hsub_u.d $w11, $w12, $w31 # encoding: [0x7b,0xff,0x62,0xd5]
0x7b,0x1e,0x84,0x94 == ilvev.b $w18, $w16, $w30 # encoding: [0x7b,0x1e,0x84,0x94]
0x7b,0x2d,0x03,0x94 == ilvev.h $w14, $w0, $w13 # encoding: [0x7b,0x2d,0x03,0x94]
0x7b,0x56,0xcb,0x14 == ilvev.w $w12, $w25, $w22 # encoding: [0x7b,0x56,0xcb,0x14]
0x7b,0x63,0xdf,0x94 == ilvev.d $w30, $w27, $w3 # encoding: [0x7b,0x63,0xdf,0x94]
0x7a,0x15,0x1f,0x54 == ilvl.b $w29, $w3, $w21 # encoding: [0x7a,0x15,0x1f,0x54]
0x7a,0x31,0x56,0xd4 == ilvl.h $w27, $w10, $w17 # encoding: [0x7a,0x31,0x56,0xd4]
0x7a,0x40,0x09,0x94 == ilvl.w $w6, $w1, $w0 # encoding: [0x7a,0x40,0x09,0x94]
0x7a,0x78,0x80,0xd4 == ilvl.d $w3, $w16, $w24 # encoding: [0x7a,0x78,0x80,0xd4]
0x7b,0x94,0x2a,0xd4 == ilvod.b $w11, $w5, $w20 # encoding: [0x7b,0x94,0x2a,0xd4]
0x7b,0xbf,0x6c,0x94 == ilvod.h $w18, $w13, $w31 # encoding: [0x7b,0xbf,0x6c,0x94]
0x7b,0xd8,0x87,0x54 == ilvod.w $w29, $w16, $w24 # encoding: [0x7b,0xd8,0x87,0x54]
0x7b,0xfd,0x65,0x94 == ilvod.d $w22, $w12, $w29 # encoding: [0x7b,0xfd,0x65,0x94]
0x7a,0x86,0xf1,0x14 == ilvr.b $w4, $w30, $w6 # encoding: [0x7a,0x86,0xf1,0x14]
0x7a,0xbd,0x9f,0x14 == ilvr.h $w28, $w19, $w29 # encoding: [0x7a,0xbd,0x9f,0x14]
0x7a,0xd5,0xa4,0x94 == ilvr.w $w18, $w20, $w21 # encoding: [0x7a,0xd5,0xa4,0x94]
0x7a,0xec,0xf5,0xd4 == ilvr.d $w23, $w30, $w12 # encoding: [0x7a,0xec,0xf5,0xd4]
0x78,0x9d,0xfc,0x52 == maddv.b $w17, $w31, $w29 # encoding: [0x78,0x9d,0xfc,0x52]
0x78,0xa9,0xc1,0xd2 == maddv.h $w7, $w24, $w9 # encoding: [0x78,0xa9,0xc1,0xd2]
0x78,0xd4,0xb5,0x92 == maddv.w $w22, $w22, $w20 # encoding: [0x78,0xd4,0xb5,0x92]
0x78,0xf4,0xd7,0x92 == maddv.d $w30, $w26, $w20 # encoding: [0x78,0xf4,0xd7,0x92]
0x7b,0x17,0x5d,0xce == max_a.b $w23, $w11, $w23 # encoding: [0x7b,0x17,0x5d,0xce]
0x7b,0x3e,0x2d,0x0e == max_a.h $w20, $w5, $w30 # encoding: [0x7b,0x3e,0x2d,0x0e]
0x7b,0x5e,0x91,0xce == max_a.w $w7, $w18, $w30 # encoding: [0x7b,0x5e,0x91,0xce]
0x7b,0x7f,0x42,0x0e == max_a.d $w8, $w8, $w31 # encoding: [0x7b,0x7f,0x42,0x0e]
0x79,0x13,0x0a,0x8e == max_s.b $w10, $w1, $w19 # encoding: [0x79,0x13,0x0a,0x8e]
0x79,0x31,0xeb,0xce == max_s.h $w15, $w29, $w17 # encoding: [0x79,0x31,0xeb,0xce]
0x79,0x4e,0xeb,0xce == max_s.w $w15, $w29, $w14 # encoding: [0x79,0x4e,0xeb,0xce]
0x79,0x63,0xc6,0x4e == max_s.d $w25, $w24, $w3 # encoding: [0x79,0x63,0xc6,0x4e]
0x79,0x85,0xc3,0x0e == max_u.b $w12, $w24, $w5 # encoding: [0x79,0x85,0xc3,0x0e]
0x79,0xa7,0x31,0x4e == max_u.h $w5, $w6, $w7 # encoding: [0x79,0xa7,0x31,0x4e]
0x79,0xc7,0x24,0x0e == max_u.w $w16, $w4, $w7 # encoding: [0x79,0xc7,0x24,0x0e]
0x79,0xf8,0x66,0x8e == max_u.d $w26, $w12, $w24 # encoding: [0x79,0xf8,0x66,0x8e]
0x7b,0x81,0xd1,0x0e == min_a.b $w4, $w26, $w1 # encoding: [0x7b,0x81,0xd1,0x0e]
0x7b,0xbf,0x6b,0x0e == min_a.h $w12, $w13, $w31 # encoding: [0x7b,0xbf,0x6b,0x0e]
0x7b,0xc0,0xa7,0x0e == min_a.w $w28, $w20, $w0 # encoding: [0x7b,0xc0,0xa7,0x0e]
0x7b,0xf3,0xa3,0x0e == min_a.d $w12, $w20, $w19 # encoding: [0x7b,0xf3,0xa3,0x0e]
0x7a,0x0e,0x1c,0xce == min_s.b $w19, $w3, $w14 # encoding: [0x7a,0x0e,0x1c,0xce]
0x7a,0x28,0xae,0xce == min_s.h $w27, $w21, $w8 # encoding: [0x7a,0x28,0xae,0xce]
0x7a,0x5e,0x70,0x0e == min_s.w $w0, $w14, $w30 # encoding: [0x7a,0x5e,0x70,0x0e]
0x7a,0x75,0x41,0x8e == min_s.d $w6, $w8, $w21 # encoding: [0x7a,0x75,0x41,0x8e]
0x7a,0x88,0xd5,0x8e == min_u.b $w22, $w26, $w8 # encoding: [0x7a,0x88,0xd5,0x8e]
0x7a,0xac,0xd9,0xce == min_u.h $w7, $w27, $w12 # encoding: [0x7a,0xac,0xd9,0xce]
0x7a,0xce,0xa2,0x0e == min_u.w $w8, $w20, $w14 # encoding: [0x7a,0xce,0xa2,0x0e]
0x7a,0xef,0x76,0x8e == min_u.d $w26, $w14, $w15 # encoding: [0x7a,0xef,0x76,0x8e]
0x7b,0x1a,0x0c,0x92 == mod_s.b $w18, $w1, $w26 # encoding: [0x7b,0x1a,0x0c,0x92]
0x7b,0x3c,0xf7,0xd2 == mod_s.h $w31, $w30, $w28 # encoding: [0x7b,0x3c,0xf7,0xd2]
0x7b,0x4d,0x30,0x92 == mod_s.w $w2, $w6, $w13 # encoding: [0x7b,0x4d,0x30,0x92]
0x7b,0x76,0xdd,0x52 == mod_s.d $w21, $w27, $w22 # encoding: [0x7b,0x76,0xdd,0x52]
0x7b,0x8d,0x3c,0x12 == mod_u.b $w16, $w7, $w13 # encoding: [0x7b,0x8d,0x3c,0x12]
0x7b,0xa7,0x46,0x12 == mod_u.h $w24, $w8, $w7 # encoding: [0x7b,0xa7,0x46,0x12]
0x7b,0xd1,0x17,0x92 == mod_u.w $w30, $w2, $w17 # encoding: [0x7b,0xd1,0x17,0x92]
0x7b,0xf9,0x17,0xd2 == mod_u.d $w31, $w2, $w25 # encoding: [0x7b,0xf9,0x17,0xd2]
0x79,0x0c,0x2b,0x92 == msubv.b $w14, $w5, $w12 # encoding: [0x79,0x0c,0x2b,0x92]
0x79,0x3e,0x39,0x92 == msubv.h $w6, $w7, $w30 # encoding: [0x79,0x3e,0x39,0x92]
0x79,0x55,0x13,0x52 == msubv.w $w13, $w2, $w21 # encoding: [0x79,0x55,0x13,0x52]
0x79,0x7b,0x74,0x12 == msubv.d $w16, $w14, $w27 # encoding: [0x79,0x7b,0x74,0x12]
0x78,0x0d,0x1d,0x12 == mulv.b $w20, $w3, $w13 # encoding: [0x78,0x0d,0x1d,0x12]
0x78,0x2e,0xd6,0xd2 == mulv.h $w27, $w26, $w14 # encoding: [0x78,0x2e,0xd6,0xd2]
0x78,0x43,0xea,0x92 == mulv.w $w10, $w29, $w3 # encoding: [0x78,0x43,0xea,0x92]
0x78,0x7d,0x99,0xd2 == mulv.d $w7, $w19, $w29 # encoding: [0x78,0x7d,0x99,0xd2]
0x79,0x07,0xd9,0x54 == pckev.b $w5, $w27, $w7 # encoding: [0x79,0x07,0xd9,0x54]
0x79,0x3b,0x20,0x54 == pckev.h $w1, $w4, $w27 # encoding: [0x79,0x3b,0x20,0x54]
0x79,0x40,0xa7,0x94 == pckev.w $w30, $w20, $w0 # encoding: [0x79,0x40,0xa7,0x94]
0x79,0x6f,0x09,0x94 == pckev.d $w6, $w1, $w15 # encoding: [0x79,0x6f,0x09,0x94]
0x79,0x9e,0xe4,0x94 == pckod.b $w18, $w28, $w30 # encoding: [0x79,0x9e,0xe4,0x94]
0x79,0xa8,0x2e,0x94 == pckod.h $w26, $w5, $w8 # encoding: [0x79,0xa8,0x2e,0x94]
0x79,0xc2,0x22,0x54 == pckod.w $w9, $w4, $w2 # encoding: [0x79,0xc2,0x22,0x54]
0x79,0xf4,0xb7,0x94 == pckod.d $w30, $w22, $w20 # encoding: [0x79,0xf4,0xb7,0x94]
0x78,0x0c,0xb9,0x54 == sld.b $w5, $w23[$12] # encoding: [0x78,0x0c,0xb9,0x54]
0x78,0x23,0xb8,0x54 == sld.h $w1, $w23[$3] # encoding: [0x78,0x23,0xb8,0x54]
0x78,0x49,0x45,0x14 == sld.w $w20, $w8[$9] # encoding: [0x78,0x49,0x45,0x14]
0x78,0x7e,0xb9,0xd4 == sld.d $w7, $w23[$fp] # encoding: [0x78,0x7e,0xb9,0xd4]
0x78,0x11,0x00,0xcd == sll.b $w3, $w0, $w17 # encoding: [0x78,0x11,0x00,0xcd]
0x78,0x23,0xdc,0x4d == sll.h $w17, $w27, $w3 # encoding: [0x78,0x23,0xdc,0x4d]
0x78,0x46,0x3c,0x0d == sll.w $w16, $w7, $w6 # encoding: [0x78,0x46,0x3c,0x0d]
0x78,0x7a,0x02,0x4d == sll.d $w9, $w0, $w26 # encoding: [0x78,0x7a,0x02,0x4d]
0x78,0x81,0x0f,0x14 == splat.b $w28, $w1[$1] # encoding: [0x78,0x81,0x0f,0x14]
0x78,0xab,0x58,0x94 == splat.h $w2, $w11[$11] # encoding: [0x78,0xab,0x58,0x94]
0x78,0xcb,0x05,0x94 == splat.w $w22, $w0[$11] # encoding: [0x78,0xcb,0x05,0x94]
0x78,0xe2,0x00,0x14 == splat.d $w0, $w0[$2] # encoding: [0x78,0xe2,0x00,0x14]
0x78,0x91,0x27,0x0d == sra.b $w28, $w4, $w17 # encoding: [0x78,0x91,0x27,0x0d]
0x78,0xa3,0x4b,0x4d == sra.h $w13, $w9, $w3 # encoding: [0x78,0xa3,0x4b,0x4d]
0x78,0xd3,0xae,0xcd == sra.w $w27, $w21, $w19 # encoding: [0x78,0xd3,0xae,0xcd]
0x78,0xf7,0x47,0x8d == sra.d $w30, $w8, $w23 # encoding: [0x78,0xf7,0x47,0x8d]
0x78,0x92,0x94,0xd5 == srar.b $w19, $w18, $w18 # encoding: [0x78,0x92,0x94,0xd5]
0x78,0xa8,0xb9,0xd5 == srar.h $w7, $w23, $w8 # encoding: [0x78,0xa8,0xb9,0xd5]
0x78,0xc2,0x60,0x55 == srar.w $w1, $w12, $w2 # encoding: [0x78,0xc2,0x60,0x55]
0x78,0xee,0x3d,0x55 == srar.d $w21, $w7, $w14 # encoding: [0x78,0xee,0x3d,0x55]
0x79,0x13,0x1b,0x0d == srl.b $w12, $w3, $w19 # encoding: [0x79,0x13,0x1b,0x0d]
0x79,0x34,0xfd,0xcd == srl.h $w23, $w31, $w20 # encoding: [0x79,0x34,0xfd,0xcd]
0x79,0x4b,0xdc,0x8d == srl.w $w18, $w27, $w11 # encoding: [0x79,0x4b,0xdc,0x8d]
0x79,0x7a,0x60,0xcd == srl.d $w3, $w12, $w26 # encoding: [0x79,0x7a,0x60,0xcd]
0x79,0x0b,0xab,0xd5 == srlr.b $w15, $w21, $w11 # encoding: [0x79,0x0b,0xab,0xd5]
0x79,0x33,0x6d,0x55 == srlr.h $w21, $w13, $w19 # encoding: [0x79,0x33,0x6d,0x55]
0x79,0x43,0xf1,0x95 == srlr.w $w6, $w30, $w3 # encoding: [0x79,0x43,0xf1,0x95]
0x79,0x6e,0x10,0x55 == srlr.d $w1, $w2, $w14 # encoding: [0x79,0x6e,0x10,0x55]
0x78,0x01,0x7e,0x51 == subs_s.b $w25, $w15, $w1 # encoding: [0x78,0x01,0x7e,0x51]
0x78,0x36,0xcf,0x11 == subs_s.h $w28, $w25, $w22 # encoding: [0x78,0x36,0xcf,0x11]
0x78,0x55,0x62,0x91 == subs_s.w $w10, $w12, $w21 # encoding: [0x78,0x55,0x62,0x91]
0x78,0x72,0xa1,0x11 == subs_s.d $w4, $w20, $w18 # encoding: [0x78,0x72,0xa1,0x11]
0x78,0x99,0x35,0x51 == subs_u.b $w21, $w6, $w25 # encoding: [0x78,0x99,0x35,0x51]
0x78,0xa7,0x50,0xd1 == subs_u.h $w3, $w10, $w7 # encoding: [0x78,0xa7,0x50,0xd1]
0x78,0xca,0x7a,0x51 == subs_u.w $w9, $w15, $w10 # encoding: [0x78,0xca,0x7a,0x51]
0x78,0xea,0x99,0xd1 == subs_u.d $w7, $w19, $w10 # encoding: [0x78,0xea,0x99,0xd1]
0x79,0x0c,0x39,0x91 == subsus_u.b $w6, $w7, $w12 # encoding: [0x79,0x0c,0x39,0x91]
0x79,0x33,0xe9,0x91 == subsus_u.h $w6, $w29, $w19 # encoding: [0x79,0x33,0xe9,0x91]
0x79,0x47,0x79,0xd1 == subsus_u.w $w7, $w15, $w7 # encoding: [0x79,0x47,0x79,0xd1]
0x79,0x6f,0x1a,0x51 == subsus_u.d $w9, $w3, $w15 # encoding: [0x79,0x6f,0x1a,0x51]
0x79,0x9f,0x1d,0x91 == subsuu_s.b $w22, $w3, $w31 # encoding: [0x79,0x9f,0x1d,0x91]
0x79,0xb6,0xbc,0xd1 == subsuu_s.h $w19, $w23, $w22 # encoding: [0x79,0xb6,0xbc,0xd1]
0x79,0xcd,0x52,0x51 == subsuu_s.w $w9, $w10, $w13 # encoding: [0x79,0xcd,0x52,0x51]
0x79,0xe0,0x31,0x51 == subsuu_s.d $w5, $w6, $w0 # encoding: [0x79,0xe0,0x31,0x51]
0x78,0x93,0x69,0x8e == subv.b $w6, $w13, $w19 # encoding: [0x78,0x93,0x69,0x8e]
0x78,0xac,0xc9,0x0e == subv.h $w4, $w25, $w12 # encoding: [0x78,0xac,0xc9,0x0e]
0x78,0xcb,0xde,0xce == subv.w $w27, $w27, $w11 # encoding: [0x78,0xcb,0xde,0xce]
0x78,0xea,0xc2,0x4e == subv.d $w9, $w24, $w10 # encoding: [0x78,0xea,0xc2,0x4e]
0x78,0x05,0x80,0xd5 == vshf.b $w3, $w16, $w5 # encoding: [0x78,0x05,0x80,0xd5]
0x78,0x28,0x9d,0x15 == vshf.h $w20, $w19, $w8 # encoding: [0x78,0x28,0x9d,0x15]
0x78,0x59,0xf4,0x15 == vshf.w $w16, $w30, $w25 # encoding: [0x78,0x59,0xf4,0x15]
0x78,0x6f,0x5c,0xd5 == vshf.d $w19, $w11, $w15 # encoding: [0x78,0x6f,0x5c,0xd5]

165
suite/MC/Mips/test_3rf.s.cs
View File

@ -1,83 +1,84 @@
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
0x78,0x1c,0x9f,0x1b = fadd.w $w28, $w19, $w28
0x78,0x3d,0x13,0x5b = fadd.d $w13, $w2, $w29
0x78,0x19,0x5b,0x9a = fcaf.w $w14, $w11, $w25
0x78,0x33,0x08,0x5a = fcaf.d $w1, $w1, $w19
0x78,0x90,0xb8,0x5a = fceq.w $w1, $w23, $w16
0x78,0xb0,0x40,0x1a = fceq.d $w0, $w8, $w16
0x79,0x98,0x4c,0x1a = fcle.w $w16, $w9, $w24
0x79,0xa1,0x76,0xda = fcle.d $w27, $w14, $w1
0x79,0x08,0x47,0x1a = fclt.w $w28, $w8, $w8
0x79,0x2b,0xcf,0x9a = fclt.d $w30, $w25, $w11
0x78,0xd7,0x90,0x9c = fcne.w $w2, $w18, $w23
0x78,0xef,0xa3,0x9c = fcne.d $w14, $w20, $w15
0x78,0x59,0x92,0x9c = fcor.w $w10, $w18, $w25
0x78,0x6b,0xcc,0x5c = fcor.d $w17, $w25, $w11
0x78,0xd5,0x13,0x9a = fcueq.w $w14, $w2, $w21
0x78,0xe7,0x1f,0x5a = fcueq.d $w29, $w3, $w7
0x79,0xc3,0x2c,0x5a = fcule.w $w17, $w5, $w3
0x79,0xfe,0x0f,0xda = fcule.d $w31, $w1, $w30
0x79,0x49,0xc9,0x9a = fcult.w $w6, $w25, $w9
0x79,0x71,0x46,0xda = fcult.d $w27, $w8, $w17
0x78,0x48,0xa1,0x1a = fcun.w $w4, $w20, $w8
0x78,0x63,0x5f,0x5a = fcun.d $w29, $w11, $w3
0x78,0x93,0x93,0x5c = fcune.w $w13, $w18, $w19
0x78,0xb5,0xd4,0x1c = fcune.d $w16, $w26, $w21
0x78,0xc2,0xc3,0x5b = fdiv.w $w13, $w24, $w2
0x78,0xf9,0x24,0xdb = fdiv.d $w19, $w4, $w25
0x7a,0x10,0x02,0x1b = fexdo.h $w8, $w0, $w16
0x7a,0x3b,0x68,0x1b = fexdo.w $w0, $w13, $w27
0x79,0xc3,0x04,0x5b = fexp2.w $w17, $w0, $w3
0x79,0xea,0x05,0x9b = fexp2.d $w22, $w0, $w10
0x79,0x17,0x37,0x5b = fmadd.w $w29, $w6, $w23
0x79,0x35,0xe2,0xdb = fmadd.d $w11, $w28, $w21
0x7b,0x8d,0xb8,0x1b = fmax.w $w0, $w23, $w13
0x7b,0xa8,0x96,0x9b = fmax.d $w26, $w18, $w8
0x7b,0xca,0x82,0x9b = fmax_a.w $w10, $w16, $w10
0x7b,0xf6,0x4f,0x9b = fmax_a.d $w30, $w9, $w22
0x7b,0x1e,0x0e,0x1b = fmin.w $w24, $w1, $w30
0x7b,0x2a,0xde,0xdb = fmin.d $w27, $w27, $w10
0x7b,0x54,0xea,0x9b = fmin_a.w $w10, $w29, $w20
0x7b,0x78,0xf3,0x5b = fmin_a.d $w13, $w30, $w24
0x79,0x40,0xcc,0x5b = fmsub.w $w17, $w25, $w0
0x79,0x70,0x92,0x1b = fmsub.d $w8, $w18, $w16
0x78,0x8f,0x78,0xdb = fmul.w $w3, $w15, $w15
0x78,0xaa,0xf2,0x5b = fmul.d $w9, $w30, $w10
0x7a,0x0a,0x2e,0x5a = fsaf.w $w25, $w5, $w10
0x7a,0x3d,0x1e,0x5a = fsaf.d $w25, $w3, $w29
0x7a,0x8d,0x8a,0xda = fseq.w $w11, $w17, $w13
0x7a,0xbf,0x07,0x5a = fseq.d $w29, $w0, $w31
0x7b,0x9f,0xff,0x9a = fsle.w $w30, $w31, $w31
0x7b,0xb8,0xbc,0x9a = fsle.d $w18, $w23, $w24
0x7b,0x06,0x2b,0x1a = fslt.w $w12, $w5, $w6
0x7b,0x35,0xd4,0x1a = fslt.d $w16, $w26, $w21
0x7a,0xcc,0x0f,0x9c = fsne.w $w30, $w1, $w12
0x7a,0xf7,0x6b,0x9c = fsne.d $w14, $w13, $w23
0x7a,0x5b,0x6e,0xdc = fsor.w $w27, $w13, $w27
0x7a,0x6b,0xc3,0x1c = fsor.d $w12, $w24, $w11
0x78,0x41,0xd7,0xdb = fsub.w $w31, $w26, $w1
0x78,0x7b,0x8c,0xdb = fsub.d $w19, $w17, $w27
0x7a,0xd9,0xc4,0x1a = fsueq.w $w16, $w24, $w25
0x7a,0xee,0x74,0x9a = fsueq.d $w18, $w14, $w14
0x7b,0xcd,0xf5,0xda = fsule.w $w23, $w30, $w13
0x7b,0xfa,0x58,0x9a = fsule.d $w2, $w11, $w26
0x7b,0x56,0xd2,0xda = fsult.w $w11, $w26, $w22
0x7b,0x7e,0xb9,0x9a = fsult.d $w6, $w23, $w30
0x7a,0x5c,0x90,0xda = fsun.w $w3, $w18, $w28
0x7a,0x73,0x5c,0x9a = fsun.d $w18, $w11, $w19
0x7a,0x82,0xfc,0x1c = fsune.w $w16, $w31, $w2
0x7a,0xb1,0xd0,0xdc = fsune.d $w3, $w26, $w17
0x7a,0x98,0x24,0x1b = ftq.h $w16, $w4, $w24
0x7a,0xb9,0x29,0x5b = ftq.w $w5, $w5, $w25
0x79,0x4a,0xa4,0x1c = madd_q.h $w16, $w20, $w10
0x79,0x69,0x17,0x1c = madd_q.w $w28, $w2, $w9
0x7b,0x49,0x92,0x1c = maddr_q.h $w8, $w18, $w9
0x7b,0x70,0x67,0x5c = maddr_q.w $w29, $w12, $w16
0x79,0x8a,0xd6,0x1c = msub_q.h $w24, $w26, $w10
0x79,0xbc,0xf3,0x5c = msub_q.w $w13, $w30, $w28
0x7b,0x8b,0xab,0x1c = msubr_q.h $w12, $w21, $w11
0x7b,0xb4,0x70,0x5c = msubr_q.w $w1, $w14, $w20
0x79,0x1e,0x81,0x9c = mul_q.h $w6, $w16, $w30
0x79,0x24,0x0c,0x1c = mul_q.w $w16, $w1, $w4
0x7b,0x13,0xa1,0x9c = mulr_q.h $w6, $w20, $w19
0x7b,0x34,0x0e,0xdc = mulr_q.w $w27, $w1, $w20
0x78,0x1c,0x9f,0x1b == fadd.w $w28, $w19, $w28 # encoding: [0x78,0x1c,0x9f,0x1b]
0x78,0x3d,0x13,0x5b == fadd.d $w13, $w2, $w29 # encoding: [0x78,0x3d,0x13,0x5b]
0x78,0x19,0x5b,0x9a == fcaf.w $w14, $w11, $w25 # encoding: [0x78,0x19,0x5b,0x9a]
0x78,0x33,0x08,0x5a == fcaf.d $w1, $w1, $w19 # encoding: [0x78,0x33,0x08,0x5a]
0x78,0x90,0xb8,0x5a == fceq.w $w1, $w23, $w16 # encoding: [0x78,0x90,0xb8,0x5a]
0x78,0xb0,0x40,0x1a == fceq.d $w0, $w8, $w16 # encoding: [0x78,0xb0,0x40,0x1a]
0x79,0x98,0x4c,0x1a == fcle.w $w16, $w9, $w24 # encoding: [0x79,0x98,0x4c,0x1a]
0x79,0xa1,0x76,0xda == fcle.d $w27, $w14, $w1 # encoding: [0x79,0xa1,0x76,0xda]
0x79,0x08,0x47,0x1a == fclt.w $w28, $w8, $w8 # encoding: [0x79,0x08,0x47,0x1a]
0x79,0x2b,0xcf,0x9a == fclt.d $w30, $w25, $w11 # encoding: [0x79,0x2b,0xcf,0x9a]
0x78,0xd7,0x90,0x9c == fcne.w $w2, $w18, $w23 # encoding: [0x78,0xd7,0x90,0x9c]
0x78,0xef,0xa3,0x9c == fcne.d $w14, $w20, $w15 # encoding: [0x78,0xef,0xa3,0x9c]
0x78,0x59,0x92,0x9c == fcor.w $w10, $w18, $w25 # encoding: [0x78,0x59,0x92,0x9c]
0x78,0x6b,0xcc,0x5c == fcor.d $w17, $w25, $w11 # encoding: [0x78,0x6b,0xcc,0x5c]
0x78,0xd5,0x13,0x9a == fcueq.w $w14, $w2, $w21 # encoding: [0x78,0xd5,0x13,0x9a]
0x78,0xe7,0x1f,0x5a == fcueq.d $w29, $w3, $w7 # encoding: [0x78,0xe7,0x1f,0x5a]
0x79,0xc3,0x2c,0x5a == fcule.w $w17, $w5, $w3 # encoding: [0x79,0xc3,0x2c,0x5a]
0x79,0xfe,0x0f,0xda == fcule.d $w31, $w1, $w30 # encoding: [0x79,0xfe,0x0f,0xda]
0x79,0x49,0xc9,0x9a == fcult.w $w6, $w25, $w9 # encoding: [0x79,0x49,0xc9,0x9a]
0x79,0x71,0x46,0xda == fcult.d $w27, $w8, $w17 # encoding: [0x79,0x71,0x46,0xda]
0x78,0x48,0xa1,0x1a == fcun.w $w4, $w20, $w8 # encoding: [0x78,0x48,0xa1,0x1a]
0x78,0x63,0x5f,0x5a == fcun.d $w29, $w11, $w3 # encoding: [0x78,0x63,0x5f,0x5a]
0x78,0x93,0x93,0x5c == fcune.w $w13, $w18, $w19 # encoding: [0x78,0x93,0x93,0x5c]
0x78,0xb5,0xd4,0x1c == fcune.d $w16, $w26, $w21 # encoding: [0x78,0xb5,0xd4,0x1c]
0x78,0xc2,0xc3,0x5b == fdiv.w $w13, $w24, $w2 # encoding: [0x78,0xc2,0xc3,0x5b]
0x78,0xf9,0x24,0xdb == fdiv.d $w19, $w4, $w25 # encoding: [0x78,0xf9,0x24,0xdb]
0x7a,0x10,0x02,0x1b == fexdo.h $w8, $w0, $w16 # encoding: [0x7a,0x10,0x02,0x1b]
0x7a,0x3b,0x68,0x1b == fexdo.w $w0, $w13, $w27 # encoding: [0x7a,0x3b,0x68,0x1b]
0x79,0xc3,0x04,0x5b == fexp2.w $w17, $w0, $w3 # encoding: [0x79,0xc3,0x04,0x5b]
0x79,0xea,0x05,0x9b == fexp2.d $w22, $w0, $w10 # encoding: [0x79,0xea,0x05,0x9b]
0x79,0x17,0x37,0x5b == fmadd.w $w29, $w6, $w23 # encoding: [0x79,0x17,0x37,0x5b]
0x79,0x35,0xe2,0xdb == fmadd.d $w11, $w28, $w21 # encoding: [0x79,0x35,0xe2,0xdb]
0x7b,0x8d,0xb8,0x1b == fmax.w $w0, $w23, $w13 # encoding: [0x7b,0x8d,0xb8,0x1b]
0x7b,0xa8,0x96,0x9b == fmax.d $w26, $w18, $w8 # encoding: [0x7b,0xa8,0x96,0x9b]
0x7b,0xca,0x82,0x9b == fmax_a.w $w10, $w16, $w10 # encoding: [0x7b,0xca,0x82,0x9b]
0x7b,0xf6,0x4f,0x9b == fmax_a.d $w30, $w9, $w22 # encoding: [0x7b,0xf6,0x4f,0x9b]
0x7b,0x1e,0x0e,0x1b == fmin.w $w24, $w1, $w30 # encoding: [0x7b,0x1e,0x0e,0x1b]
0x7b,0x2a,0xde,0xdb == fmin.d $w27, $w27, $w10 # encoding: [0x7b,0x2a,0xde,0xdb]
0x7b,0x54,0xea,0x9b == fmin_a.w $w10, $w29, $w20 # encoding: [0x7b,0x54,0xea,0x9b]
0x7b,0x78,0xf3,0x5b == fmin_a.d $w13, $w30, $w24 # encoding: [0x7b,0x78,0xf3,0x5b]
0x79,0x40,0xcc,0x5b == fmsub.w $w17, $w25, $w0 # encoding: [0x79,0x40,0xcc,0x5b]
0x79,0x70,0x92,0x1b == fmsub.d $w8, $w18, $w16 # encoding: [0x79,0x70,0x92,0x1b]
0x78,0x8f,0x78,0xdb == fmul.w $w3, $w15, $w15 # encoding: [0x78,0x8f,0x78,0xdb]
0x78,0xaa,0xf2,0x5b == fmul.d $w9, $w30, $w10 # encoding: [0x78,0xaa,0xf2,0x5b]
0x7a,0x0a,0x2e,0x5a == fsaf.w $w25, $w5, $w10 # encoding: [0x7a,0x0a,0x2e,0x5a]
0x7a,0x3d,0x1e,0x5a == fsaf.d $w25, $w3, $w29 # encoding: [0x7a,0x3d,0x1e,0x5a]
0x7a,0x8d,0x8a,0xda == fseq.w $w11, $w17, $w13 # encoding: [0x7a,0x8d,0x8a,0xda]
0x7a,0xbf,0x07,0x5a == fseq.d $w29, $w0, $w31 # encoding: [0x7a,0xbf,0x07,0x5a]
0x7b,0x9f,0xff,0x9a == fsle.w $w30, $w31, $w31 # encoding: [0x7b,0x9f,0xff,0x9a]
0x7b,0xb8,0xbc,0x9a == fsle.d $w18, $w23, $w24 # encoding: [0x7b,0xb8,0xbc,0x9a]
0x7b,0x06,0x2b,0x1a == fslt.w $w12, $w5, $w6 # encoding: [0x7b,0x06,0x2b,0x1a]
0x7b,0x35,0xd4,0x1a == fslt.d $w16, $w26, $w21 # encoding: [0x7b,0x35,0xd4,0x1a]
0x7a,0xcc,0x0f,0x9c == fsne.w $w30, $w1, $w12 # encoding: [0x7a,0xcc,0x0f,0x9c]
0x7a,0xf7,0x6b,0x9c == fsne.d $w14, $w13, $w23 # encoding: [0x7a,0xf7,0x6b,0x9c]
0x7a,0x5b,0x6e,0xdc == fsor.w $w27, $w13, $w27 # encoding: [0x7a,0x5b,0x6e,0xdc]
0x7a,0x6b,0xc3,0x1c == fsor.d $w12, $w24, $w11 # encoding: [0x7a,0x6b,0xc3,0x1c]
0x78,0x41,0xd7,0xdb == fsub.w $w31, $w26, $w1 # encoding: [0x78,0x41,0xd7,0xdb]
0x78,0x7b,0x8c,0xdb == fsub.d $w19, $w17, $w27 # encoding: [0x78,0x7b,0x8c,0xdb]
0x7a,0xd9,0xc4,0x1a == fsueq.w $w16, $w24, $w25 # encoding: [0x7a,0xd9,0xc4,0x1a]
0x7a,0xee,0x74,0x9a == fsueq.d $w18, $w14, $w14 # encoding: [0x7a,0xee,0x74,0x9a]
0x7b,0xcd,0xf5,0xda == fsule.w $w23, $w30, $w13 # encoding: [0x7b,0xcd,0xf5,0xda]
0x7b,0xfa,0x58,0x9a == fsule.d $w2, $w11, $w26 # encoding: [0x7b,0xfa,0x58,0x9a]
0x7b,0x56,0xd2,0xda == fsult.w $w11, $w26, $w22 # encoding: [0x7b,0x56,0xd2,0xda]
0x7b,0x7e,0xb9,0x9a == fsult.d $w6, $w23, $w30 # encoding: [0x7b,0x7e,0xb9,0x9a]
0x7a,0x5c,0x90,0xda == fsun.w $w3, $w18, $w28 # encoding: [0x7a,0x5c,0x90,0xda]
0x7a,0x73,0x5c,0x9a == fsun.d $w18, $w11, $w19 # encoding: [0x7a,0x73,0x5c,0x9a]
0x7a,0x82,0xfc,0x1c == fsune.w $w16, $w31, $w2 # encoding: [0x7a,0x82,0xfc,0x1c]
0x7a,0xb1,0xd0,0xdc == fsune.d $w3, $w26, $w17 # encoding: [0x7a,0xb1,0xd0,0xdc]
0x7a,0x98,0x24,0x1b == ftq.h $w16, $w4, $w24 # encoding: [0x7a,0x98,0x24,0x1b]
0x7a,0xb9,0x29,0x5b == ftq.w $w5, $w5, $w25 # encoding: [0x7a,0xb9,0x29,0x5b]
0x79,0x4a,0xa4,0x1c == madd_q.h $w16, $w20, $w10 # encoding: [0x79,0x4a,0xa4,0x1c]
0x79,0x69,0x17,0x1c == madd_q.w $w28, $w2, $w9 # encoding: [0x79,0x69,0x17,0x1c]
0x7b,0x49,0x92,0x1c == maddr_q.h $w8, $w18, $w9 # encoding: [0x7b,0x49,0x92,0x1c]
0x7b,0x70,0x67,0x5c == maddr_q.w $w29, $w12, $w16 # encoding: [0x7b,0x70,0x67,0x5c]
0x79,0x8a,0xd6,0x1c == msub_q.h $w24, $w26, $w10 # encoding: [0x79,0x8a,0xd6,0x1c]
0x79,0xbc,0xf3,0x5c == msub_q.w $w13, $w30, $w28 # encoding: [0x79,0xbc,0xf3,0x5c]
0x7b,0x8b,0xab,0x1c == msubr_q.h $w12, $w21, $w11 # encoding: [0x7b,0x8b,0xab,0x1c]
0x7b,0xb4,0x70,0x5c == msubr_q.w $w1, $w14, $w20 # encoding: [0x7b,0xb4,0x70,0x5c]
0x79,0x1e,0x81,0x9c == mul_q.h $w6, $w16, $w30 # encoding: [0x79,0x1e,0x81,0x9c]
0x79,0x24,0x0c,0x1c == mul_q.w $w16, $w1, $w4 # encoding: [0x79,0x24,0x0c,0x1c]
0x7b,0x13,0xa1,0x9c == mulr_q.h $w6, $w20, $w19 # encoding: [0x7b,0x13,0xa1,0x9c]
0x7b,0x34,0x0e,0xdc == mulr_q.w $w27, $w1, $w20 # encoding: [0x7b,0x34,0x0e,0xdc]

97
suite/MC/Mips/test_bit.s.cs
View File

@ -1,49 +1,50 @@
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
0x79,0xf2,0xf5,0x49 = bclri.b $w21, $w30, 2
0x79,0xe0,0xae,0x09 = bclri.h $w24, $w21, 0
0x79,0xc3,0xf5,0xc9 = bclri.w $w23, $w30, 3
0x79,0x80,0x5a,0x49 = bclri.d $w9, $w11, 0
0x7b,0x71,0x66,0x49 = binsli.b $w25, $w12, 1
0x7b,0x60,0xb5,0x49 = binsli.h $w21, $w22, 0
0x7b,0x40,0x25,0x89 = binsli.w $w22, $w4, 0
0x7b,0x06,0x11,0x89 = binsli.d $w6, $w2, 6
0x7b,0xf0,0x9b,0xc9 = binsri.b $w15, $w19, 0
0x7b,0xe1,0xf2,0x09 = binsri.h $w8, $w30, 1
0x7b,0xc5,0x98,0x89 = binsri.w $w2, $w19, 5
0x7b,0x81,0xa4,0x89 = binsri.d $w18, $w20, 1
0x7a,0xf0,0x9e,0x09 = bnegi.b $w24, $w19, 0
0x7a,0xe3,0x5f,0x09 = bnegi.h $w28, $w11, 3
0x7a,0xc5,0xd8,0x49 = bnegi.w $w1, $w27, 5
0x7a,0x81,0xa9,0x09 = bnegi.d $w4, $w21, 1
0x7a,0x70,0x44,0x89 = bseti.b $w18, $w8, 0
0x7a,0x62,0x76,0x09 = bseti.h $w24, $w14, 2
0x7a,0x44,0x92,0x49 = bseti.w $w9, $w18, 4
0x7a,0x01,0x79,0xc9 = bseti.d $w7, $w15, 1
0x78,0x72,0xff,0xca = sat_s.b $w31, $w31, 2
0x78,0x60,0x9c,0xca = sat_s.h $w19, $w19, 0
0x78,0x40,0xec,0xca = sat_s.w $w19, $w29, 0
0x78,0x00,0xb2,0xca = sat_s.d $w11, $w22, 0
0x78,0xf3,0x68,0x4a = sat_u.b $w1, $w13, 3
0x78,0xe4,0xc7,0x8a = sat_u.h $w30, $w24, 4
0x78,0xc0,0x6f,0xca = sat_u.w $w31, $w13, 0
0x78,0x85,0x87,0x4a = sat_u.d $w29, $w16, 5
0x78,0x71,0x55,0xc9 = slli.b $w23, $w10, 1
0x78,0x61,0x92,0x49 = slli.h $w9, $w18, 1
0x78,0x44,0xea,0xc9 = slli.w $w11, $w29, 4
0x78,0x01,0xa6,0x49 = slli.d $w25, $w20, 1
0x78,0xf1,0xee,0x09 = srai.b $w24, $w29, 1
0x78,0xe0,0x30,0x49 = srai.h $w1, $w6, 0
0x78,0xc1,0xd1,0xc9 = srai.w $w7, $w26, 1
0x78,0x83,0xcd,0x09 = srai.d $w20, $w25, 3
0x79,0x70,0xc9,0x4a = srari.b $w5, $w25, 0
0x79,0x64,0x31,0xca = srari.h $w7, $w6, 4
0x79,0x45,0x5c,0x4a = srari.w $w17, $w11, 5
0x79,0x05,0xcd,0x4a = srari.d $w21, $w25, 5
0x79,0x72,0x00,0x89 = srli.b $w2, $w0, 2
0x79,0x62,0xff,0xc9 = srli.h $w31, $w31, 2
0x79,0x44,0x49,0x49 = srli.w $w5, $w9, 4
0x79,0x05,0xd6,0xc9 = srli.d $w27, $w26, 5
0x79,0xf0,0x1c,0x8a = srlri.b $w18, $w3, 0
0x79,0xe3,0x10,0x4a = srlri.h $w1, $w2, 3
0x79,0xc2,0xb2,0xca = srlri.w $w11, $w22, 2
0x79,0x86,0x56,0x0a = srlri.d $w24, $w10, 6
0x79,0xf2,0xf5,0x49 == bclri.b $w21, $w30, 2 # encoding: [0x79,0xf2,0xf5,0x49]
0x79,0xe0,0xae,0x09 == bclri.h $w24, $w21, 0 # encoding: [0x79,0xe0,0xae,0x09]
0x79,0xc3,0xf5,0xc9 == bclri.w $w23, $w30, 3 # encoding: [0x79,0xc3,0xf5,0xc9]
0x79,0x80,0x5a,0x49 == bclri.d $w9, $w11, 0 # encoding: [0x79,0x80,0x5a,0x49]
0x7b,0x71,0x66,0x49 == binsli.b $w25, $w12, 1 # encoding: [0x7b,0x71,0x66,0x49]
0x7b,0x60,0xb5,0x49 == binsli.h $w21, $w22, 0 # encoding: [0x7b,0x60,0xb5,0x49]
0x7b,0x40,0x25,0x89 == binsli.w $w22, $w4, 0 # encoding: [0x7b,0x40,0x25,0x89]
0x7b,0x06,0x11,0x89 == binsli.d $w6, $w2, 6 # encoding: [0x7b,0x06,0x11,0x89]
0x7b,0xf0,0x9b,0xc9 == binsri.b $w15, $w19, 0 # encoding: [0x7b,0xf0,0x9b,0xc9]
0x7b,0xe1,0xf2,0x09 == binsri.h $w8, $w30, 1 # encoding: [0x7b,0xe1,0xf2,0x09]
0x7b,0xc5,0x98,0x89 == binsri.w $w2, $w19, 5 # encoding: [0x7b,0xc5,0x98,0x89]
0x7b,0x81,0xa4,0x89 == binsri.d $w18, $w20, 1 # encoding: [0x7b,0x81,0xa4,0x89]
0x7a,0xf0,0x9e,0x09 == bnegi.b $w24, $w19, 0 # encoding: [0x7a,0xf0,0x9e,0x09]
0x7a,0xe3,0x5f,0x09 == bnegi.h $w28, $w11, 3 # encoding: [0x7a,0xe3,0x5f,0x09]
0x7a,0xc5,0xd8,0x49 == bnegi.w $w1, $w27, 5 # encoding: [0x7a,0xc5,0xd8,0x49]
0x7a,0x81,0xa9,0x09 == bnegi.d $w4, $w21, 1 # encoding: [0x7a,0x81,0xa9,0x09]
0x7a,0x70,0x44,0x89 == bseti.b $w18, $w8, 0 # encoding: [0x7a,0x70,0x44,0x89]
0x7a,0x62,0x76,0x09 == bseti.h $w24, $w14, 2 # encoding: [0x7a,0x62,0x76,0x09]
0x7a,0x44,0x92,0x49 == bseti.w $w9, $w18, 4 # encoding: [0x7a,0x44,0x92,0x49]
0x7a,0x01,0x79,0xc9 == bseti.d $w7, $w15, 1 # encoding: [0x7a,0x01,0x79,0xc9]
0x78,0x72,0xff,0xca == sat_s.b $w31, $w31, 2 # encoding: [0x78,0x72,0xff,0xca]
0x78,0x60,0x9c,0xca == sat_s.h $w19, $w19, 0 # encoding: [0x78,0x60,0x9c,0xca]
0x78,0x40,0xec,0xca == sat_s.w $w19, $w29, 0 # encoding: [0x78,0x40,0xec,0xca]
0x78,0x00,0xb2,0xca == sat_s.d $w11, $w22, 0 # encoding: [0x78,0x00,0xb2,0xca]
0x78,0xf3,0x68,0x4a == sat_u.b $w1, $w13, 3 # encoding: [0x78,0xf3,0x68,0x4a]
0x78,0xe4,0xc7,0x8a == sat_u.h $w30, $w24, 4 # encoding: [0x78,0xe4,0xc7,0x8a]
0x78,0xc0,0x6f,0xca == sat_u.w $w31, $w13, 0 # encoding: [0x78,0xc0,0x6f,0xca]
0x78,0x85,0x87,0x4a == sat_u.d $w29, $w16, 5 # encoding: [0x78,0x85,0x87,0x4a]
0x78,0x71,0x55,0xc9 == slli.b $w23, $w10, 1 # encoding: [0x78,0x71,0x55,0xc9]
0x78,0x61,0x92,0x49 == slli.h $w9, $w18, 1 # encoding: [0x78,0x61,0x92,0x49]
0x78,0x44,0xea,0xc9 == slli.w $w11, $w29, 4 # encoding: [0x78,0x44,0xea,0xc9]
0x78,0x01,0xa6,0x49 == slli.d $w25, $w20, 1 # encoding: [0x78,0x01,0xa6,0x49]
0x78,0xf1,0xee,0x09 == srai.b $w24, $w29, 1 # encoding: [0x78,0xf1,0xee,0x09]
0x78,0xe0,0x30,0x49 == srai.h $w1, $w6, 0 # encoding: [0x78,0xe0,0x30,0x49]
0x78,0xc1,0xd1,0xc9 == srai.w $w7, $w26, 1 # encoding: [0x78,0xc1,0xd1,0xc9]
0x78,0x83,0xcd,0x09 == srai.d $w20, $w25, 3 # encoding: [0x78,0x83,0xcd,0x09]
0x79,0x70,0xc9,0x4a == srari.b $w5, $w25, 0 # encoding: [0x79,0x70,0xc9,0x4a]
0x79,0x64,0x31,0xca == srari.h $w7, $w6, 4 # encoding: [0x79,0x64,0x31,0xca]
0x79,0x45,0x5c,0x4a == srari.w $w17, $w11, 5 # encoding: [0x79,0x45,0x5c,0x4a]
0x79,0x05,0xcd,0x4a == srari.d $w21, $w25, 5 # encoding: [0x79,0x05,0xcd,0x4a]
0x79,0x72,0x00,0x89 == srli.b $w2, $w0, 2 # encoding: [0x79,0x72,0x00,0x89]
0x79,0x62,0xff,0xc9 == srli.h $w31, $w31, 2 # encoding: [0x79,0x62,0xff,0xc9]
0x79,0x44,0x49,0x49 == srli.w $w5, $w9, 4 # encoding: [0x79,0x44,0x49,0x49]
0x79,0x05,0xd6,0xc9 == srli.d $w27, $w26, 5 # encoding: [0x79,0x05,0xd6,0xc9]
0x79,0xf0,0x1c,0x8a == srlri.b $w18, $w3, 0 # encoding: [0x79,0xf0,0x1c,0x8a]
0x79,0xe3,0x10,0x4a == srlri.h $w1, $w2, 3 # encoding: [0x79,0xe3,0x10,0x4a]
0x79,0xc2,0xb2,0xca == srlri.w $w11, $w22, 2 # encoding: [0x79,0xc2,0xb2,0xca]
0x79,0x86,0x56,0x0a == srlri.d $w24, $w10, 6 # encoding: [0x79,0x86,0x56,0x0a]

50
suite/MC/Mips/test_cbranch.s.cs
View File

@ -1,11 +1,41 @@
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
// 0x47,0x80,0x00,0x01 = bnz.b $w0, 4
// 0x47,0xa1,0x00,0x04 = bnz.h $w1, 16
// 0x47,0xc2,0x00,0x20 = bnz.w $w2, 128
// 0x47,0xe3,0xff,0xe0 = bnz.d $w3, -128
// 0x45,0xe0,0x00,0x01 = bnz.v $w0, 4
// 0x47,0x00,0x00,0x20 = bz.b $w0, 128
// 0x47,0x21,0x00,0x40 = bz.h $w1, 256
// 0x47,0x42,0x00,0x80 = bz.w $w2, 512
// 0x47,0x63,0xff,0x00 = bz.d $w3, -1024
// 0x45,0x60,0x00,0x01 = bz.v $w0, 4
0x47,0x80,0x00,0x01 == bnz.b $w0, 4 # encoding: [0x47,0x80,0x00,0x01]
0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00]
0x47,0xa1,0x00,0x04 == bnz.h $w1, 16 # encoding: [0x47,0xa1,0x00,0x04]
0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00]
0x47,0xc2,0x00,0x20 == bnz.w $w2, 128 # encoding: [0x47,0xc2,0x00,0x20]
0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00]
0x47,0xe3,0xff,0xe0 == bnz.d $w3, -128 # encoding: [0x47,0xe3,0xff,0xe0]
0x47,0x80, == bnz.b $w0, SYMBOL0 # encoding: [0x47,0x80,A,A]
0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00]
0x47,0xa1, == bnz.h $w1, SYMBOL1 # encoding: [0x47,0xa1,A,A]
0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00]
0x47,0xc2, == bnz.w $w2, SYMBOL2 # encoding: [0x47,0xc2,A,A]
0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00]
0x47,0xe3, == bnz.d $w3, SYMBOL3 # encoding: [0x47,0xe3,A,A]
0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00]
0x45,0xe0,0x00,0x01 == bnz.v $w0, 4 # encoding: [0x45,0xe0,0x00,0x01]
0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00]
0x45,0xe0, == bnz.v $w0, SYMBOL0 # encoding: [0x45,0xe0,A,A]
0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00]
0x47,0x00,0x00,0x20 == bz.b $w0, 128 # encoding: [0x47,0x00,0x00,0x20]
0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00]
0x47,0x21,0x00,0x40 == bz.h $w1, 256 # encoding: [0x47,0x21,0x00,0x40]
0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00]
0x47,0x42,0x00,0x80 == bz.w $w2, 512 # encoding: [0x47,0x42,0x00,0x80]
0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00]
0x47,0x63,0xff,0x00 == bz.d $w3, -1024 # encoding: [0x47,0x63,0xff,0x00]
0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00]
0x47,0x00, == bz.b $w0, SYMBOL0 # encoding: [0x47,0x00,A,A]
0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00]
0x47,0x21, == bz.h $w1, SYMBOL1 # encoding: [0x47,0x21,A,A]
0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00]
0x47,0x42, == bz.w $w2, SYMBOL2 # encoding: [0x47,0x42,A,A]
0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00]
0x47,0x63, == bz.d $w3, SYMBOL3 # encoding: [0x47,0x63,A,A]
0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00]
0x45,0x60,0x00,0x01 == bz.v $w0, 4 # encoding: [0x45,0x60,0x00,0x01]
0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00]
0x45,0x60, == bz.v $w0, SYMBOL0 # encoding: [0x45,0x60,A,A]
0x00,0x00,0x00,0x00 == nop # encoding: [0x00,0x00,0x00,0x00]

65
suite/MC/Mips/test_ctrlregs.s.cs
View File

@ -1,33 +1,34 @@
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
0x78,0x7e,0x00,0x59 = cfcmsa $at, $0
0x78,0x7e,0x00,0x59 = cfcmsa $at, $0
0x78,0x7e,0x08,0x99 = cfcmsa $v0, $1
0x78,0x7e,0x08,0x99 = cfcmsa $v0, $1
0x78,0x7e,0x10,0xd9 = cfcmsa $v1, $2
0x78,0x7e,0x10,0xd9 = cfcmsa $v1, $2
0x78,0x7e,0x19,0x19 = cfcmsa $a0, $3
0x78,0x7e,0x19,0x19 = cfcmsa $a0, $3
0x78,0x7e,0x21,0x59 = cfcmsa $a1, $4
0x78,0x7e,0x21,0x59 = cfcmsa $a1, $4
0x78,0x7e,0x29,0x99 = cfcmsa $a2, $5
0x78,0x7e,0x29,0x99 = cfcmsa $a2, $5
0x78,0x7e,0x31,0xd9 = cfcmsa $a3, $6
0x78,0x7e,0x31,0xd9 = cfcmsa $a3, $6
0x78,0x7e,0x3a,0x19 = cfcmsa $t0, $7
0x78,0x7e,0x3a,0x19 = cfcmsa $t0, $7
0x78,0x3e,0x08,0x19 = ctcmsa $0, $at
0x78,0x3e,0x08,0x19 = ctcmsa $0, $at
0x78,0x3e,0x10,0x59 = ctcmsa $1, $v0
0x78,0x3e,0x10,0x59 = ctcmsa $1, $v0
0x78,0x3e,0x18,0x99 = ctcmsa $2, $v1
0x78,0x3e,0x18,0x99 = ctcmsa $2, $v1
0x78,0x3e,0x20,0xd9 = ctcmsa $3, $a0
0x78,0x3e,0x20,0xd9 = ctcmsa $3, $a0
0x78,0x3e,0x29,0x19 = ctcmsa $4, $a1
0x78,0x3e,0x29,0x19 = ctcmsa $4, $a1
0x78,0x3e,0x31,0x59 = ctcmsa $5, $a2
0x78,0x3e,0x31,0x59 = ctcmsa $5, $a2
0x78,0x3e,0x39,0x99 = ctcmsa $6, $a3
0x78,0x3e,0x39,0x99 = ctcmsa $6, $a3
0x78,0x3e,0x41,0xd9 = ctcmsa $7, $t0
0x78,0x3e,0x41,0xd9 = ctcmsa $7, $t0
0x78,0x7e,0x00,0x59 == cfcmsa $1, $0 # encoding: [0x78,0x7e,0x00,0x59]
0x78,0x7e,0x00,0x59 == cfcmsa $1, $0 # encoding: [0x78,0x7e,0x00,0x59]
0x78,0x7e,0x08,0x99 == cfcmsa $2, $1 # encoding: [0x78,0x7e,0x08,0x99]
0x78,0x7e,0x08,0x99 == cfcmsa $2, $1 # encoding: [0x78,0x7e,0x08,0x99]
0x78,0x7e,0x10,0xd9 == cfcmsa $3, $2 # encoding: [0x78,0x7e,0x10,0xd9]
0x78,0x7e,0x10,0xd9 == cfcmsa $3, $2 # encoding: [0x78,0x7e,0x10,0xd9]
0x78,0x7e,0x19,0x19 == cfcmsa $4, $3 # encoding: [0x78,0x7e,0x19,0x19]
0x78,0x7e,0x19,0x19 == cfcmsa $4, $3 # encoding: [0x78,0x7e,0x19,0x19]
0x78,0x7e,0x21,0x59 == cfcmsa $5, $4 # encoding: [0x78,0x7e,0x21,0x59]
0x78,0x7e,0x21,0x59 == cfcmsa $5, $4 # encoding: [0x78,0x7e,0x21,0x59]
0x78,0x7e,0x29,0x99 == cfcmsa $6, $5 # encoding: [0x78,0x7e,0x29,0x99]
0x78,0x7e,0x29,0x99 == cfcmsa $6, $5 # encoding: [0x78,0x7e,0x29,0x99]
0x78,0x7e,0x31,0xd9 == cfcmsa $7, $6 # encoding: [0x78,0x7e,0x31,0xd9]
0x78,0x7e,0x31,0xd9 == cfcmsa $7, $6 # encoding: [0x78,0x7e,0x31,0xd9]
0x78,0x7e,0x3a,0x19 == cfcmsa $8, $7 # encoding: [0x78,0x7e,0x3a,0x19]
0x78,0x7e,0x3a,0x19 == cfcmsa $8, $7 # encoding: [0x78,0x7e,0x3a,0x19]
0x78,0x3e,0x08,0x19 == ctcmsa $0, $1 # encoding: [0x78,0x3e,0x08,0x19]
0x78,0x3e,0x08,0x19 == ctcmsa $0, $1 # encoding: [0x78,0x3e,0x08,0x19]
0x78,0x3e,0x10,0x59 == ctcmsa $1, $2 # encoding: [0x78,0x3e,0x10,0x59]
0x78,0x3e,0x10,0x59 == ctcmsa $1, $2 # encoding: [0x78,0x3e,0x10,0x59]
0x78,0x3e,0x18,0x99 == ctcmsa $2, $3 # encoding: [0x78,0x3e,0x18,0x99]
0x78,0x3e,0x18,0x99 == ctcmsa $2, $3 # encoding: [0x78,0x3e,0x18,0x99]
0x78,0x3e,0x20,0xd9 == ctcmsa $3, $4 # encoding: [0x78,0x3e,0x20,0xd9]
0x78,0x3e,0x20,0xd9 == ctcmsa $3, $4 # encoding: [0x78,0x3e,0x20,0xd9]
0x78,0x3e,0x29,0x19 == ctcmsa $4, $5 # encoding: [0x78,0x3e,0x29,0x19]
0x78,0x3e,0x29,0x19 == ctcmsa $4, $5 # encoding: [0x78,0x3e,0x29,0x19]
0x78,0x3e,0x31,0x59 == ctcmsa $5, $6 # encoding: [0x78,0x3e,0x31,0x59]
0x78,0x3e,0x31,0x59 == ctcmsa $5, $6 # encoding: [0x78,0x3e,0x31,0x59]
0x78,0x3e,0x39,0x99 == ctcmsa $6, $7 # encoding: [0x78,0x3e,0x39,0x99]
0x78,0x3e,0x39,0x99 == ctcmsa $6, $7 # encoding: [0x78,0x3e,0x39,0x99]
0x78,0x3e,0x41,0xd9 == ctcmsa $7, $8 # encoding: [0x78,0x3e,0x41,0xd9]
0x78,0x3e,0x41,0xd9 == ctcmsa $7, $8 # encoding: [0x78,0x3e,0x41,0xd9]

30
suite/MC/Mips/test_elm.s.cs
View File

@ -1,16 +1,16 @@
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
0x78,0x82,0x43,0x59 = copy_s.b $t5, $w8[2]
0x78,0xa0,0xc8,0x59 = copy_s.h $at, $w25[0]
0x78,0xb1,0x2d,0x99 = copy_s.w $s6, $w5[1]
0x78,0xc4,0xa5,0x99 = copy_u.b $s6, $w20[4]
0x78,0xe0,0x25,0x19 = copy_u.h $s4, $w4[0]
0x78,0xf2,0x6f,0x99 = copy_u.w $fp, $w13[2]
0x78,0x04,0xe8,0x19 = sldi.b $w0, $w29[4]
0x78,0x20,0x8a,0x19 = sldi.h $w8, $w17[0]
0x78,0x32,0xdd,0x19 = sldi.w $w20, $w27[2]
0x78,0x38,0x61,0x19 = sldi.d $w4, $w12[0]
0x78,0x42,0x1e,0x59 = splati.b $w25, $w3[2]
0x78,0x61,0xe6,0x19 = splati.h $w24, $w28[1]
0x78,0x70,0x93,0x59 = splati.w $w13, $w18[0]
0x78,0x78,0x0f,0x19 = splati.d $w28, $w1[0]
0x78,0xbe,0xc5,0xd9 = move.v $w23, $w24
0x78,0x82,0x43,0x59 == copy_s.b $13, $w8[2] # encoding: [0x78,0x82,0x43,0x59]
0x78,0xa0,0xc8,0x59 == copy_s.h $1, $w25[0] # encoding: [0x78,0xa0,0xc8,0x59]
0x78,0xb1,0x2d,0x99 == copy_s.w $22, $w5[1] # encoding: [0x78,0xb1,0x2d,0x99]
0x78,0xc4,0xa5,0x99 == copy_u.b $22, $w20[4] # encoding: [0x78,0xc4,0xa5,0x99]
0x78,0xe0,0x25,0x19 == copy_u.h $20, $w4[0] # encoding: [0x78,0xe0,0x25,0x19]
0x78,0x04,0xe8,0x19 == sldi.b $w0, $w29[4] # encoding: [0x78,0x04,0xe8,0x19]
0x78,0x20,0x8a,0x19 == sldi.h $w8, $w17[0] # encoding: [0x78,0x20,0x8a,0x19]
0x78,0x32,0xdd,0x19 == sldi.w $w20, $w27[2] # encoding: [0x78,0x32,0xdd,0x19]
0x78,0x38,0x61,0x19 == sldi.d $w4, $w12[0] # encoding: [0x78,0x38,0x61,0x19]
0x78,0x42,0x1e,0x59 == splati.b $w25, $w3[2] # encoding: [0x78,0x42,0x1e,0x59]
0x78,0x61,0xe6,0x19 == splati.h $w24, $w28[1] # encoding: [0x78,0x61,0xe6,0x19]
0x78,0x70,0x93,0x59 == splati.w $w13, $w18[0] # encoding: [0x78,0x70,0x93,0x59]
0x78,0x78,0x0f,0x19 == splati.d $w28, $w1[0] # encoding: [0x78,0x78,0x0f,0x19]
0x78,0xbe,0xc5,0xd9 == move.v $w23, $w24 # encoding: [0x78,0xbe,0xc5,0xd9]

7
suite/MC/Mips/test_elm_insert.s.cs
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@ -1,4 +1,5 @@
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
0x79,0x03,0xed,0xd9 = insert.b $w23[3], $sp
0x79,0x22,0x2d,0x19 = insert.h $w20[2], $a1
0x79,0x32,0x7a,0x19 = insert.w $w8[2], $t7
0x79,0x03,0xed,0xd9 == insert.b $w23[3], $sp # encoding: [0x79,0x03,0xed,0xd9]
0x79,0x22,0x2d,0x19 == insert.h $w20[2], $5 # encoding: [0x79,0x22,0x2d,0x19]
0x79,0x32,0x7a,0x19 == insert.w $w8[2], $15 # encoding: [0x79,0x32,0x7a,0x19]

9
suite/MC/Mips/test_elm_insve.s.cs
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@ -1,5 +1,6 @@
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
0x79,0x43,0x4e,0x59 = insve.b $w25[3], $w9[0]
0x79,0x62,0x16,0x19 = insve.h $w24[2], $w2[0]
0x79,0x72,0x68,0x19 = insve.w $w0[2], $w13[0]
0x79,0x78,0x90,0xd9 = insve.d $w3[0], $w18[0]
0x79,0x43,0x4e,0x59 == insve.b $w25[3], $w9[0] # encoding: [0x79,0x43,0x4e,0x59]
0x79,0x62,0x16,0x19 == insve.h $w24[2], $w2[0] # encoding: [0x79,0x62,0x16,0x19]
0x79,0x72,0x68,0x19 == insve.w $w0[2], $w13[0] # encoding: [0x79,0x72,0x68,0x19]
0x79,0x78,0x90,0xd9 == insve.d $w3[0], $w18[0] # encoding: [0x79,0x78,0x90,0xd9]

9
suite/MC/Mips/test_i10.s.cs
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@ -1,5 +1,6 @@
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
0x7b,0x06,0x32,0x07 = ldi.b $w8, 198
0x7b,0x29,0xcd,0x07 = ldi.h $w20, 313
0x7b,0x4f,0x66,0x07 = ldi.w $w24, 492
// 0x7b,0x7a,0x66,0xc7 = ldi.d $w27, -180
0x7b,0x06,0x32,0x07 == ldi.b $w8, 198 # encoding: [0x7b,0x06,0x32,0x07]
0x7b,0x29,0xcd,0x07 == ldi.h $w20, 313 # encoding: [0x7b,0x29,0xcd,0x07]
0x7b,0x4f,0x66,0x07 == ldi.w $w24, 492 # encoding: [0x7b,0x4f,0x66,0x07]
0x7b,0x7a,0x66,0xc7 == ldi.d $w27, -180 # encoding: [0x7b,0x7a,0x66,0xc7]

89
suite/MC/Mips/test_i5.s.cs
View File

@ -1,45 +1,46 @@
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
0x78,0x1e,0xf8,0xc6 = addvi.b $w3, $w31, 30
0x78,0x3a,0x6e,0x06 = addvi.h $w24, $w13, 26
0x78,0x5a,0xa6,0x86 = addvi.w $w26, $w20, 26
0x78,0x75,0x0c,0x06 = addvi.d $w16, $w1, 21
// 0x78,0x18,0xae,0x07 = ceqi.b $w24, $w21, -8
0x78,0x22,0x7f,0xc7 = ceqi.h $w31, $w15, 2
// 0x78,0x5f,0x0b,0x07 = ceqi.w $w12, $w1, -1
0x78,0x67,0xb6,0x07 = ceqi.d $w24, $w22, 7
0x7a,0x01,0x83,0x07 = clei_s.b $w12, $w16, 1
// 0x7a,0x37,0x50,0x87 = clei_s.h $w2, $w10, -9
// 0x7a,0x56,0x59,0x07 = clei_s.w $w4, $w11, -10
// 0x7a,0x76,0xe8,0x07 = clei_s.d $w0, $w29, -10
0x7a,0x83,0x8d,0x47 = clei_u.b $w21, $w17, 3
0x7a,0xb1,0x3f,0x47 = clei_u.h $w29, $w7, 17
0x7a,0xc2,0x08,0x47 = clei_u.w $w1, $w1, 2
0x7a,0xfd,0xde,0xc7 = clei_u.d $w27, $w27, 29
// 0x79,0x19,0x6c,0xc7 = clti_s.b $w19, $w13, -7
// 0x79,0x34,0x53,0xc7 = clti_s.h $w15, $w10, -12
0x79,0x4b,0x63,0x07 = clti_s.w $w12, $w12, 11
// 0x79,0x71,0xa7,0x47 = clti_s.d $w29, $w20, -15
0x79,0x9d,0x4b,0x87 = clti_u.b $w14, $w9, 29
0x79,0xb9,0xce,0x07 = clti_u.h $w24, $w25, 25
0x79,0xd6,0x08,0x47 = clti_u.w $w1, $w1, 22
0x79,0xe1,0xcd,0x47 = clti_u.d $w21, $w25, 1
0x79,0x01,0xad,0x86 = maxi_s.b $w22, $w21, 1
// 0x79,0x38,0x2f,0x46 = maxi_s.h $w29, $w5, -8
// 0x79,0x54,0x50,0x46 = maxi_s.w $w1, $w10, -12
// 0x79,0x70,0xeb,0x46 = maxi_s.d $w13, $w29, -16
0x79,0x8c,0x05,0x06 = maxi_u.b $w20, $w0, 12
0x79,0xa3,0x70,0x46 = maxi_u.h $w1, $w14, 3
0x79,0xcb,0xb6,0xc6 = maxi_u.w $w27, $w22, 11
0x79,0xe4,0x36,0x86 = maxi_u.d $w26, $w6, 4
0x7a,0x01,0x09,0x06 = mini_s.b $w4, $w1, 1
// 0x7a,0x37,0xde,0xc6 = mini_s.h $w27, $w27, -9
0x7a,0x49,0x5f,0x06 = mini_s.w $w28, $w11, 9
0x7a,0x6a,0x52,0xc6 = mini_s.d $w11, $w10, 10
0x7a,0x9b,0xbc,0x86 = mini_u.b $w18, $w23, 27
0x7a,0xb2,0xd1,0xc6 = mini_u.h $w7, $w26, 18
0x7a,0xda,0x62,0xc6 = mini_u.w $w11, $w12, 26
0x7a,0xe2,0x7a,0xc6 = mini_u.d $w11, $w15, 2
0x78,0x93,0xa6,0x06 = subvi.b $w24, $w20, 19
0x78,0xa4,0x9a,0xc6 = subvi.h $w11, $w19, 4
0x78,0xcb,0x53,0x06 = subvi.w $w12, $w10, 11
0x78,0xe7,0x84,0xc6 = subvi.d $w19, $w16, 7
0x78,0x1e,0xf8,0xc6 == addvi.b $w3, $w31, 30 # encoding: [0x78,0x1e,0xf8,0xc6]
0x78,0x3a,0x6e,0x06 == addvi.h $w24, $w13, 26 # encoding: [0x78,0x3a,0x6e,0x06]
0x78,0x5a,0xa6,0x86 == addvi.w $w26, $w20, 26 # encoding: [0x78,0x5a,0xa6,0x86]
0x78,0x75,0x0c,0x06 == addvi.d $w16, $w1, 21 # encoding: [0x78,0x75,0x0c,0x06]
0x78,0x18,0xae,0x07 == ceqi.b $w24, $w21, -8 # encoding: [0x78,0x18,0xae,0x07]
0x78,0x22,0x7f,0xc7 == ceqi.h $w31, $w15, 2 # encoding: [0x78,0x22,0x7f,0xc7]
0x78,0x5f,0x0b,0x07 == ceqi.w $w12, $w1, -1 # encoding: [0x78,0x5f,0x0b,0x07]
0x78,0x67,0xb6,0x07 == ceqi.d $w24, $w22, 7 # encoding: [0x78,0x67,0xb6,0x07]
0x7a,0x01,0x83,0x07 == clei_s.b $w12, $w16, 1 # encoding: [0x7a,0x01,0x83,0x07]
0x7a,0x37,0x50,0x87 == clei_s.h $w2, $w10, -9 # encoding: [0x7a,0x37,0x50,0x87]
0x7a,0x56,0x59,0x07 == clei_s.w $w4, $w11, -10 # encoding: [0x7a,0x56,0x59,0x07]
0x7a,0x76,0xe8,0x07 == clei_s.d $w0, $w29, -10 # encoding: [0x7a,0x76,0xe8,0x07]
0x7a,0x83,0x8d,0x47 == clei_u.b $w21, $w17, 3 # encoding: [0x7a,0x83,0x8d,0x47]
0x7a,0xb1,0x3f,0x47 == clei_u.h $w29, $w7, 17 # encoding: [0x7a,0xb1,0x3f,0x47]
0x7a,0xc2,0x08,0x47 == clei_u.w $w1, $w1, 2 # encoding: [0x7a,0xc2,0x08,0x47]
0x7a,0xfd,0xde,0xc7 == clei_u.d $w27, $w27, 29 # encoding: [0x7a,0xfd,0xde,0xc7]
0x79,0x19,0x6c,0xc7 == clti_s.b $w19, $w13, -7 # encoding: [0x79,0x19,0x6c,0xc7]
0x79,0x34,0x53,0xc7 == clti_s.h $w15, $w10, -12 # encoding: [0x79,0x34,0x53,0xc7]
0x79,0x4b,0x63,0x07 == clti_s.w $w12, $w12, 11 # encoding: [0x79,0x4b,0x63,0x07]
0x79,0x71,0xa7,0x47 == clti_s.d $w29, $w20, -15 # encoding: [0x79,0x71,0xa7,0x47]
0x79,0x9d,0x4b,0x87 == clti_u.b $w14, $w9, 29 # encoding: [0x79,0x9d,0x4b,0x87]
0x79,0xb9,0xce,0x07 == clti_u.h $w24, $w25, 25 # encoding: [0x79,0xb9,0xce,0x07]
0x79,0xd6,0x08,0x47 == clti_u.w $w1, $w1, 22 # encoding: [0x79,0xd6,0x08,0x47]
0x79,0xe1,0xcd,0x47 == clti_u.d $w21, $w25, 1 # encoding: [0x79,0xe1,0xcd,0x47]
0x79,0x01,0xad,0x86 == maxi_s.b $w22, $w21, 1 # encoding: [0x79,0x01,0xad,0x86]
0x79,0x38,0x2f,0x46 == maxi_s.h $w29, $w5, -8 # encoding: [0x79,0x38,0x2f,0x46]
0x79,0x54,0x50,0x46 == maxi_s.w $w1, $w10, -12 # encoding: [0x79,0x54,0x50,0x46]
0x79,0x70,0xeb,0x46 == maxi_s.d $w13, $w29, -16 # encoding: [0x79,0x70,0xeb,0x46]
0x79,0x8c,0x05,0x06 == maxi_u.b $w20, $w0, 12 # encoding: [0x79,0x8c,0x05,0x06]
0x79,0xa3,0x70,0x46 == maxi_u.h $w1, $w14, 3 # encoding: [0x79,0xa3,0x70,0x46]
0x79,0xcb,0xb6,0xc6 == maxi_u.w $w27, $w22, 11 # encoding: [0x79,0xcb,0xb6,0xc6]
0x79,0xe4,0x36,0x86 == maxi_u.d $w26, $w6, 4 # encoding: [0x79,0xe4,0x36,0x86]
0x7a,0x01,0x09,0x06 == mini_s.b $w4, $w1, 1 # encoding: [0x7a,0x01,0x09,0x06]
0x7a,0x37,0xde,0xc6 == mini_s.h $w27, $w27, -9 # encoding: [0x7a,0x37,0xde,0xc6]
0x7a,0x49,0x5f,0x06 == mini_s.w $w28, $w11, 9 # encoding: [0x7a,0x49,0x5f,0x06]
0x7a,0x6a,0x52,0xc6 == mini_s.d $w11, $w10, 10 # encoding: [0x7a,0x6a,0x52,0xc6]
0x7a,0x9b,0xbc,0x86 == mini_u.b $w18, $w23, 27 # encoding: [0x7a,0x9b,0xbc,0x86]
0x7a,0xb2,0xd1,0xc6 == mini_u.h $w7, $w26, 18 # encoding: [0x7a,0xb2,0xd1,0xc6]
0x7a,0xda,0x62,0xc6 == mini_u.w $w11, $w12, 26 # encoding: [0x7a,0xda,0x62,0xc6]
0x7a,0xe2,0x7a,0xc6 == mini_u.d $w11, $w15, 2 # encoding: [0x7a,0xe2,0x7a,0xc6]
0x78,0x93,0xa6,0x06 == subvi.b $w24, $w20, 19 # encoding: [0x78,0x93,0xa6,0x06]
0x78,0xa4,0x9a,0xc6 == subvi.h $w11, $w19, 4 # encoding: [0x78,0xa4,0x9a,0xc6]
0x78,0xcb,0x53,0x06 == subvi.w $w12, $w10, 11 # encoding: [0x78,0xcb,0x53,0x06]
0x78,0xe7,0x84,0xc6 == subvi.d $w19, $w16, 7 # encoding: [0x78,0xe7,0x84,0xc6]

21
suite/MC/Mips/test_i8.s.cs
View File

@ -1,11 +1,12 @@
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
0x78,0x30,0xe8,0x80 = andi.b $w2, $w29, 48
0x78,0x7e,0xb1,0x81 = bmnzi.b $w6, $w22, 126
0x79,0x58,0x0e,0xc1 = bmzi.b $w27, $w1, 88
0x7a,0xbd,0x1f,0x41 = bseli.b $w29, $w3, 189
0x7a,0x38,0x88,0x40 = nori.b $w1, $w17, 56
0x79,0x87,0xa6,0x80 = ori.b $w26, $w20, 135
0x78,0x69,0xf4,0xc2 = shf.b $w19, $w30, 105
0x79,0x4c,0x44,0x42 = shf.h $w17, $w8, 76
0x7a,0x5d,0x1b,0x82 = shf.w $w14, $w3, 93
0x7b,0x14,0x54,0x00 = xori.b $w16, $w10, 20
0x78,0x30,0xe8,0x80 == andi.b $w2, $w29, 48 # encoding: [0x78,0x30,0xe8,0x80]
0x78,0x7e,0xb1,0x81 == bmnzi.b $w6, $w22, 126 # encoding: [0x78,0x7e,0xb1,0x81]
0x79,0x58,0x0e,0xc1 == bmzi.b $w27, $w1, 88 # encoding: [0x79,0x58,0x0e,0xc1]
0x7a,0xbd,0x1f,0x41 == bseli.b $w29, $w3, 189 # encoding: [0x7a,0xbd,0x1f,0x41]
0x7a,0x38,0x88,0x40 == nori.b $w1, $w17, 56 # encoding: [0x7a,0x38,0x88,0x40]
0x79,0x87,0xa6,0x80 == ori.b $w26, $w20, 135 # encoding: [0x79,0x87,0xa6,0x80]
0x78,0x69,0xf4,0xc2 == shf.b $w19, $w30, 105 # encoding: [0x78,0x69,0xf4,0xc2]
0x79,0x4c,0x44,0x42 == shf.h $w17, $w8, 76 # encoding: [0x79,0x4c,0x44,0x42]
0x7a,0x5d,0x1b,0x82 == shf.w $w14, $w3, 93 # encoding: [0x7a,0x5d,0x1b,0x82]
0x7b,0x14,0x54,0x00 == xori.b $w16, $w10, 20 # encoding: [0x7b,0x14,0x54,0x00]

9
suite/MC/Mips/test_lsa.s.cs
View File

@ -1,5 +1,6 @@
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
0x01,0x2a,0x40,0x05 = lsa $t0, $t1, $t2, 1
0x01,0x2a,0x40,0x45 = lsa $t0, $t1, $t2, 2
0x01,0x2a,0x40,0x85 = lsa $t0, $t1, $t2, 3
0x01,0x2a,0x40,0xc5 = lsa $t0, $t1, $t2, 4
0x01,0x2a,0x40,0x05 == lsa $8, $9, $10, 1 # encoding: [0x01,0x2a,0x40,0x05]
0x01,0x2a,0x40,0x45 == lsa $8, $9, $10, 2 # encoding: [0x01,0x2a,0x40,0x45]
0x01,0x2a,0x40,0x85 == lsa $8, $9, $10, 3 # encoding: [0x01,0x2a,0x40,0x85]
0x01,0x2a,0x40,0xc5 == lsa $8, $9, $10, 4 # encoding: [0x01,0x2a,0x40,0xc5]

47
suite/MC/Mips/test_mi10.s.cs
View File

@ -1,24 +1,25 @@
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
0x7a,0x00,0x08,0x20 = ld.b $w0, -512($at)
0x78,0x00,0x10,0x60 = ld.b $w1, ($v0)
0x79,0xff,0x18,0xa0 = ld.b $w2, 511($v1)
0x7a,0x00,0x20,0xe1 = ld.h $w3, -1024($a0)
0x7b,0x00,0x29,0x21 = ld.h $w4, -512($a1)
0x78,0x00,0x31,0x61 = ld.h $w5, ($a2)
0x79,0x00,0x39,0xa1 = ld.h $w6, 512($a3)
0x79,0xff,0x41,0xe1 = ld.h $w7, 1022($t0)
0x7a,0x00,0x4a,0x22 = ld.w $w8, -2048($t1)
0x7b,0x00,0x52,0x62 = ld.w $w9, -1024($t2)
0x7b,0x80,0x5a,0xa2 = ld.w $w10, -512($t3)
0x78,0x80,0x62,0xe2 = ld.w $w11, 512($t4)
0x79,0x00,0x6b,0x22 = ld.w $w12, 1024($t5)
0x79,0xff,0x73,0x62 = ld.w $w13, 2044($t6)
0x7a,0x00,0x7b,0xa3 = ld.d $w14, -4096($t7)
0x7b,0x00,0x83,0xe3 = ld.d $w15, -2048($s0)
0x7b,0x80,0x8c,0x23 = ld.d $w16, -1024($s1)
0x7b,0xc0,0x94,0x63 = ld.d $w17, -512($s2)
0x78,0x00,0x9c,0xa3 = ld.d $w18, ($s3)
0x78,0x40,0xa4,0xe3 = ld.d $w19, 512($s4)
0x78,0x80,0xad,0x23 = ld.d $w20, 1024($s5)
0x79,0x00,0xb5,0x63 = ld.d $w21, 2048($s6)
0x79,0xff,0xbd,0xa3 = ld.d $w22, 4088($s7)
0x7a,0x00,0x08,0x20 == ld.b $w0, -512($1) # encoding: [0x7a,0x00,0x08,0x20]
0x78,0x00,0x10,0x60 == ld.b $w1, 0($2) # encoding: [0x78,0x00,0x10,0x60]
0x79,0xff,0x18,0xa0 == ld.b $w2, 511($3) # encoding: [0x79,0xff,0x18,0xa0]
0x7a,0x00,0x20,0xe1 == ld.h $w3, -1024($4) # encoding: [0x7a,0x00,0x20,0xe1]
0x7b,0x00,0x29,0x21 == ld.h $w4, -512($5) # encoding: [0x7b,0x00,0x29,0x21]
0x78,0x00,0x31,0x61 == ld.h $w5, 0($6) # encoding: [0x78,0x00,0x31,0x61]
0x79,0x00,0x39,0xa1 == ld.h $w6, 512($7) # encoding: [0x79,0x00,0x39,0xa1]
0x79,0xff,0x41,0xe1 == ld.h $w7, 1022($8) # encoding: [0x79,0xff,0x41,0xe1]
0x7a,0x00,0x4a,0x22 == ld.w $w8, -2048($9) # encoding: [0x7a,0x00,0x4a,0x22]
0x7b,0x00,0x52,0x62 == ld.w $w9, -1024($10) # encoding: [0x7b,0x00,0x52,0x62]
0x7b,0x80,0x5a,0xa2 == ld.w $w10, -512($11) # encoding: [0x7b,0x80,0x5a,0xa2]
0x78,0x80,0x62,0xe2 == ld.w $w11, 512($12) # encoding: [0x78,0x80,0x62,0xe2]
0x79,0x00,0x6b,0x22 == ld.w $w12, 1024($13) # encoding: [0x79,0x00,0x6b,0x22]
0x79,0xff,0x73,0x62 == ld.w $w13, 2044($14) # encoding: [0x79,0xff,0x73,0x62]
0x7a,0x00,0x7b,0xa3 == ld.d $w14, -4096($15) # encoding: [0x7a,0x00,0x7b,0xa3]
0x7b,0x00,0x83,0xe3 == ld.d $w15, -2048($16) # encoding: [0x7b,0x00,0x83,0xe3]
0x7b,0x80,0x8c,0x23 == ld.d $w16, -1024($17) # encoding: [0x7b,0x80,0x8c,0x23]
0x7b,0xc0,0x94,0x63 == ld.d $w17, -512($18) # encoding: [0x7b,0xc0,0x94,0x63]
0x78,0x00,0x9c,0xa3 == ld.d $w18, 0($19) # encoding: [0x78,0x00,0x9c,0xa3]
0x78,0x40,0xa4,0xe3 == ld.d $w19, 512($20) # encoding: [0x78,0x40,0xa4,0xe3]
0x78,0x80,0xad,0x23 == ld.d $w20, 1024($21) # encoding: [0x78,0x80,0xad,0x23]
0x79,0x00,0xb5,0x63 == ld.d $w21, 2048($22) # encoding: [0x79,0x00,0xb5,0x63]
0x79,0xff,0xbd,0xa3 == ld.d $w22, 4088($23) # encoding: [0x79,0xff,0xbd,0xa3]

15
suite/MC/Mips/test_vec.s.cs
View File

@ -1,8 +1,9 @@
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
0x78,0x1b,0xa6,0x5e = and.v $w25, $w20, $w27
0x78,0x87,0x34,0x5e = bmnz.v $w17, $w6, $w7
0x78,0xa9,0x88,0xde = bmz.v $w3, $w17, $w9
0x78,0xce,0x02,0x1e = bsel.v $w8, $w0, $w14
0x78,0x40,0xf9,0xde = nor.v $w7, $w31, $w0
0x78,0x3e,0xd6,0x1e = or.v $w24, $w26, $w30
0x78,0x6f,0xd9,0xde = xor.v $w7, $w27, $w15
0x78,0x1b,0xa6,0x5e == and.v $w25, $w20, $w27 # encoding: [0x78,0x1b,0xa6,0x5e]
0x78,0x87,0x34,0x5e == bmnz.v $w17, $w6, $w7 # encoding: [0x78,0x87,0x34,0x5e]
0x78,0xa9,0x88,0xde == bmz.v $w3, $w17, $w9 # encoding: [0x78,0xa9,0x88,0xde]
0x78,0xce,0x02,0x1e == bsel.v $w8, $w0, $w14 # encoding: [0x78,0xce,0x02,0x1e]
0x78,0x40,0xf9,0xde == nor.v $w7, $w31, $w0 # encoding: [0x78,0x40,0xf9,0xde]
0x78,0x3e,0xd6,0x1e == or.v $w24, $w26, $w30 # encoding: [0x78,0x3e,0xd6,0x1e]
0x78,0x6f,0xd9,0xde == xor.v $w7, $w27, $w15 # encoding: [0x78,0x6f,0xd9,0xde]

2
suite/auto-sync/pyproject.toml
View File

@ -8,7 +8,7 @@ version = "0.1.0"
dependencies = [
"termcolor >= 2.3.0",
"tree_sitter == 0.22.3",
"tree-sitter-cpp >=0.22.0",
"tree-sitter-cpp == 0.22.3",
"black >= 24.3.0",
"usort >= 1.0.8",
"setuptools >= 69.2.0",

2
suite/auto-sync/src/autosync/ASUpdater.py
View File

@ -216,7 +216,7 @@ def parse_args() -> argparse.Namespace:
"-a",
dest="arch",
help="Name of target architecture.",
choices=["ARM", "PPC", "AArch64", "Alpha", "LoongArch"],
choices=["ARM", "PPC", "AArch64", "Alpha", "LoongArch", "Mips"],
required=True,
)
parser.add_argument(

35
suite/auto-sync/src/autosync/MCUpdater.py
View File

@ -143,6 +143,8 @@ class TestFile:
text_section = 0 # Counts the .text sections
asm_pat = f"(?P<asm_text>.+)"
enc_pat = r"(\[?(?P<full_enc_string>(?P<enc_bytes>((0x[a-fA-F0-9]{1,2}[, ]{0,2}))+)[^, ]?)\]?)"
dups = []
for line in mc_output.stdout.splitlines():
line = line.decode("utf8")
if ".text" in line:
@ -166,6 +168,10 @@ class TestFile:
if not self.valid_byte_seq(enc_bytes):
continue
if (enc_bytes + asm_text) in dups:
continue
dups.append(enc_bytes + asm_text)
if text_section in self.tests:
if unified_test_cases:
self.tests[text_section][0].extend(enc_bytes, asm_text)
@ -262,6 +268,20 @@ class MCUpdater:
if self.arch in self.conf["mandatory_options"]
else list()
)
self.remove_options: str = (
self.conf["remove_options"][self.arch]
if self.arch in self.conf["remove_options"]
else list()
)
self.remove_options = [x.lower() for x in self.remove_options]
self.replace_option_map: str = (
self.conf["replace_option_map"][self.arch]
if self.arch in self.conf["replace_option_map"]
else {}
)
self.replace_option_map = {
k.lower(): v for k, v in self.replace_option_map.items()
}
self.multi_mode = multi_mode
def check_prerequisites(self, paths):
@ -331,17 +351,30 @@ class MCUpdater:
f"See also: https://github.com/capstone-engine/capstone/issues/1992"
)
def build_test_options(self, options):
new_options = [] + self.mandatory_options
for opt in options:
opt = opt.lower()
if opt in self.remove_options:
continue
elif opt in self.replace_option_map:
new_options.append(self.replace_option_map[opt])
else:
new_options.append(opt)
return new_options
def build_test_files(self, mc_cmds: list[LLVM_MC_Command]) -> list[TestFile]:
log.info("Build TestFile objects")
test_files = list()
n_all = len(mc_cmds)
for i, mcc in enumerate(mc_cmds):
print(f"{i + 1}/{n_all} {mcc.file.name}", flush=True, end="\r")
opts = self.build_test_options(mcc.get_opts_list())
test_files.append(
TestFile(
self.arch,
mcc.file,
mcc.get_opts_list() + self.mandatory_options,
opts,
mcc,
self.unified_test_cases,
)

6
suite/auto-sync/src/autosync/cpptranslator/Configurator.py
View File

@ -57,6 +57,12 @@ class Configurator:
self.load_config()
return self.config["General"]
def get_patch_config(self) -> dict:
if self.config:
return self.config["General"]["patching"]
self.load_config()
return self.config["General"]["patching"]
def load_config(self) -> None:
if not Path.exists(self.config_path):
fail_exit(f"Could not load arch config file at '{self.config_path}'")

30
suite/auto-sync/src/autosync/cpptranslator/CppTranslator.py
View File

@ -382,32 +382,16 @@ class Translator:
def apply_patch(self, patch: Patch) -> bool:
"""Tests if the given patch should be applied for the current architecture or file."""
has_apply_only = (
len(patch.apply_only_to["files"]) > 0
or len(patch.apply_only_to["archs"]) > 0
)
has_do_not_apply = (
len(patch.do_not_apply["files"]) > 0 or len(patch.do_not_apply["archs"]) > 0
)
if not (has_apply_only or has_do_not_apply):
# Lists empty.
apply_only_to = self.configurator.get_patch_config()["apply_patch_only_to"]
patch_name = patch.__class__.__name__
if patch_name not in apply_only_to:
# No constraints
return True
if has_apply_only:
if self.arch in patch.apply_only_to["archs"]:
return True
elif self.current_src_path_in.name in patch.apply_only_to["files"]:
return True
return False
elif has_do_not_apply:
if self.arch in patch.do_not_apply["archs"]:
return False
elif self.current_src_path_in.name in patch.do_not_apply["files"]:
return False
file_constraints = apply_only_to[patch_name]
if self.current_src_path_in.name in file_constraints["files"]:
return True
log.fatal("Logical error.")
exit(1)
return False
def translate(self) -> None:
for self.current_src_path_in, self.current_src_path_out in zip(

21
suite/auto-sync/src/autosync/cpptranslator/Differ.py
View File

@ -636,18 +636,21 @@ class Differ:
j = old_node_ids.index(self.cur_nid)
while j >= 0 and (old_node_ids[j] not in new_nodes.keys()):
j -= 1
ref_new: Node = (
new_nodes[old_node_ids[j]]
if old_node_ids[j] in new_nodes.keys()
else new_nodes[0]
)
ref_end_byte = ref_new.start_byte
if j < 0 or old_node_ids[j] not in new_nodes.keys():
# No new node exists before the old node.
# So just put it to the very beginning.
ref_end_byte = 1
ref_start_point = (1, 0)
else:
ref_new: Node = new_nodes[old_node_ids[j]]
ref_end_byte = ref_new.start_byte
ref_start_point = ref_new.start_point
# We always write to the new file. So we always take he coordinates form it.
patch_coord = PatchCoord(
ref_end_byte - 1,
ref_end_byte - 1,
ref_new.start_point,
ref_new.start_point,
ref_start_point,
ref_start_point,
)
save_exists = False
@ -922,7 +925,7 @@ def parse_args() -> argparse.Namespace:
"-a",
dest="arch",
help="Name of target architecture (ignored with -t option)",
choices=["ARM", "PPC", "AArch64", "Alpha", "LoongArch"],
choices=["ARM", "PPC", "AArch64", "Alpha", "LoongArch", "Mips"],
required=True,
)
parser.add_argument(

1
suite/auto-sync/src/autosync/cpptranslator/TemplateCollector.py
View File

@ -107,7 +107,6 @@ class TemplateCollector:
tree = self.parser.parse(src, keep_text=True)
query: Query = self.lang_cpp.query(self.get_template_pattern())
self.get_capture_bundles(query, tree)
capture_bundles = self.get_capture_bundles(query, tree)
for cb in capture_bundles:

25
suite/auto-sync/src/autosync/cpptranslator/Tests/Patches/test_arch_config.json
View File

@ -5,7 +5,30 @@
"diff_color_saved": "yellow",
"diff_color_edited": "light_magenta",
"patch_editor": "vim",
"nodes_to_diff": []
"nodes_to_diff": [],
"patching": {
"apply_patch_only_to": {
"AddCSDetail": {
"files": [
"ARMInstPrinter.cpp",
"PPCInstPrinter.cpp",
"AArch64InstPrinter.cpp",
"LoongArchInstPrinter.cpp",
"MipsInstPrinter.cpp"
]
},
"InlineToStaticInline": {
"files": [
"ARMAddressingModes.h"
]
},
"PrintRegImmShift": {
"files": [
"ARMInstPrinter.cpp"
]
}
}
}
},
"ARCH": {
"files_to_translate": [],

44
suite/auto-sync/src/autosync/cpptranslator/Tests/test_unit.py Normal file
View File

@ -0,0 +1,44 @@
# SPDX-FileCopyrightText: 2024 Rot127 <unisono@quyllur.org>
# SPDX-License-Identifier: BSD-3
import unittest
from pathlib import Path
from autosync.Helper import get_path
from autosync.cpptranslator import CppTranslator
from autosync.cpptranslator.Configurator import Configurator
from autosync.cpptranslator.patches.AddCSDetail import AddCSDetail
from autosync.cpptranslator.patches.InlineToStaticInline import InlineToStaticInline
from autosync.cpptranslator.patches.PrintRegImmShift import PrintRegImmShift
from autosync.cpptranslator.patches.Data import Data
class TestCppTranslator(unittest.TestCase):
@classmethod
def setUpClass(cls):
configurator = Configurator("ARCH", get_path("{PATCHES_TEST_CONFIG}"))
cls.translator = CppTranslator.Translator(configurator, False)
def test_patching_constraints(self):
self.translator.current_src_path_in = Path("Random_file.cpp")
patch_add_cs_detail = AddCSDetail(0, "ARCH")
patch_inline_to_static_inline = InlineToStaticInline(0)
patch_print_reg_imm_shift = PrintRegImmShift(0)
patch_data = Data(0)
self.assertFalse(self.translator.apply_patch(patch_add_cs_detail))
self.assertFalse(self.translator.apply_patch(patch_inline_to_static_inline))
self.assertFalse(self.translator.apply_patch(patch_print_reg_imm_shift))
self.assertTrue(self.translator.apply_patch(patch_data))
self.translator.current_src_path_in = Path("ARMInstPrinter.cpp")
self.assertTrue(self.translator.apply_patch(patch_add_cs_detail))
self.assertFalse(self.translator.apply_patch(patch_inline_to_static_inline))
self.assertTrue(self.translator.apply_patch(patch_print_reg_imm_shift))
self.assertTrue(self.translator.apply_patch(patch_data))
self.translator.current_src_path_in = Path("ARMAddressingModes.h")
self.assertFalse(self.translator.apply_patch(patch_add_cs_detail))
self.assertTrue(self.translator.apply_patch(patch_inline_to_static_inline))
self.assertFalse(self.translator.apply_patch(patch_print_reg_imm_shift))
self.assertTrue(self.translator.apply_patch(patch_data))

65
suite/auto-sync/src/autosync/cpptranslator/arch_config.json
View File

@ -5,6 +5,29 @@
"diff_color_saved": "yellow",
"diff_color_edited": "light_magenta",
"patch_editor": "vim",
"patching": {
"apply_patch_only_to": {
"AddCSDetail": {
"files": [
"ARMInstPrinter.cpp",
"PPCInstPrinter.cpp",
"AArch64InstPrinter.cpp",
"LoongArchInstPrinter.cpp",
"MipsInstPrinter.cpp"
]
},
"InlineToStaticInline": {
"files": [
"ARMAddressingModes.h"
]
},
"PrintRegImmShift": {
"files": [
"ARMInstPrinter.cpp"
]
}
}
},
"nodes_to_diff": [
{
"node_type": "function_definition",
@ -51,7 +74,7 @@
"{LLVM_ROOT}/llvm/lib/Target/ARM/Utils/ARMBaseInfo.h"
]
},
"PPC": {
"PPC": {
"files_to_translate": [
{
"in": "{LLVM_ROOT}/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp",
@ -147,7 +170,47 @@
"{LLVM_ROOT}/llvm/lib/Target/LoongArch/Disassembler/LoongArchDisassembler.cpp",
"{LLVM_ROOT}/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchInstPrinter.cpp"
],
"templates_with_arg_deduction": [],
"manually_edited_files": []
},
"Mips": {
"files_to_translate": [
{
"in": "{LLVM_ROOT}/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp",
"out": "MipsDisassembler.c"
},{
"in": "{LLVM_ROOT}/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.cpp",
"out": "MipsInstPrinter.c"
},{
"in": "{LLVM_ROOT}/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.h",
"out": "MipsInstPrinter.h"
}
],
"files_for_template_search": [
"{CPP_INC_OUT_DIR}/MipsGenDisassemblerTables.inc",
"{LLVM_ROOT}/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.cpp",
"{CPP_INC_OUT_DIR}/MipsGenAsmWriter.inc"
],
"templates_with_arg_deduction": [
"DecodeINSVE_DF",
"DecodeDAHIDATIMMR6",
"DecodeDAHIDATI",
"DecodeAddiGroupBranch",
"DecodePOP35GroupBranchMMR6",
"DecodeDaddiGroupBranch",
"DecodePOP37GroupBranchMMR6",
"DecodePOP65GroupBranchMMR6",
"DecodePOP75GroupBranchMMR6",
"DecodeBlezlGroupBranch",
"DecodeBgtzlGroupBranch",
"DecodeBgtzGroupBranch",
"DecodeBlezGroupBranch",
"DecodeBgtzGroupBranchMMR6",
"DecodeBlezGroupBranchMMR6",
"DecodeDINS",
"DecodeDEXT",
"DecodeCRC",
"isReg"
],
"manually_edited_files": []
}

24
suite/auto-sync/src/autosync/cpptranslator/patches/AddCSDetail.py
View File

@ -31,6 +31,7 @@ class AddCSDetail(Patch):
valid_param_lists = [
b"(MCInst*MI,unsignedOpNum,SStream*O)", # Default printOperand parameters.
b"(MCInst*MI,unsignedOpNo,SStream*O)", # ARM - printComplexRotationOp / PPC default
b"(MCInst*MI,intopNum,SStream *O)", # Mips - printMemOperandEA and others
b"(SStream*O,ARM_AM::ShiftOpcShOpc,unsignedShImm,boolgetUseMarkup())", # ARM - printRegImmShift
b"(MCInst*MI,unsignedOpNo,SStream*O,constchar*Modifier)", # PPC - printPredicateOperand
b"(MCInst*MI,uint64_tAddress,unsignedOpNo,SStream*O)", # PPC - printBranchOperand
@ -39,15 +40,6 @@ class AddCSDetail(Patch):
def __init__(self, priority: int, arch: str):
super().__init__(priority)
self.arch = arch
self.apply_only_to = {
"files": [
"ARMInstPrinter.cpp",
"PPCInstPrinter.cpp",
"AArch64InstPrinter.cpp",
"LoongArchInstPrinter.cpp",
],
"archs": list(),
}
def get_search_pattern(self) -> str:
return (
@ -88,11 +80,15 @@ class AddCSDetail(Patch):
) # Remove "print" from function id
is_template = fcn_def.prev_sibling.type == "template_parameter_list"
op_num_var_name = (
b"OpNum"
if b"OpNum" in params
else (b"OpNo" if b"OpNo" in params else b"-.-")
)
if b"OpNum" in params:
op_num_var_name = b"OpNum"
elif b"OpNo" in params:
op_num_var_name = b"OpNo"
elif b"opNum" in params:
op_num_var_name = b"opNum"
else:
raise ValueError("OpNum parameter could not be identified.")
if not is_template and op_num_var_name in params:
# Standard printOperand() parameters
mcinst_var = get_MCInst_var_name(src, fcn_def)

35
suite/auto-sync/src/autosync/cpptranslator/patches/FieldFromInstr.py
View File

@ -41,9 +41,9 @@ class FieldFromInstr(Patch):
# Determine width of instruction by the variable name.
if ffi_first_arg_text[-2:] == "32":
inst_width = 4
inst_width = b"4"
elif ffi_first_arg_text[-2:] == "16":
inst_width = 2
inst_width = b"2"
else:
# Get the Val/Inst parameter.
# Its type determines the instruction width.
@ -55,17 +55,38 @@ class FieldFromInstr(Patch):
inst_type = inst_param_text.split(b" ")[0]
if inst_type:
if inst_type in [b"unsigned", b"uint32_t"]:
inst_width = 4
inst_width = b"4"
elif inst_type in [b"uint16_t"]:
inst_width = 2
inst_width = b"2"
elif inst_type in [b"InsnType"]:
# Case means the decode function inherits the type from
# a template argument InsnType. The InsnType template argument
# is the type of integer holding the instruction bytes.
# This type is defined in ARCHDisassembler on calling the right macro.
# Hence, we do not know at this point of patching which type it might be.
# It needs to call fieldOfInstruction_X() which detects dynamically which
# integer type might hold the bytes (e.g. a uint32_t or uint16_t).
# You can check it manually in ARCHDisassembler.c, but the script can't.
#
# Here we just create a function with the postfix fieldFromInstruction_w (for width).
# This function must be implemented by hand, and check MCInst for the actual bit width.
# The bit width must be set in the ARCHDisassembler.c. Just add the code there by hand.
# Then call fieldFromInstruction_4, fieldFromInstruction_2 appropriately.
log.warning(
"Variable fieldFromInstruction width detected.\n"
"Please implement fieldFromInstruction_w() and call "
"fieldFromInstruction_4, fieldFromInstruction_2 appropriately.\n"
"In fieldFromInstruction_w() check MCInst for the actual bit width.\n"
"The bit width must be set in the ARCHDisassembler.c. Just add the code there by hand."
)
inst_width = b"w"
else:
log.fatal(f"Type {inst_type} no handled.")
exit(1)
raise ValueError(f"Type {inst_type} not handled.")
else:
# Needs manual fix
return get_text(src, ffi_call.start_byte, ffi_call.end_byte)
return re.sub(
rb"fieldFromInstruction",
b"fieldFromInstruction_%d" % inst_width,
b"fieldFromInstruction_%s" % inst_width,
get_text(src, ffi_call.start_byte, ffi_call.end_byte),
)

39
suite/auto-sync/src/autosync/cpptranslator/patches/Includes.py
View File

@ -64,6 +64,8 @@ class Includes(Patch):
return res + get_AArch64_includes(filename) + get_general_macros()
case "LoongArch":
return res + get_LoongArch_includes(filename) + get_general_macros()
case "Mips":
return res + get_Mips_includes(filename) + get_general_macros()
case "TEST_ARCH":
return res + b"test_output"
case _:
@ -294,6 +296,43 @@ def get_LoongArch_includes(filename: str) -> bytes:
exit(1)
def get_Mips_includes(filename: str) -> bytes:
match filename:
case "MipsDisassembler.cpp":
return (
b'#include "../../MCInst.h"\n'
+ b'#include "../../MathExtras.h"\n'
+ b'#include "../../MCInstPrinter.h"\n'
+ b'#include "../../MCDisassembler.h"\n'
+ b'#include "../../MCFixedLenDisassembler.h"\n'
+ b'#include "../../cs_priv.h"\n'
+ b'#include "../../utils.h"\n'
+ b"#define GET_SUBTARGETINFO_ENUM\n"
+ b'#include "MipsGenSubtargetInfo.inc"\n\n'
+ b"#define GET_INSTRINFO_ENUM\n"
+ b'#include "MipsGenInstrInfo.inc"\n\n'
+ b"#define GET_REGINFO_ENUM\n"
+ b'#include "MipsGenRegisterInfo.inc"\n\n'
)
case "MipsInstPrinter.cpp":
return (
b'#include "MipsMapping.h"\n'
+ b'#include "MipsInstPrinter.h"\n\n'
+ b"#define GET_SUBTARGETINFO_ENUM\n"
+ b'#include "MipsGenSubtargetInfo.inc"\n\n'
+ b"#define GET_INSTRINFO_ENUM\n"
+ b'#include "MipsGenInstrInfo.inc"\n\n'
+ b"#define GET_REGINFO_ENUM\n"
+ b'#include "MipsGenRegisterInfo.inc"\n\n'
)
case "MipsInstPrinter.h":
return (
b'#include "../../MCInstPrinter.h"\n' + b'#include "../../cs_priv.h"\n'
)
log.fatal(f"No includes given for Mips source file: {filename}")
exit(1)
def get_general_macros():
return (
b"#define CONCAT(a, b) CONCAT_(a, b)\n" b"#define CONCAT_(a, b) a ## _ ## b\n"

1
suite/auto-sync/src/autosync/cpptranslator/patches/InlineToStaticInline.py
View File

@ -19,7 +19,6 @@ class InlineToStaticInline(Patch):
def __init__(self, priority: int):
super().__init__(priority)
self.apply_only_to = {"files": ["ARMAddressingModes.h"], "archs": list()}
def get_search_pattern(self) -> str:
return (

11
suite/auto-sync/src/autosync/cpptranslator/patches/Patch.py
View File

@ -9,17 +9,6 @@ from tree_sitter import Node
class Patch:
priority: int = None
# List of filenames and architectures this patch applies to or not.
# Order of testing:
# 1. apply_only_to.archs
# 2. apply_only_to.files
# 3. do_not_apply.archs
# 4. do_not_apply.files
# Contains the _in_ filenames and architectures this patch should be applied to. Empty list means all.
apply_only_to = {"files": list(), "archs": list()}
# Contains the _in_ filenames and architectures this patch should NOT be applied to.
do_not_apply = {"files": list(), "archs": list()}
def __init__(self, priority: int = 0):
self.priority = priority

882
suite/auto-sync/src/autosync/cpptranslator/saved_patches.json
View File

@ -2408,5 +2408,887 @@
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"DecodeGPRNM1R1RegisterClass": {
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"DecodeGPRNM32NZRegisterClass": {
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"DecodeGPRNM3RegisterClass": {
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"DecodeHI32DSPRegisterClass": {
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"DecodeINSVE_DF": {
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"DecodeInsSize": {
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"DecodeJumpTargetXMM": {
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"DecodeLO32DSPRegisterClass": {
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"DecodeLoadByte15": {
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"DecodeMSA128BRegisterClass": {
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"DecodeMSA128Mem": {
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"DecodeMSA128WRegisterClass": {
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"DecodeMSACtrlRegisterClass": {
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"DecodeMem": {
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"DecodeMemEVA": {
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"DecodeMemMMGPImm7Lsl2": {
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"DecodeMemMMImm12": {
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"DecodeMemMMImm16": {
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"DecodeMemMMImm4": {
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"DecodeMemMMImm9": {
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"DecodeMemMMReglistImm4Lsl2": {
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"DecodeMemMMSPImm5Lsl2": {
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"DecodeMemNM4x4": {
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"DecodeMemZeroNM": {
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"DecodeMovePOperands": {
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"DecodeNMRegList16Operand": {
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"DecodeNMRegListOperand": {
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"DecodeNegImm12": {
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"DecodePOP35GroupBranchMMR6": {
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"DecodePOP37GroupBranchMMR6": {
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"DecodePOP65GroupBranchMMR6": {
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"DecodePOP75GroupBranchMMR6": {
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"DecodePrefeOpMM": {
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"DecodePtrRegisterClass": {
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"DecodeRegListOperand": {
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"DecodeRegListOperand16": {
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"DecodeSImm32s12": {
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"DecodeSimm18Lsl3": {
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"DecodeSimm19Lsl2": {
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"DecodeSimm23Lsl2": {
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"DecodeSimm9SP": {
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"DecodeSpecial3LlSc": {
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"DecodeSyncI": {
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"DecodeSyncI_MM": {
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"DecodeSynciR6": {
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"Mips_LLVM_getInstruction": {
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"Mips_getFeatureBits": {
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"createMipsDisassembler": {
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"createMipselDisassembler": {
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"getInstruction": {
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"getReg": {
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"readInstruction16": {
"apply_type": "OLD",
"old_hash": "97a35e0038b8c65211b379e4056300253388880078f294554a66c24ad9098838",
"new_hash": "b557ab16a7fbf7deae9d94d0d0c27e0763c4aff63e7df8a26c25c2a9b574e24d",
"edit": ""
},
"readInstruction32": {
"apply_type": "OLD",
"old_hash": "2c457bf651fe2170716e5db95b8f674e5b14c03e694a58832a47f543ade71687",
"new_hash": "b0605f16c54c20bdef3619448a56a99552a8b83c46f70b15b0fce4daa9023368",
"edit": ""
},
"readInstruction48": {
"apply_type": "OLD",
"old_hash": "52da39fa622a75b02161317d6bd93b17bcca0fa9691e251e79fe4bb63f67785c",
"new_hash": "f680512de5c7f01db4fff30c051dbd924d9414b2111b2a9e40bd520e829588e4",
"edit": ""
}
},
"MipsInstPrinter.c": {
"DEFINE_printUImm": {
"apply_type": "OLD",
"old_hash": "53ae0f1c9bc04d13f0d04872cf7967f3240239de0167e89a7bbb9c88f9693d7a",
"new_hash": "facdff402f9d252c808d90a54209081ef8cb55d89a44e0416f3e1b2f8875a925",
"edit": ""
},
"DEFINE_printUImm_2": {
"apply_type": "OLD",
"old_hash": "6c19b6355fa6035f8c5ed42c829539e439024448c2cbb29673edafd6a2a52167",
"new_hash": "",
"edit": ""
},
"MipsFCCToString": {
"apply_type": "OLD",
"old_hash": "7182d974e8a5d575736c86cc7a88bf59ff0bbae99cde83a72a4befeacae0b192",
"new_hash": "d2442362ae7a9c5a3edaecfacb6b2f198b4a64ab892eb8f4c94ca4164ce6df64",
"edit": ""
},
"Mips_LLVM_getRegisterName": {
"apply_type": "OLD",
"old_hash": "df6019c36822141534647a1401f2ad35a93afd55850942f97b9142eb8c40f832",
"new_hash": "",
"edit": ""
},
"Mips_LLVM_printInst": {
"apply_type": "OLD",
"old_hash": "660b5eba392f6b7738cb3f241e8ff34f2a0137b12c7ca36b1ccbe0832d345d1d",
"new_hash": "",
"edit": ""
},
"isReg": {
"apply_type": "OLD",
"old_hash": "34203d392642dffc6802f8b83461970f5a2b494c0161e55e200b8c2c6bf7a54b",
"new_hash": "97981713a49723ff8194dffcb4cae77b8da54a5467320dbace0e30dcca3f62c2",
"edit": ""
},
"printAlias": {
"apply_type": "OLD",
"old_hash": "3e91b4b218d68fbf5862e6f714320bf0c0292c1fe31fc039a1e2aac5b876d67b",
"new_hash": "",
"edit": ""
},
"printAlias2": {
"apply_type": "OLD",
"old_hash": "6e3b2448fb62f2bbd6684652184b4e5adcba323318d73b7ee4aef4acc896f4c9",
"new_hash": "",
"edit": ""
},
"printAlias3": {
"apply_type": "OLD",
"old_hash": "4eb79f76f7d84a89fb7db7259c2ba8903f0a426b0827da757338cf4a76686fa0",
"new_hash": "",
"edit": ""
},
"printAlias4": {
"apply_type": "OLD",
"old_hash": "68e131d12b29b480dd0981ae73566892486f6cb947b9bc3d737801eed2a37808",
"new_hash": "",
"edit": ""
},
"printAliasHex": {
"apply_type": "OLD",
"old_hash": "",
"new_hash": "1dd77aad2f90881b3df09dff4b624a3f1bd7842c59ed9215d8f864ed57edf69a",
"edit": ""
},
"printBranchOperand": {
"apply_type": "OLD",
"old_hash": "55c249da72a1afe6c1fffa0df01e2f152b00e8db92b3bdff098c64021e639e07",
"new_hash": "ae3c09e80b494cf5f50f5635c100acc19e0aa2dbe45cc30fab652337deb35d03",
"edit": ""
},
"printFCCOperand": {
"apply_type": "OLD",
"old_hash": "dca2d4e01ca07a1058df9e3b624aca7c56aece157c137d16cc709ac2e68ac3ba",
"new_hash": "d9c750542ff035652477778a34d7892f881088172d2787dd455320acb0334a5c",
"edit": ""
},
"printHi20": {
"apply_type": "OLD",
"old_hash": "2964fb32cbd0f9508d6f62a372211f396eb11642f0e8ae3e8e2bf6926f090ada",
"new_hash": "2e048e424a08cb5f6781d7d92a507e111452ea34d0a2fbe8545716c6d3fdd70c",
"edit": ""
},
"printHi20PCRel": {
"apply_type": "OLD",
"old_hash": "1e501b0a3f2fd3556a6ba59dcb70ea2b5de37060390d628e952f2fec787360eb",
"new_hash": "d5f95f06aba32b0f3a2920b319c33e69ec3ec1598a35b2462df419aa9a6841a6",
"edit": ""
},
"printInst": {
"apply_type": "OLD",
"old_hash": "",
"new_hash": "3aec06d252656b5d52191046737785e713ba284069d7877b347c94e25b02a546",
"edit": ""
},
"printJumpOperand": {
"apply_type": "OLD",
"old_hash": "6d084ada9b6feec97e1548800407bbbe428a8787c514992d9bf8efd73176f717",
"new_hash": "844ffab898f4ad38b9b9467897583d1b6c65cebdae729df0412af73537c97e64",
"edit": ""
},
"printMemOperand": {
"apply_type": "OLD",
"old_hash": "0bee738dab28731710512bf16fa03f31f10209f777cea83f0d16aa66412e6201",
"new_hash": "b23d985030fe56708a6cb5bb6a433c24fbca10e89f094a24ebfeae33b65af0d3",
"edit": ""
},
"printMemOperandEA": {
"apply_type": "OLD",
"old_hash": "0629eed2d2eee3a553c38cb62077ce29e4398f601afa06d0233f4cf70c976cea",
"new_hash": "615aacb0ba3bb7bc63c827aaef822bfb7552b9688408181f819a8aaa388dd123",
"edit": ""
},
"printMemOperandGPRel": {
"apply_type": "OLD",
"old_hash": "",
"new_hash": "03a58352102b07f37da60354963648a2d0c383bfb3755aa06a33b85a0b81364c",
"edit": ""
},
"printNanoMipsRegisterList": {
"apply_type": "OLD",
"old_hash": "d5e6ad71c9661c2996c8d3fd158d854c7968d994c2443cbb87db4eaf27b38602",
"new_hash": "93f0b35923e7f7079d1a4ad82b9b7bcf75f61bfa7c8b77f745954be739771e0d",
"edit": ""
},
"printOperand": {
"apply_type": "OLD",
"old_hash": "f82a0d318d803c5e649a76333382391aaf33a5f70111d8097fd1a0e29806f25b",
"new_hash": "2b2d943eefb4583bd34b5019b60892078c38b58e9304d63927d9034ce5d8b2a9",
"edit": ""
},
"printPCRel": {
"apply_type": "OLD",
"old_hash": "cbea0cd3eeece2e8e35a20a198c68f9dc8768e85225e71c22ec0b41a6fdd45e7",
"new_hash": "56fa496c7e24b743f39d041a74c8625d8c513c239112aff9b2097b5f9365ff46",
"edit": ""
},
"printRegName": {
"apply_type": "OLD",
"old_hash": "2bb60804f739dbad89ceadcea389c7b4151a11feac690098942a28fc56288beb",
"new_hash": "229be3874bde1bf33bc0120c4b8c6134d789903c49fe21b2e3d33a4185854357",
"edit": ""
},
"printRegisterList": {
"apply_type": "OLD",
"old_hash": "cbdbe99cacca7a7173ff929ef118be9f3968b1619c58f3f3cb20000a223d3770",
"new_hash": "774bbb5782799c798145d78be150dc2b2c7016ebf4723988122610d034402ada",
"edit": ""
},
"printSHFMask": {
"apply_type": "OLD",
"old_hash": "",
"new_hash": "6a1963dc458109069478f4474a8158a025c3177263daac00c45504d5da042391",
"edit": ""
},
"printSaveRestore": {
"apply_type": "OLD",
"old_hash": "",
"new_hash": "f5c17b2b290fa440877c0b85c85bcc9b050891db002932e0c6448b7f5649339d",
"edit": ""
}
},
"MipsInstPrinter.h": {
"DECLARE_printUImm": {
"apply_type": "OLD",
"old_hash": "faefa6d7d623550d91fcf096238173c734b43b0717806ce8313f4c4ffb549cd8",
"new_hash": "6bae637a74ba6624001e568e7b960417c99cd2b8fa2d310bc30b1328585cd223",
"edit": ""
},
"DECLARE_printUImm_2": {
"apply_type": "OLD",
"old_hash": "81028329d6713020ee9beb36a8a459f2672dd35838aa2f682f74407c9dda8dc0",
"new_hash": "",
"edit": ""
}
}
}

87
suite/auto-sync/src/autosync/mcupdater.json
View File

@ -1,10 +1,79 @@
{
"additional_mattr":
{
"AArch64": [ "+all" ]
},
"mandatory_options":
{
"SystemZ": [ "CS_MODE_BIG_ENDIAN" ]
}
}
"additional_mattr":
{
"AArch64":
[
"+all"
]
},
"mandatory_options":
{
"SystemZ":
[
"CS_MODE_BIG_ENDIAN"
],
"Mips":
[
"CS_OPT_SYNTAX_NOREGNAME"
]
},
"remove_options":
{
"Mips":
[
"mips",
"dsp",
"dspr2",
"dspr3",
"mips3d",
"msa",
"eva",
"crc",
"virt",
"ginv",
"fp64",
"+virt",
"mt"
]
},
"replace_option_map":
{
"Mips":
{
"mips-unknown-linux": "CS_MODE_BIG_ENDIAN",
"mips-unknown-linux-gnu": "CS_MODE_BIG_ENDIAN",
"mips32-unknown-linux": "CS_MODE_BIG_ENDIAN",
"mips64-unknown-linux": "CS_MODE_BIG_ENDIAN",
"mips64-unknown-linux-gnu": "CS_MODE_BIG_ENDIAN",
"mips64el-unknown-linux": "CS_MODE_LITTLE_ENDIAN",
"mips64el-unknown-linux-gnu": "CS_MODE_LITTLE_ENDIAN",
"mipsel": "CS_MODE_LITTLE_ENDIAN",
"mipsel-unknown-linux": "CS_MODE_LITTLE_ENDIAN",
"mipsel-unknown-linux-gnu": "CS_MODE_LITTLE_ENDIAN",
"mips16": "CS_MODE_MIPS16",
"mips32": "CS_MODE_MIPS32",
"mips64": "CS_MODE_MIPS64",
"micromips": "CS_MODE_MICRO",
"mips1": "CS_MODE_MIPS1",
"mips2": "CS_MODE_MIPS2",
"mips32r2": "CS_MODE_MIPS32R2",
"mips32r3": "CS_MODE_MIPS32R3",
"mips32r5": "CS_MODE_MIPS32R5",
"mips32r6": "CS_MODE_MIPS32R6",
"mips3": "CS_MODE_MIPS3",
"mips4": "CS_MODE_MIPS4",
"mips5": "CS_MODE_MIPS5",
"mips64r2": "CS_MODE_MIPS64R2",
"mips64r3": "CS_MODE_MIPS64R3",
"mips64r5": "CS_MODE_MIPS64R5",
"mips64r6": "CS_MODE_MIPS64R6",
"octeon": "CS_MODE_OCTEON",
"octeon+": "CS_MODE_OCTEONP",
"nanomips": "CS_MODE_NANOMIPS",
"nms1": "CS_MODE_NMS1",
"i7200": "CS_MODE_I7200",
"mips_nofloat": "CS_MODE_MIPS_NOFLOAT",
"mips_ptr64": "CS_MODE_MIPS_PTR64"
}
}
}

20
suite/cstest/include/test_mapping.h
View File

@ -73,6 +73,7 @@ static const cs_enum_id_map test_mode_map[] = {
{ .str = "CS_MODE_HPPA_11", .val = CS_MODE_HPPA_11 },
{ .str = "CS_MODE_HPPA_20", .val = CS_MODE_HPPA_20 },
{ .str = "CS_MODE_HPPA_20W", .val = CS_MODE_HPPA_20W },
{ .str = "CS_MODE_I7200", .val = CS_MODE_I7200 },
{ .str = "CS_MODE_LITTLE_ENDIAN", .val = CS_MODE_LITTLE_ENDIAN },
{ .str = "CS_MODE_LOONGARCH32", .val = CS_MODE_LOONGARCH32 },
{ .str = "CS_MODE_LOONGARCH64", .val = CS_MODE_LOONGARCH64 },
@ -94,11 +95,26 @@ static const cs_enum_id_map test_mode_map[] = {
{ .str = "CS_MODE_M68K_060", .val = CS_MODE_M68K_060 },
{ .str = "CS_MODE_MCLASS", .val = CS_MODE_MCLASS },
{ .str = "CS_MODE_MICRO", .val = CS_MODE_MICRO },
{ .str = "CS_MODE_MICRO32R3", .val = CS_MODE_MICRO32R3 },
{ .str = "CS_MODE_MICRO32R6", .val = CS_MODE_MICRO32R6 },
{ .str = "CS_MODE_MIPS1", .val = CS_MODE_MIPS1 },
{ .str = "CS_MODE_MIPS16", .val = CS_MODE_MIPS16 },
{ .str = "CS_MODE_MIPS2", .val = CS_MODE_MIPS2 },
{ .str = "CS_MODE_MIPS3", .val = CS_MODE_MIPS3 },
{ .str = "CS_MODE_MIPS32", .val = CS_MODE_MIPS32 },
{ .str = "CS_MODE_MIPS32R2", .val = CS_MODE_MIPS32R2 },
{ .str = "CS_MODE_MIPS32R3", .val = CS_MODE_MIPS32R3 },
{ .str = "CS_MODE_MIPS32R5", .val = CS_MODE_MIPS32R5 },
{ .str = "CS_MODE_MIPS32R6", .val = CS_MODE_MIPS32R6 },
{ .str = "CS_MODE_MIPS4", .val = CS_MODE_MIPS4 },
{ .str = "CS_MODE_MIPS5", .val = CS_MODE_MIPS5 },
{ .str = "CS_MODE_MIPS64", .val = CS_MODE_MIPS64 },
{ .str = "CS_MODE_MIPS64R2", .val = CS_MODE_MIPS64R2 },
{ .str = "CS_MODE_MIPS64R3", .val = CS_MODE_MIPS64R3 },
{ .str = "CS_MODE_MIPS64R5", .val = CS_MODE_MIPS64R5 },
{ .str = "CS_MODE_MIPS64R6", .val = CS_MODE_MIPS64R6 },
{ .str = "CS_MODE_MIPS_NOFLOAT", .val = CS_MODE_MIPS_NOFLOAT },
{ .str = "CS_MODE_MIPS_PTR64", .val = CS_MODE_MIPS_PTR64 },
{ .str = "CS_MODE_MOS65XX_6502", .val = CS_MODE_MOS65XX_6502 },
{ .str = "CS_MODE_MOS65XX_65816", .val = CS_MODE_MOS65XX_65816 },
{ .str = "CS_MODE_MOS65XX_65816_LONG_M",
@ -109,6 +125,10 @@ static const cs_enum_id_map test_mode_map[] = {
.val = CS_MODE_MOS65XX_65816_LONG_X },
{ .str = "CS_MODE_MOS65XX_65C02", .val = CS_MODE_MOS65XX_65C02 },
{ .str = "CS_MODE_MOS65XX_W65C02", .val = CS_MODE_MOS65XX_W65C02 },
{ .str = "CS_MODE_NANOMIPS", .val = CS_MODE_NANOMIPS },
{ .str = "CS_MODE_NMS1", .val = CS_MODE_NMS1 },
{ .str = "CS_MODE_OCTEON", .val = CS_MODE_OCTEON },
{ .str = "CS_MODE_OCTEONP", .val = CS_MODE_OCTEONP },
{ .str = "CS_MODE_PS", .val = CS_MODE_PS },
{ .str = "CS_MODE_QPX", .val = CS_MODE_QPX },
{ .str = "CS_MODE_RISCV32", .val = CS_MODE_RISCV32 },

19
suite/cstest/src/test_run.c
View File

@ -102,17 +102,18 @@ static bool parse_input_options(const TestInput *input, cs_arch *arch,
}
*mode = 0;
bool mode_found = false;
size_t opt_idx = 0;
char **options = input->options;
for (size_t i = 0; i < input->options_count; ++i) {
bool opt_found = false;
opt_str = options[i];
val = enum_map_bin_search(test_mode_map,
ARR_SIZE(test_mode_map), opt_str,
&mode_found);
if (mode_found) {
ARR_SIZE(test_mode_map),
opt_str, &opt_found);
if (opt_found) {
*mode |= val;
goto next_option;
continue;
}
// Might be an option descriptor
@ -126,12 +127,12 @@ static bool parse_input_options(const TestInput *input, cs_arch *arch,
return false;
}
opt_arr[opt_idx++] = test_option_map[k].opt;
goto next_option;
opt_found = true;
}
}
fprintf(stderr, "[!] Option: '%s' not used\n", opt_str);
next_option:
continue;
if (!opt_found) {
fprintf(stderr, "[!] Option: '%s' not used\n", opt_str);
}
}
*opt_set = opt_idx;
return true;

70
tests/MC/Mips/invalid-xfail.txt.yaml Normal file
View File

@ -0,0 +1,70 @@
test_cases:
-
input:
bytes: [ 0x00, 0x00, 0x00, 0x00 ]
arch: "CS_ARCH_MIPS"
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ]
expected:
insns:
-
asm_text: "nop"
-
input:
bytes: [ 0x45, 0x06, 0x00, 0x83 ]
arch: "CS_ARCH_MIPS"
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ]
expected:
insns:
-
asm_text: "bc1fl $fcc1, 528"
-
input:
bytes: [ 0x45, 0x07, 0xd8, 0x02 ]
arch: "CS_ARCH_MIPS"
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ]
expected:
insns:
-
asm_text: "bc1tl $fcc1, -40948"
-
input:
bytes: [ 0x45, 0x08, 0x14, 0x03 ]
arch: "CS_ARCH_MIPS"
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ]
expected:
insns:
-
asm_text: "bc1f $fcc2, 20496"
-
input:
bytes: [ 0x45, 0x09, 0x01, 0x02 ]
arch: "CS_ARCH_MIPS"
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ]
expected:
insns:
-
asm_text: "bc1t $fcc2, 1036"
-
input:
bytes: [ 0x48, 0x00, 0x00, 0x01 ]
arch: "CS_ARCH_MIPS"
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ]
expected:
insns:
-
asm_text: "mfc2 $zero, $0, 1"
-
input:
bytes: [ 0x48, 0x86, 0x00, 0x04 ]
arch: "CS_ARCH_MIPS"
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64R5" ]
expected:
insns:
-
asm_text: "mtc2 $6, $0, 4"

10
tests/MC/Mips/invalid.txt.yaml Normal file
View File

@ -0,0 +1,10 @@
test_cases:
-
input:
bytes: [ 0x00, 0x00, 0x00, 0x00 ]
arch: "CS_ARCH_MIPS"
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS1" ]
expected:
insns:
-
asm_text: "nop"

380
tests/MC/Mips/mftr-mttr-aliases.s.yaml Normal file
View File

@ -0,0 +1,380 @@
test_cases:
-
input:
bytes: [ 0x41, 0x05, 0x20, 0x00 ]
arch: "CS_ARCH_MIPS"
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ]
expected:
insns:
-
asm_text: "mftr $4, $5, 0, 0, 0"
-
input:
bytes: [ 0x41, 0x07, 0x30, 0x01 ]
arch: "CS_ARCH_MIPS"
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ]
expected:
insns:
-
asm_text: "mftr $6, $7, 0, 1, 0"
-
input:
bytes: [ 0x41, 0x09, 0x28, 0x20 ]
arch: "CS_ARCH_MIPS"
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ]
expected:
insns:
-
asm_text: "mftr $5, $9, 1, 0, 0"
-
input:
bytes: [ 0x41, 0x00, 0x18, 0x21 ]
arch: "CS_ARCH_MIPS"
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ]
expected:
insns:
-
asm_text: "mftr $3, $zero, 1, 1, 0"
-
input:
bytes: [ 0x41, 0x04, 0x18, 0x21 ]
arch: "CS_ARCH_MIPS"
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ]
expected:
insns:
-
asm_text: "mftr $3, $4, 1, 1, 0"
-
input:
bytes: [ 0x41, 0x08, 0x18, 0x21 ]
arch: "CS_ARCH_MIPS"
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ]
expected:
insns:
-
asm_text: "mftr $3, $8, 1, 1, 0"
-
input:
bytes: [ 0x41, 0x0c, 0x18, 0x21 ]
arch: "CS_ARCH_MIPS"
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ]
expected:
insns:
-
asm_text: "mftr $3, $12, 1, 1, 0"
-
input:
bytes: [ 0x41, 0x01, 0x18, 0x21 ]
arch: "CS_ARCH_MIPS"
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ]
expected:
insns:
-
asm_text: "mftr $3, $1, 1, 1, 0"
-
input:
bytes: [ 0x41, 0x05, 0x18, 0x21 ]
arch: "CS_ARCH_MIPS"
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ]
expected:
insns:
-
asm_text: "mftr $3, $5, 1, 1, 0"
-
input:
bytes: [ 0x41, 0x09, 0x18, 0x21 ]
arch: "CS_ARCH_MIPS"
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ]
expected:
insns:
-
asm_text: "mftr $3, $9, 1, 1, 0"
-
input:
bytes: [ 0x41, 0x0d, 0x18, 0x21 ]
arch: "CS_ARCH_MIPS"
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ]
expected:
insns:
-
asm_text: "mftr $3, $13, 1, 1, 0"
-
input:
bytes: [ 0x41, 0x02, 0x18, 0x21 ]
arch: "CS_ARCH_MIPS"
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ]
expected:
insns:
-
asm_text: "mftr $3, $2, 1, 1, 0"
-
input:
bytes: [ 0x41, 0x06, 0x18, 0x21 ]
arch: "CS_ARCH_MIPS"
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ]
expected:
insns:
-
asm_text: "mftr $3, $6, 1, 1, 0"
-
input:
bytes: [ 0x41, 0x0a, 0x18, 0x21 ]
arch: "CS_ARCH_MIPS"
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ]
expected:
insns:
-
asm_text: "mftr $3, $10, 1, 1, 0"
-
input:
bytes: [ 0x41, 0x0e, 0x18, 0x21 ]
arch: "CS_ARCH_MIPS"
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ]
expected:
insns:
-
asm_text: "mftr $3, $14, 1, 1, 0"
-
input:
bytes: [ 0x41, 0x10, 0x20, 0x21 ]
arch: "CS_ARCH_MIPS"
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ]
expected:
insns:
-
asm_text: "mftr $4, $16, 1, 1, 0"
-
input:
bytes: [ 0x41, 0x05, 0x20, 0x22 ]
arch: "CS_ARCH_MIPS"
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ]
expected:
insns:
-
asm_text: "mftr $4, $5, 1, 2, 0"
-
input:
bytes: [ 0x41, 0x05, 0x20, 0x32 ]
arch: "CS_ARCH_MIPS"
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ]
expected:
insns:
-
asm_text: "mftr $4, $5, 1, 2, 1"
-
input:
bytes: [ 0x41, 0x09, 0x20, 0x23 ]
arch: "CS_ARCH_MIPS"
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ]
expected:
insns:
-
asm_text: "mftr $4, $9, 1, 3, 0"
-
input:
bytes: [ 0x41, 0x84, 0x28, 0x00 ]
arch: "CS_ARCH_MIPS"
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ]
expected:
insns:
-
asm_text: "mttr $4, $5, 0, 0, 0"
-
input:
bytes: [ 0x41, 0x86, 0x38, 0x01 ]
arch: "CS_ARCH_MIPS"
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ]
expected:
insns:
-
asm_text: "mttr $6, $7, 0, 1, 0"
-
input:
bytes: [ 0x41, 0x85, 0x48, 0x20 ]
arch: "CS_ARCH_MIPS"
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ]
expected:
insns:
-
asm_text: "mttr $5, $9, 1, 0, 0"
-
input:
bytes: [ 0x41, 0x83, 0x00, 0x21 ]
arch: "CS_ARCH_MIPS"
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ]
expected:
insns:
-
asm_text: "mttr $3, $zero, 1, 1, 0"
-
input:
bytes: [ 0x41, 0x83, 0x20, 0x21 ]
arch: "CS_ARCH_MIPS"
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ]
expected:
insns:
-
asm_text: "mttr $3, $4, 1, 1, 0"
-
input:
bytes: [ 0x41, 0x83, 0x40, 0x21 ]
arch: "CS_ARCH_MIPS"
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ]
expected:
insns:
-
asm_text: "mttr $3, $8, 1, 1, 0"
-
input:
bytes: [ 0x41, 0x83, 0x60, 0x21 ]
arch: "CS_ARCH_MIPS"
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ]
expected:
insns:
-
asm_text: "mttr $3, $12, 1, 1, 0"
-
input:
bytes: [ 0x41, 0x83, 0x08, 0x21 ]
arch: "CS_ARCH_MIPS"
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ]
expected:
insns:
-
asm_text: "mttr $3, $1, 1, 1, 0"
-
input:
bytes: [ 0x41, 0x83, 0x28, 0x21 ]
arch: "CS_ARCH_MIPS"
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ]
expected:
insns:
-
asm_text: "mttr $3, $5, 1, 1, 0"
-
input:
bytes: [ 0x41, 0x83, 0x48, 0x21 ]
arch: "CS_ARCH_MIPS"
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ]
expected:
insns:
-
asm_text: "mttr $3, $9, 1, 1, 0"
-
input:
bytes: [ 0x41, 0x83, 0x68, 0x21 ]
arch: "CS_ARCH_MIPS"
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ]
expected:
insns:
-
asm_text: "mttr $3, $13, 1, 1, 0"
-
input:
bytes: [ 0x41, 0x83, 0x10, 0x21 ]
arch: "CS_ARCH_MIPS"
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ]
expected:
insns:
-
asm_text: "mttr $3, $2, 1, 1, 0"
-
input:
bytes: [ 0x41, 0x83, 0x30, 0x21 ]
arch: "CS_ARCH_MIPS"
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ]
expected:
insns:
-
asm_text: "mttr $3, $6, 1, 1, 0"
-
input:
bytes: [ 0x41, 0x83, 0x50, 0x21 ]
arch: "CS_ARCH_MIPS"
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ]
expected:
insns:
-
asm_text: "mttr $3, $10, 1, 1, 0"
-
input:
bytes: [ 0x41, 0x83, 0x70, 0x21 ]
arch: "CS_ARCH_MIPS"
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ]
expected:
insns:
-
asm_text: "mttr $3, $14, 1, 1, 0"
-
input:
bytes: [ 0x41, 0x84, 0x80, 0x21 ]
arch: "CS_ARCH_MIPS"
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ]
expected:
insns:
-
asm_text: "mttr $4, $16, 1, 1, 0"
-
input:
bytes: [ 0x41, 0x84, 0x28, 0x22 ]
arch: "CS_ARCH_MIPS"
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ]
expected:
insns:
-
asm_text: "mttr $4, $5, 1, 2, 0"
-
input:
bytes: [ 0x41, 0x84, 0x28, 0x32 ]
arch: "CS_ARCH_MIPS"
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ]
expected:
insns:
-
asm_text: "mttr $4, $5, 1, 2, 1"
-
input:
bytes: [ 0x41, 0x84, 0x48, 0x23 ]
arch: "CS_ARCH_MIPS"
options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS32R2" ]
expected:
insns:
-
asm_text: "mttr $4, $9, 1, 3, 0"

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