mirror of
https://github.com/capstone-engine/capstone.git
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arm64: sync with LLVM 7.0.1
This commit is contained in:
Nguyen Anh Quynh
parent
caa4a98e34
commit
9d292268a9
@ -164,27 +164,21 @@ if (NOT CAPSTONE_X86_ONLY AND CAPSTONE_ARM64_SUPPORT)
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arch/AArch64/AArch64AddressingModes.h
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arch/AArch64/AArch64BaseInfo.h
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arch/AArch64/AArch64Disassembler.h
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arch/AArch64/AArch64InstPrinter.h
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arch/AArch64/AArch64Mapping.h
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arch/AArch64/AArch64GenAsmWriter.inc
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arch/AArch64/AArch64GenDisassemblerTables.inc
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arch/AArch64/AArch64GenInstrInfo.inc
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arch/AArch64/AArch64GenRegisterInfo.inc
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arch/AArch64/AArch64GenRegisterName.inc
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arch/AArch64/AArch64GenRegisterV.inc
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arch/AArch64/AArch64GenSubtargetInfo.inc
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arch/AArch64/AArch64InstPrinter.h
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arch/AArch64/AArch64Mapping.h
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arch/AArch64/AArch64GenSystemOperands.inc
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arch/AArch64/AArch64GenSystemOperands_enum.inc
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arch/AArch64/AArch64MappingInsn.inc
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)
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set(HEADERS_ARM64
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arch/AArch64/AArch64AddressingModes.h
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arch/AArch64/AArch64BaseInfo.h
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arch/AArch64/AArch64Disassembler.h
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arch/AArch64/AArch64GenAsmWriter.inc
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arch/AArch64/AArch64GenDisassemblerTables.inc
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arch/AArch64/AArch64GenInstrInfo.inc
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arch/AArch64/AArch64GenRegisterInfo.inc
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arch/AArch64/AArch64GenSubtargetInfo.inc
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arch/AArch64/AArch64InstPrinter.h
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arch/AArch64/AArch64Mapping.h
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)
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arch/AArch64/AArch64MappingInsnName.inc
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arch/AArch64/AArch64MappingInsnOp.inc
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)
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set(TEST_SOURCES ${TEST_SOURCES} test_arm64.c)
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endif ()
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@ -26,6 +26,13 @@
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typedef uint16_t MCPhysReg;
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typedef const MCPhysReg* iterator;
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typedef struct MCRegisterClass2 {
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iterator RegsBegin;
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const uint8_t *RegSet;
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uint8_t RegsSize;
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uint8_t RegSetSize;
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} MCRegisterClass2;
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typedef struct MCRegisterClass {
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iterator RegsBegin;
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const uint8_t *RegSet;
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@ -39,6 +39,15 @@ void SStream_concat0(SStream *ss, const char *s)
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#endif
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}
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void SStream_concat1(SStream *ss, const char c)
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{
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#ifndef CAPSTONE_DIET
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ss->buffer[ss->index] = c;
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ss->index++;
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ss->buffer[ss->index] = '\0';
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#endif
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}
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void SStream_concat(SStream *ss, const char *fmt, ...)
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{
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#ifndef CAPSTONE_DIET
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@ -17,6 +17,8 @@ void SStream_concat(SStream *ss, const char *fmt, ...);
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void SStream_concat0(SStream *ss, const char *s);
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void SStream_concat1(SStream *ss, const char c);
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void printInt64Bang(SStream *O, int64_t val);
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void printUInt64Bang(SStream *O, uint64_t val);
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@ -88,6 +88,7 @@ static inline unsigned AArch64_AM_getShifterImm(AArch64_AM_ShiftExtendType ST, u
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{
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// assert((Imm & 0x3f) == Imm && "Illegal shifted immedate value!");
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unsigned STEnc = 0;
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switch (ST) {
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default: // llvm_unreachable("Invalid shift requested");
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case AArch64_AM_LSL: STEnc = 0; break;
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@ -96,6 +97,7 @@ static inline unsigned AArch64_AM_getShifterImm(AArch64_AM_ShiftExtendType ST, u
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case AArch64_AM_ROR: STEnc = 3; break;
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case AArch64_AM_MSL: STEnc = 4; break;
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}
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return (STEnc << 6) | (Imm & 0x3f);
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}
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@ -163,7 +165,7 @@ inline unsigned AArch64_AM_getExtendEncoding(AArch64_AM_ShiftExtendType ET)
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static inline unsigned AArch64_AM_getArithExtendImm(AArch64_AM_ShiftExtendType ET, unsigned Imm)
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{
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// assert((Imm & 0x7) == Imm && "Illegal shifted immedate value!");
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return (getExtendEncoding(ET) << 3) | (Imm & 0x7);
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return (AArch64_AM_getExtendEncoding(ET) << 3) | (Imm & 0x7);
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}
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/// getMemDoShift - Extract the "do shift" flag value for load/store
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@ -177,25 +179,15 @@ static inline bool AArch64_AM_getMemDoShift(unsigned Imm)
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/// loads/stores.
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static inline AArch64_AM_ShiftExtendType AArch64_AM_getMemExtendType(unsigned Imm)
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{
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return AArch64_AM_getMemExtendType((Imm >> 1) & 0x7);
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return AArch64_AM_getExtendType((Imm >> 1) & 0x7);
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}
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/// getExtendImm - Encode the extend type and amount for a load/store inst:
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/// doshift: should the offset be scaled by the access size
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/// shifter: 000 ==> uxtb
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/// 001 ==> uxth
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/// 010 ==> uxtw
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/// 011 ==> uxtx
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/// 100 ==> sxtb
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/// 101 ==> sxth
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/// 110 ==> sxtw
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/// 111 ==> sxtx
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/// {3-1} = shifter
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/// {0} = doshift
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#if 0
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static inline unsigned AArch64_AM_getMemExtendImm(AArch64_AM_ShiftExtendType ET, bool DoShift)
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{
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return (getExtendEncoding(ET) << 1) | unsigned(DoShift);
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return (AArch64_AM_getExtendEncoding(ET) << 1) | unsigned(DoShift);
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}
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#endif
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static inline uint64_t ror(uint64_t elt, unsigned size)
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{
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@ -206,61 +198,78 @@ static inline uint64_t ror(uint64_t elt, unsigned size)
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/// as the immediate operand of a logical instruction for the given register
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/// size. If so, return true with "encoding" set to the encoded value in
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/// the form N:immr:imms.
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static inline bool AArch64_AM_processLogicalImmediate(uint64_t Imm, unsigned RegSize, uint64_t &Encoding)
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static inline bool AArch64_AM_processLogicalImmediate(uint64_t Imm, unsigned RegSize, uint64_t *Encoding)
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{
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unsigned Size, Immr, N;
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uint32_t CTO, I;
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uint64_t Mask, NImms;
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if (Imm == 0ULL || Imm == ~0ULL ||
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(RegSize != 64 && (Imm >> RegSize != 0 || Imm == (~0ULL >> (64 - RegSize))))) {
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return false;
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}
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// First, determine the element size.
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unsigned Size = RegSize;
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Size = RegSize;
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do {
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uint64_t Mask;
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Size /= 2;
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uint64_t Mask = (1ULL << Size) - 1;
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Mask = (1ULL << Size) - 1;
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if ((Imm & Mask) != ((Imm >> Size) & Mask)) {
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Size *= 2;
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break;
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}
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} while (Size > 2);
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// Second, determine the rotation to make the element be: 0^m 1^n.
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uint32_t CTO, I;
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uint64_t Mask = ((uint64_t)-1LL) >> (64 - Size);
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Mask = ((uint64_t)-1LL) >> (64 - Size);
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Imm &= Mask;
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if (isShiftedMask_64(Imm)) {
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I = countTrailingZeros(Imm);
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I = CountTrailingZeros_32(Imm);
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// assert(I < 64 && "undefined behavior");
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CTO = countTrailingOnes(Imm >> I);
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CTO = CountTrailingOnes_32(Imm >> I);
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} else {
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unsigned CLO;
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Imm |= ~Mask;
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if (!isShiftedMask_64(~Imm))
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return false;
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unsigned CLO = countLeadingOnes(Imm);
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CLO = CountLeadingOnes_32(Imm);
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I = 64 - CLO;
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CTO = CLO + countTrailingOnes(Imm) - (64 - Size);
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CTO = CLO + CountTrailingOnes_32(Imm) - (64 - Size);
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}
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// Encode in Immr the number of RORs it would take to get *from* 0^m 1^n
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// to our target value, where I is the number of RORs to go the opposite
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// direction.
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// assert(Size > I && "I should be smaller than element size");
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unsigned Immr = (Size - I) & (Size - 1);
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Immr = (Size - I) & (Size - 1);
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// If size has a 1 in the n'th bit, create a value that has zeroes in
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// bits [0, n] and ones above that.
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uint64_t NImms = ~(Size-1) << 1;
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NImms = ~(Size-1) << 1;
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// Or the CTO value into the low bits, which must be below the Nth bit
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// bit mentioned above.
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NImms |= (CTO-1);
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// Extract the seventh bit and toggle it to create the N field.
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unsigned N = ((NImms >> 6) & 1) ^ 1;
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Encoding = (N << 12) | (Immr << 6) | (NImms & 0x3f);
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N = ((NImms >> 6) & 1) ^ 1;
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*Encoding = (N << 12) | (Immr << 6) | (NImms & 0x3f);
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return true;
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}
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/// isLogicalImmediate - Return true if the immediate is valid for a logical
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/// immediate instruction of the given register size. Return false otherwise.
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static inline bool AArch64_AM_isLogicalImmediate(uint64_t imm, unsigned regSize)
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static inline bool isLogicalImmediate(uint64_t imm, unsigned regSize)
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{
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uint64_t encoding;
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return AArch64_AM_processLogicalImmediate(imm, regSize, encoding);
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return AArch64_AM_processLogicalImmediate(imm, regSize, &encoding);
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}
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/// encodeLogicalImmediate - Return the encoded immediate value for a logical
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@ -268,9 +277,11 @@ static inline bool AArch64_AM_isLogicalImmediate(uint64_t imm, unsigned regSize)
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static inline uint64_t AArch64_AM_encodeLogicalImmediate(uint64_t imm, unsigned regSize)
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{
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uint64_t encoding = 0;
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bool res = AArch64_AM_processLogicalImmediate(imm, regSize, encoding);
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bool res = AArch64_AM_processLogicalImmediate(imm, regSize, &encoding);
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// assert(res && "invalid logical immediate");
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(void)res;
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return encoding;
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}
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@ -283,16 +294,20 @@ static inline uint64_t AArch64_AM_decodeLogicalImmediate(uint64_t val, unsigned
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unsigned N = (val >> 12) & 1;
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unsigned immr = (val >> 6) & 0x3f;
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unsigned imms = val & 0x3f;
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unsigned i;
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unsigned i, size, R, S;
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uint64_t pattern;
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// assert((regSize == 64 || N == 0) && "undefined logical immediate encoding");
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int len = 31 - countLeadingZeros((N << 6) | (~imms & 0x3f));
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int len = 31 - CountLeadingZeros_32((N << 6) | (~imms & 0x3f));
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// assert(len >= 0 && "undefined logical immediate encoding");
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unsigned size = (1 << len);
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unsigned R = immr & (size - 1);
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unsigned S = imms & (size - 1);
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size = (1 << len);
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R = immr & (size - 1);
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S = imms & (size - 1);
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// assert(S != size - 1 && "undefined logical immediate encoding");
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uint64_t pattern = (1ULL << (S + 1)) - 1;
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pattern = (1ULL << (S + 1)) - 1;
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for (i = 0; i < R; ++i)
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pattern = ror(pattern, size);
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@ -310,8 +325,7 @@ static inline uint64_t AArch64_AM_decodeLogicalImmediate(uint64_t val, unsigned
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/// is a valid encoding for an integer value with regSize bits.
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static inline bool AArch64_AM_isValidDecodeLogicalImmediate(uint64_t val, unsigned regSize)
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{
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unsigned size;
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unsigned S;
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unsigned size, S;
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int len;
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// Extract the N and imms fields needed for checking.
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unsigned N = (val >> 12) & 1;
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@ -319,7 +333,7 @@ static inline bool AArch64_AM_isValidDecodeLogicalImmediate(uint64_t val, unsign
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if (regSize == 32 && N != 0) // undefined logical immediate encoding
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return false;
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len = 31 - countLeadingZeros((N << 6) | (~imms & 0x3f));
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len = 31 - CountLeadingZeros_32((N << 6) | (~imms & 0x3f));
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if (len < 0) // undefined logical immediate encoding
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return false;
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size = (1 << len);
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@ -360,6 +374,7 @@ static inline float AArch64_AM_getFPImmFloat(unsigned Imm)
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return FPUnion.F;
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}
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#if 0
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/// getFP16Imm - Return an 8-bit floating-point version of the 16-bit
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/// floating-point value. If the value cannot be represented as an 8-bit
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/// floating-point value, then return -1.
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@ -378,6 +393,7 @@ static inline int AArch64_AM_getFP16Imm(const APInt &Imm)
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// We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
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if (Exp < -3 || Exp > 4)
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return -1;
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Exp = ((Exp + 3) & 0x7) ^ 4;
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return ((int)Sign << 7) | (Exp << 4) | Mantissa;
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@ -408,6 +424,7 @@ static inline int AArch64_AM_getFP32Imm(const APInt &Imm)
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// We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
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if (Exp < -3 || Exp > 4)
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return -1;
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Exp = ((Exp + 3) & 0x7) ^ 4;
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return ((int)Sign << 7) | (Exp << 4) | Mantissa;
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@ -438,6 +455,7 @@ static inline int AArch64_AM_getFP64Imm(const APInt &Imm)
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// We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
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if (Exp < -3 || Exp > 4)
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return -1;
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Exp = ((Exp + 3) & 0x7) ^ 4;
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return ((int)Sign << 7) | (Exp << 4) | Mantissa;
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@ -447,6 +465,7 @@ static inline int AArch64_AM_getFP64Imm(const APFloat &FPImm)
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{
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return getFP64Imm(FPImm.bitcastToAPInt());
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}
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#endif
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//===--------------------------------------------------------------------===//
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// AdvSIMD Modified Immediates
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@ -456,7 +475,7 @@ static inline int AArch64_AM_getFP64Imm(const APFloat &FPImm)
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static inline bool AArch64_AM_isAdvSIMDModImmType1(uint64_t Imm)
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{
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return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
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((Imm & 0xffffff00ffffff00ULL) == 0);
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((Imm & 0xffffff00ffffff00ULL) == 0);
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}
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static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType1(uint64_t Imm)
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@ -467,6 +486,7 @@ static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType1(uint64_t Imm)
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static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType1(uint8_t Imm)
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{
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uint64_t EncVal = Imm;
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return (EncVal << 32) | EncVal;
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}
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@ -474,7 +494,7 @@ static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType1(uint8_t Imm)
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static inline bool AArch64_AM_isAdvSIMDModImmType2(uint64_t Imm)
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{
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return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
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((Imm & 0xffff00ffffff00ffULL) == 0);
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((Imm & 0xffff00ffffff00ffULL) == 0);
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}
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static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType2(uint64_t Imm)
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@ -492,7 +512,7 @@ static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType2(uint8_t Imm)
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static inline bool AArch64_AM_isAdvSIMDModImmType3(uint64_t Imm)
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{
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return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
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((Imm & 0xff00ffffff00ffffULL) == 0);
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((Imm & 0xff00ffffff00ffffULL) == 0);
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}
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static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType3(uint64_t Imm)
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@ -510,7 +530,7 @@ static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType3(uint8_t Imm)
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static inline bool AArch64_AM_isAdvSIMDModImmType4(uint64_t Imm)
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{
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return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
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((Imm & 0x00ffffff00ffffffULL) == 0);
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((Imm & 0x00ffffff00ffffffULL) == 0);
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}
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static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType4(uint64_t Imm)
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@ -528,8 +548,8 @@ static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType4(uint8_t Imm)
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static inline bool AArch64_AM_isAdvSIMDModImmType5(uint64_t Imm)
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{
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return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
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(((Imm & 0x00ff0000ULL) >> 16) == (Imm & 0x000000ffULL)) &&
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((Imm & 0xff00ff00ff00ff00ULL) == 0);
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(((Imm & 0x00ff0000ULL) >> 16) == (Imm & 0x000000ffULL)) &&
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((Imm & 0xff00ff00ff00ff00ULL) == 0);
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}
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static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType5(uint64_t Imm)
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@ -547,8 +567,8 @@ static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType5(uint8_t Imm)
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static inline bool AArch64_AM_isAdvSIMDModImmType6(uint64_t Imm)
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{
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return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
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(((Imm & 0xff000000ULL) >> 16) == (Imm & 0x0000ff00ULL)) &&
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((Imm & 0x00ff00ff00ff00ffULL) == 0);
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(((Imm & 0xff000000ULL) >> 16) == (Imm & 0x0000ff00ULL)) &&
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((Imm & 0x00ff00ff00ff00ffULL) == 0);
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}
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static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType6(uint64_t Imm)
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@ -566,7 +586,7 @@ static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType6(uint8_t Imm)
|
||||
static inline bool AArch64_AM_isAdvSIMDModImmType7(uint64_t Imm)
|
||||
{
|
||||
return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
|
||||
((Imm & 0xffff00ffffff00ffULL) == 0x000000ff000000ffULL);
|
||||
((Imm & 0xffff00ffffff00ffULL) == 0x000000ff000000ffULL);
|
||||
}
|
||||
|
||||
static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType7(uint64_t Imm)
|
||||
@ -584,7 +604,7 @@ static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType7(uint8_t Imm)
|
||||
static inline bool AArch64_AM_isAdvSIMDModImmType8(uint64_t Imm)
|
||||
{
|
||||
return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
|
||||
((Imm & 0xff00ffffff00ffffULL) == 0x0000ffff0000ffffULL);
|
||||
((Imm & 0xff00ffffff00ffffULL) == 0x0000ffff0000ffffULL);
|
||||
}
|
||||
|
||||
static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType8(uint8_t Imm)
|
||||
@ -602,8 +622,8 @@ static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType8(uint64_t Imm)
|
||||
static inline bool AArch64_AM_isAdvSIMDModImmType9(uint64_t Imm)
|
||||
{
|
||||
return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
|
||||
((Imm >> 48) == (Imm & 0x0000ffffULL)) &&
|
||||
((Imm >> 56) == (Imm & 0x000000ffULL));
|
||||
((Imm >> 48) == (Imm & 0x0000ffffULL)) &&
|
||||
((Imm >> 56) == (Imm & 0x000000ffULL));
|
||||
}
|
||||
|
||||
static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType9(uint64_t Imm)
|
||||
@ -617,6 +637,7 @@ static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType9(uint8_t Imm)
|
||||
EncVal |= (EncVal << 8);
|
||||
EncVal |= (EncVal << 16);
|
||||
EncVal |= (EncVal << 32);
|
||||
|
||||
return EncVal;
|
||||
}
|
||||
|
||||
@ -634,13 +655,13 @@ static inline bool AArch64_AM_isAdvSIMDModImmType10(uint64_t Imm)
|
||||
uint64_t ByteH = Imm & 0x00000000000000ffULL;
|
||||
|
||||
return (ByteA == 0ULL || ByteA == 0xff00000000000000ULL) &&
|
||||
(ByteB == 0ULL || ByteB == 0x00ff000000000000ULL) &&
|
||||
(ByteC == 0ULL || ByteC == 0x0000ff0000000000ULL) &&
|
||||
(ByteD == 0ULL || ByteD == 0x000000ff00000000ULL) &&
|
||||
(ByteE == 0ULL || ByteE == 0x00000000ff000000ULL) &&
|
||||
(ByteF == 0ULL || ByteF == 0x0000000000ff0000ULL) &&
|
||||
(ByteG == 0ULL || ByteG == 0x000000000000ff00ULL) &&
|
||||
(ByteH == 0ULL || ByteH == 0x00000000000000ffULL);
|
||||
(ByteB == 0ULL || ByteB == 0x00ff000000000000ULL) &&
|
||||
(ByteC == 0ULL || ByteC == 0x0000ff0000000000ULL) &&
|
||||
(ByteD == 0ULL || ByteD == 0x000000ff00000000ULL) &&
|
||||
(ByteE == 0ULL || ByteE == 0x00000000ff000000ULL) &&
|
||||
(ByteF == 0ULL || ByteF == 0x0000000000ff0000ULL) &&
|
||||
(ByteG == 0ULL || ByteG == 0x000000000000ff00ULL) &&
|
||||
(ByteH == 0ULL || ByteH == 0x00000000000000ffULL);
|
||||
}
|
||||
|
||||
static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType10(uint64_t Imm)
|
||||
@ -655,6 +676,7 @@ static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType10(uint64_t Imm)
|
||||
uint8_t BitH = (Imm & 0x00000000000000ffULL) != 0;
|
||||
|
||||
uint8_t EncVal = BitA;
|
||||
|
||||
EncVal <<= 1;
|
||||
EncVal |= BitB;
|
||||
EncVal <<= 1;
|
||||
@ -669,28 +691,38 @@ static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType10(uint64_t Imm)
|
||||
EncVal |= BitG;
|
||||
EncVal <<= 1;
|
||||
EncVal |= BitH;
|
||||
|
||||
return EncVal;
|
||||
}
|
||||
|
||||
static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType10(uint8_t Imm)
|
||||
{
|
||||
uint64_t EncVal = 0;
|
||||
|
||||
if (Imm & 0x80)
|
||||
EncVal |= 0xff00000000000000ULL;
|
||||
|
||||
if (Imm & 0x40)
|
||||
EncVal |= 0x00ff000000000000ULL;
|
||||
|
||||
if (Imm & 0x20)
|
||||
EncVal |= 0x0000ff0000000000ULL;
|
||||
|
||||
if (Imm & 0x10)
|
||||
EncVal |= 0x000000ff00000000ULL;
|
||||
|
||||
if (Imm & 0x08)
|
||||
EncVal |= 0x00000000ff000000ULL;
|
||||
|
||||
if (Imm & 0x04)
|
||||
EncVal |= 0x0000000000ff0000ULL;
|
||||
|
||||
if (Imm & 0x02)
|
||||
EncVal |= 0x000000000000ff00ULL;
|
||||
|
||||
if (Imm & 0x01)
|
||||
EncVal |= 0x00000000000000ffULL;
|
||||
|
||||
return EncVal;
|
||||
}
|
||||
|
||||
@ -698,9 +730,10 @@ static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType10(uint8_t Imm)
|
||||
static inline bool AArch64_AM_isAdvSIMDModImmType11(uint64_t Imm)
|
||||
{
|
||||
uint64_t BString = (Imm & 0x7E000000ULL) >> 25;
|
||||
|
||||
return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
|
||||
(BString == 0x1f || BString == 0x20) &&
|
||||
((Imm & 0x0007ffff0007ffffULL) == 0);
|
||||
(BString == 0x1f || BString == 0x20) &&
|
||||
((Imm & 0x0007ffff0007ffffULL) == 0);
|
||||
}
|
||||
|
||||
static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType11(uint64_t Imm)
|
||||
@ -729,30 +762,40 @@ static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType11(uint64_t Imm)
|
||||
EncVal |= BitG;
|
||||
EncVal <<= 1;
|
||||
EncVal |= BitH;
|
||||
|
||||
return EncVal;
|
||||
}
|
||||
|
||||
static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType11(uint8_t Imm)
|
||||
{
|
||||
uint64_t EncVal = 0;
|
||||
|
||||
if (Imm & 0x80)
|
||||
EncVal |= 0x80000000ULL;
|
||||
|
||||
if (Imm & 0x40)
|
||||
EncVal |= 0x3e000000ULL;
|
||||
else
|
||||
EncVal |= 0x40000000ULL;
|
||||
|
||||
if (Imm & 0x20)
|
||||
EncVal |= 0x01000000ULL;
|
||||
|
||||
if (Imm & 0x10)
|
||||
EncVal |= 0x00800000ULL;
|
||||
|
||||
if (Imm & 0x08)
|
||||
EncVal |= 0x00400000ULL;
|
||||
|
||||
if (Imm & 0x04)
|
||||
EncVal |= 0x00200000ULL;
|
||||
|
||||
if (Imm & 0x02)
|
||||
EncVal |= 0x00100000ULL;
|
||||
|
||||
if (Imm & 0x01)
|
||||
EncVal |= 0x00080000ULL;
|
||||
|
||||
return (EncVal << 32) | EncVal;
|
||||
}
|
||||
|
||||
@ -790,6 +833,7 @@ static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType12(uint64_t Imm)
|
||||
EncVal |= BitG;
|
||||
EncVal <<= 1;
|
||||
EncVal |= BitH;
|
||||
|
||||
return EncVal;
|
||||
}
|
||||
|
||||
@ -798,58 +842,129 @@ static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType12(uint8_t Imm)
|
||||
uint64_t EncVal = 0;
|
||||
if (Imm & 0x80)
|
||||
EncVal |= 0x8000000000000000ULL;
|
||||
|
||||
if (Imm & 0x40)
|
||||
EncVal |= 0x3fc0000000000000ULL;
|
||||
else
|
||||
EncVal |= 0x4000000000000000ULL;
|
||||
|
||||
if (Imm & 0x20)
|
||||
EncVal |= 0x0020000000000000ULL;
|
||||
|
||||
if (Imm & 0x10)
|
||||
EncVal |= 0x0010000000000000ULL;
|
||||
|
||||
if (Imm & 0x08)
|
||||
EncVal |= 0x0008000000000000ULL;
|
||||
|
||||
if (Imm & 0x04)
|
||||
EncVal |= 0x0004000000000000ULL;
|
||||
|
||||
if (Imm & 0x02)
|
||||
EncVal |= 0x0002000000000000ULL;
|
||||
|
||||
if (Imm & 0x01)
|
||||
EncVal |= 0x0001000000000000ULL;
|
||||
|
||||
return (EncVal << 32) | EncVal;
|
||||
}
|
||||
|
||||
/// Returns true if Imm is the concatenation of a repeating pattern of type T.
|
||||
// static inline bool AArch64_AM_isSVEMaskOfIdenticalElements(int64_t Imm)
|
||||
// {
|
||||
// union {
|
||||
// int64_t Whole;
|
||||
// T Parts[sizeof(int64_t) / sizeof(T)];
|
||||
// } Vec{Imm};
|
||||
static inline bool AArch64_AM_isSVEMaskOfIdenticalElements8(int64_t Imm)
|
||||
{
|
||||
#define _VECSIZE (sizeof(int64_t)/sizeof(int8_t))
|
||||
unsigned int i;
|
||||
union {
|
||||
int64_t Whole;
|
||||
int8_t Parts[_VECSIZE];
|
||||
} Vec;
|
||||
|
||||
Vec.Whole = Imm;
|
||||
|
||||
// return all_of(Vec.Parts, [Vec](T Elem) { return Elem == Vec.Parts[0]; });
|
||||
// }
|
||||
for(i = 1; i < _VECSIZE; i++) {
|
||||
if (Vec.Parts[i] != Vec.Parts[0])
|
||||
return false;
|
||||
}
|
||||
#undef _VECSIZE
|
||||
|
||||
// /// Returns true if Imm is valid for CPY/DUP.
|
||||
// static inline bool AArch64_AM_isSVECpyImm(int64_t Imm)
|
||||
// {
|
||||
// bool IsImm8 = int8_t(Imm) == Imm;
|
||||
// bool IsImm16 = int16_t(Imm & ~0xff) == Imm;
|
||||
return true;
|
||||
}
|
||||
|
||||
// if (std::is_same<int8_t, typename std::make_signed<T>::type>::value)
|
||||
// return IsImm8 || uint8_t(Imm) == Imm;
|
||||
static inline bool AArch64_AM_isSVEMaskOfIdenticalElements16(int64_t Imm)
|
||||
{
|
||||
#define _VECSIZE (sizeof(int64_t)/sizeof(int16_t))
|
||||
unsigned int i;
|
||||
union {
|
||||
int64_t Whole;
|
||||
int16_t Parts[_VECSIZE];
|
||||
} Vec;
|
||||
|
||||
// if (std::is_same<int16_t, typename std::make_signed<T>::type>::value)
|
||||
// return IsImm8 || IsImm16 || uint16_t(Imm & ~0xff) == Imm;
|
||||
Vec.Whole = Imm;
|
||||
|
||||
// return IsImm8 || IsImm16;
|
||||
// }
|
||||
for(i = 1; i < _VECSIZE; i++) {
|
||||
if (Vec.Parts[i] != Vec.Parts[0])
|
||||
return false;
|
||||
}
|
||||
#undef _VECSIZE
|
||||
|
||||
// /// Returns true if Imm is valid for ADD/SUB.
|
||||
// static inline bool AArch64_AM_isSVEAddSubImm(int64_t Imm)
|
||||
// {
|
||||
// bool IsInt8t =
|
||||
// std::is_same<int8_t, typename std::make_signed<T>::type>::value;
|
||||
// return uint8_t(Imm) == Imm || (!IsInt8t && uint16_t(Imm & ~0xff) == Imm);
|
||||
// }
|
||||
return true;
|
||||
}
|
||||
|
||||
static inline bool AArch64_AM_isSVEMaskOfIdenticalElements32(int64_t Imm)
|
||||
{
|
||||
#define _VECSIZE (sizeof(int64_t)/sizeof(int32_t))
|
||||
unsigned int i;
|
||||
union {
|
||||
int64_t Whole;
|
||||
int32_t Parts[_VECSIZE];
|
||||
} Vec;
|
||||
|
||||
Vec.Whole = Imm;
|
||||
|
||||
for(i = 1; i < _VECSIZE; i++) {
|
||||
if (Vec.Parts[i] != Vec.Parts[0])
|
||||
return false;
|
||||
}
|
||||
#undef _VECSIZE
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static inline bool AArch64_AM_isSVEMaskOfIdenticalElements64(int64_t Imm)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
|
||||
static inline bool isSVECpyImm8(int64_t Imm)
|
||||
{
|
||||
bool IsImm8 = (int8_t)Imm == Imm;
|
||||
|
||||
return IsImm8 || (uint8_t)Imm == Imm;
|
||||
}
|
||||
|
||||
static inline bool isSVECpyImm16(int64_t Imm)
|
||||
{
|
||||
bool IsImm8 = (int8_t)Imm == Imm;
|
||||
bool IsImm16 = (int16_t)(Imm & ~0xff) == Imm;
|
||||
|
||||
return IsImm8 || IsImm16 || (uint16_t)(Imm & ~0xff) == Imm;
|
||||
}
|
||||
|
||||
static inline bool isSVECpyImm32(int64_t Imm)
|
||||
{
|
||||
bool IsImm8 = (int8_t)Imm == Imm;
|
||||
bool IsImm16 = (int16_t)(Imm & ~0xff) == Imm;
|
||||
|
||||
return IsImm8 || IsImm16;
|
||||
}
|
||||
|
||||
static inline bool isSVECpyImm64(int64_t Imm)
|
||||
{
|
||||
bool IsImm8 = (int8_t)Imm == Imm;
|
||||
bool IsImm16 = (int16_t)(Imm & ~0xff) == Imm;
|
||||
|
||||
return IsImm8 || IsImm16;
|
||||
}
|
||||
|
||||
/// Return true if Imm is valid for DUPM and has no single CPY/DUP equivalent.
|
||||
static inline bool AArch64_AM_isSVEMoveMaskPreferredLogicalImmediate(int64_t Imm)
|
||||
@ -861,25 +976,25 @@ static inline bool AArch64_AM_isSVEMoveMaskPreferredLogicalImmediate(int64_t Imm
|
||||
int8_t B[8];
|
||||
} Vec = {Imm};
|
||||
|
||||
if (isSVECpyImm<int64_t>(Vec.D))
|
||||
if (isSVECpyImm64(Vec.D))
|
||||
return false;
|
||||
|
||||
if (isSVEMaskOfIdenticalElements<int32_t>(Imm) &&
|
||||
isSVECpyImm<int32_t>(Vec.S[0]))
|
||||
if (AArch64_AM_isSVEMaskOfIdenticalElements32(Imm) &&
|
||||
isSVECpyImm32(Vec.S[0]))
|
||||
return false;
|
||||
|
||||
if (isSVEMaskOfIdenticalElements<int16_t>(Imm) &&
|
||||
isSVECpyImm<int16_t>(Vec.H[0]))
|
||||
if (AArch64_AM_isSVEMaskOfIdenticalElements16(Imm) &&
|
||||
isSVECpyImm16(Vec.H[0]))
|
||||
return false;
|
||||
|
||||
if (isSVEMaskOfIdenticalElements<int8_t>(Imm) &&
|
||||
isSVECpyImm<int8_t>(Vec.B[0]))
|
||||
if (AArch64_AM_isSVEMaskOfIdenticalElements8(Imm) &&
|
||||
isSVECpyImm8(Vec.B[0]))
|
||||
return false;
|
||||
|
||||
return isLogicalImmediate(Vec.D, 64);
|
||||
}
|
||||
|
||||
inline static bool AArch64_AM_isAnyMOVZMovAlias(uint64_t Value, int RegWidth)
|
||||
inline static bool isAnyMOVZMovAlias(uint64_t Value, int RegWidth)
|
||||
{
|
||||
for (int Shift = 0; Shift <= RegWidth - 16; Shift += 16)
|
||||
if ((Value & ~(0xffffULL << Shift)) == 0)
|
||||
@ -888,7 +1003,7 @@ inline static bool AArch64_AM_isAnyMOVZMovAlias(uint64_t Value, int RegWidth)
|
||||
return false;
|
||||
}
|
||||
|
||||
inline static bool AArch64_AM_isMOVZMovAlias(uint64_t Value, int Shift, int RegWidth)
|
||||
inline static bool isMOVZMovAlias(uint64_t Value, int Shift, int RegWidth)
|
||||
{
|
||||
if (RegWidth == 32)
|
||||
Value &= 0xffffffffULL;
|
||||
|
||||
@ -27,63 +27,15 @@
|
||||
#include <stdlib.h>
|
||||
|
||||
#include "AArch64BaseInfo.h"
|
||||
|
||||
#include "AArch64GenSystemOperands.inc"
|
||||
|
||||
const char *A64NamedImmMapper_toString(const A64NamedImmMapper *N, uint32_t Value, bool *Valid)
|
||||
{
|
||||
unsigned i;
|
||||
for (i = 0; i < N->NumPairs; ++i) {
|
||||
if (N->Pairs[i].Value == Value) {
|
||||
*Valid = true;
|
||||
return N->Pairs[i].Name;
|
||||
}
|
||||
}
|
||||
|
||||
*Valid = false;
|
||||
return 0;
|
||||
}
|
||||
|
||||
// compare s1 with lower(s2)
|
||||
// return true if s1 == lower(f2), and false otherwise
|
||||
static bool compare_lower_str(const char *s1, const char *s2)
|
||||
{
|
||||
bool res;
|
||||
char *lower = cs_strdup(s2), *c;
|
||||
for (c = lower; *c; c++)
|
||||
*c = (char)tolower((int) *c);
|
||||
|
||||
res = (strcmp(s1, lower) == 0);
|
||||
cs_mem_free(lower);
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
uint32_t A64NamedImmMapper_fromString(const A64NamedImmMapper *N, char *Name, bool *Valid)
|
||||
{
|
||||
unsigned i;
|
||||
for (i = 0; i < N->NumPairs; ++i) {
|
||||
if (compare_lower_str(N->Pairs[i].Name, Name)) {
|
||||
*Valid = true;
|
||||
return N->Pairs[i].Value;
|
||||
}
|
||||
}
|
||||
|
||||
*Valid = false;
|
||||
return (uint32_t)-1;
|
||||
}
|
||||
|
||||
bool A64NamedImmMapper_validImm(const A64NamedImmMapper *N, uint32_t Value)
|
||||
{
|
||||
return Value < N->TooBigImm;
|
||||
}
|
||||
|
||||
// return a string representing the number X
|
||||
// NOTE: caller must free() the result itself to avoid memory leak
|
||||
static char *utostr(uint64_t X, bool isNeg)
|
||||
// NOTE: result must be big enough to contain the data
|
||||
static void utostr(uint64_t X, bool isNeg, char *result)
|
||||
{
|
||||
char Buffer[22];
|
||||
char *BufPtr = Buffer+21;
|
||||
char *result;
|
||||
char *BufPtr = Buffer + 21;
|
||||
|
||||
Buffer[21] = '\0';
|
||||
if (X == 0) *--BufPtr = '0'; // Handle special case...
|
||||
@ -95,127 +47,31 @@ static char *utostr(uint64_t X, bool isNeg)
|
||||
|
||||
if (isNeg) *--BufPtr = '-'; // Add negative sign...
|
||||
|
||||
result = cs_strdup(BufPtr);
|
||||
return result;
|
||||
// suppose that result is big enough
|
||||
strncpy(result, BufPtr, sizeof(Buffer));
|
||||
}
|
||||
|
||||
// result must be a big enough buffer: 128 bytes is more than enough
|
||||
void A64SysRegMapper_toString(const A64SysRegMapper *S, uint32_t Bits, char *result)
|
||||
// NOTE: result must be big enough to contain the result
|
||||
void AArch64SysReg_genericRegisterString(uint32_t Bits, char *result)
|
||||
{
|
||||
// assert(Bits < 0x10000);
|
||||
char Op0Str[32], Op1Str[32], CRnStr[32], CRmStr[32], Op2Str[32];
|
||||
int dummy;
|
||||
uint32_t Op0, Op1, CRn, CRm, Op2;
|
||||
char *Op0S, *Op1S, *CRnS, *CRmS, *Op2S;
|
||||
unsigned i;
|
||||
uint32_t Op0 = (Bits >> 14) & 0x3;
|
||||
uint32_t Op1 = (Bits >> 11) & 0x7;
|
||||
uint32_t CRn = (Bits >> 7) & 0xf;
|
||||
uint32_t CRm = (Bits >> 3) & 0xf;
|
||||
uint32_t Op2 = Bits & 0x7;
|
||||
|
||||
// First search the registers shared by all
|
||||
for (i = 0; i < ARR_SIZE(SysRegPairs); ++i) {
|
||||
if (SysRegPairs[i].Value == Bits) {
|
||||
strcpy(result, SysRegPairs[i].Name);
|
||||
return;
|
||||
}
|
||||
}
|
||||
utostr(Op0, false, Op0Str);
|
||||
utostr(Op1, false, Op1Str);
|
||||
utostr(Op2, false, Op2Str);
|
||||
utostr(CRn, false, CRnStr);
|
||||
utostr(CRm, false, CRmStr);
|
||||
|
||||
// Next search for target specific registers
|
||||
// if (FeatureBits & AArch64_ProcCyclone) {
|
||||
if (true) {
|
||||
for (i = 0; i < ARR_SIZE(CycloneSysRegPairs); ++i) {
|
||||
if (CycloneSysRegPairs[i].Value == Bits) {
|
||||
strcpy(result, CycloneSysRegPairs[i].Name);
|
||||
return;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Now try the instruction-specific registers (either read-only or
|
||||
// write-only).
|
||||
for (i = 0; i < S->NumInstPairs; ++i) {
|
||||
if (S->InstPairs[i].Value == Bits) {
|
||||
strcpy(result, S->InstPairs[i].Name);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
Op0 = (Bits >> 14) & 0x3;
|
||||
Op1 = (Bits >> 11) & 0x7;
|
||||
CRn = (Bits >> 7) & 0xf;
|
||||
CRm = (Bits >> 3) & 0xf;
|
||||
Op2 = Bits & 0x7;
|
||||
|
||||
Op0S = utostr(Op0, false);
|
||||
Op1S = utostr(Op1, false);
|
||||
CRnS = utostr(CRn, false);
|
||||
CRmS = utostr(CRm, false);
|
||||
Op2S = utostr(Op2, false);
|
||||
|
||||
//printf("Op1S: %s, CRnS: %s, CRmS: %s, Op2S: %s\n", Op1S, CRnS, CRmS, Op2S);
|
||||
dummy = cs_snprintf(result, 128, "s3_%s_c%s_c%s_%s", Op1S, CRnS, CRmS, Op2S);
|
||||
dummy = cs_snprintf(result, 128, "s%s_%s_c%s_c%s_%s",
|
||||
Op0Str, Op1Str, CRnStr, CRmStr, Op2Str);
|
||||
(void)dummy;
|
||||
|
||||
cs_mem_free(Op0S);
|
||||
cs_mem_free(Op1S);
|
||||
cs_mem_free(CRnS);
|
||||
cs_mem_free(CRmS);
|
||||
cs_mem_free(Op2S);
|
||||
}
|
||||
|
||||
const A64NamedImmMapper A64TLBI_TLBIMapper = {
|
||||
TLBIPairs,
|
||||
ARR_SIZE(TLBIPairs),
|
||||
0,
|
||||
};
|
||||
|
||||
const A64NamedImmMapper A64AT_ATMapper = {
|
||||
ATPairs,
|
||||
ARR_SIZE(ATPairs),
|
||||
0,
|
||||
};
|
||||
|
||||
const A64NamedImmMapper A64DB_DBarrierMapper = {
|
||||
DBarrierPairs,
|
||||
ARR_SIZE(DBarrierPairs),
|
||||
16,
|
||||
};
|
||||
|
||||
const A64NamedImmMapper A64DC_DCMapper = {
|
||||
DCPairs,
|
||||
ARR_SIZE(DCPairs),
|
||||
0,
|
||||
};
|
||||
|
||||
const A64NamedImmMapper A64IC_ICMapper = {
|
||||
ICPairs,
|
||||
ARR_SIZE(ICPairs),
|
||||
0,
|
||||
};
|
||||
|
||||
const A64NamedImmMapper A64ISB_ISBMapper = {
|
||||
ISBPairs,
|
||||
ARR_SIZE(ISBPairs),
|
||||
16,
|
||||
};
|
||||
|
||||
const A64NamedImmMapper A64PRFM_PRFMMapper = {
|
||||
PRFMPairs,
|
||||
ARR_SIZE(PRFMPairs),
|
||||
32,
|
||||
};
|
||||
|
||||
const A64NamedImmMapper A64PState_PStateMapper = {
|
||||
PStatePairs,
|
||||
ARR_SIZE(PStatePairs),
|
||||
0,
|
||||
};
|
||||
|
||||
const A64SysRegMapper AArch64_MRSMapper = {
|
||||
NULL,
|
||||
MRSPairs,
|
||||
ARR_SIZE(MRSPairs),
|
||||
};
|
||||
|
||||
const A64SysRegMapper AArch64_MSRMapper = {
|
||||
NULL,
|
||||
MSRPairs,
|
||||
ARR_SIZE(MSRPairs),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
@ -22,6 +22,7 @@
|
||||
|
||||
#include <ctype.h>
|
||||
#include <string.h>
|
||||
#include "AArch64Mapping.h"
|
||||
|
||||
#ifndef __cplusplus
|
||||
#if defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64)
|
||||
@ -32,6 +33,7 @@
|
||||
inline static unsigned getWRegFromXReg(unsigned Reg)
|
||||
{
|
||||
switch (Reg) {
|
||||
default: break;
|
||||
case ARM64_REG_X0: return ARM64_REG_W0;
|
||||
case ARM64_REG_X1: return ARM64_REG_W1;
|
||||
case ARM64_REG_X2: return ARM64_REG_W2;
|
||||
@ -107,6 +109,7 @@ inline static unsigned getXRegFromWReg(unsigned Reg)
|
||||
case ARM64_REG_W30: return ARM64_REG_LR;
|
||||
case ARM64_REG_WSP: return ARM64_REG_SP;
|
||||
case ARM64_REG_WZR: return ARM64_REG_XZR;
|
||||
}
|
||||
|
||||
// For anything else, return it unchanged.
|
||||
return Reg;
|
||||
@ -193,83 +196,84 @@ inline static unsigned getDRegFromBReg(unsigned Reg)
|
||||
// For anything else, return it unchanged.
|
||||
return Reg;
|
||||
}
|
||||
|
||||
// // Enums corresponding to AArch64 condition codes
|
||||
// The CondCodes constants map directly to the 4-bit encoding of the
|
||||
// condition field for predicated instructions.
|
||||
typedef enum A64CC_CondCode { // Meaning (integer) Meaning (floating-point)
|
||||
A64CC_EQ = 0, // Equal Equal
|
||||
A64CC_NE, // Not equal Not equal, or unordered
|
||||
A64CC_HS, // Unsigned higher or same >, ==, or unordered
|
||||
A64CC_LO, // Unsigned lower or same Less than
|
||||
A64CC_MI, // Minus, negative Less than
|
||||
A64CC_PL, // Plus, positive or zero >, ==, or unordered
|
||||
A64CC_VS, // Overflow Unordered
|
||||
A64CC_VC, // No overflow Ordered
|
||||
A64CC_HI, // Unsigned higher Greater than, or unordered
|
||||
A64CC_LS, // Unsigned lower or same Less than or equal
|
||||
A64CC_GE, // Greater than or equal Greater than or equal
|
||||
A64CC_LT, // Less than Less than, or unordered
|
||||
A64CC_GT, // Signed greater than Greater than
|
||||
A64CC_LE, // Signed less than or equal <, ==, or unordered
|
||||
A64CC_AL, // Always (unconditional) Always (unconditional)
|
||||
A64CC_NV, // Always (unconditional) Always (unconditional)
|
||||
typedef enum AArch64CC_CondCode { // Meaning (integer) Meaning (floating-point)
|
||||
AArch64CC_EQ = 0x0, // Equal Equal
|
||||
AArch64CC_NE = 0x1, // Not equal Not equal, or unordered
|
||||
AArch64CC_HS = 0x2, // Unsigned higher or same >, ==, or unordered
|
||||
AArch64CC_LO = 0x3, // Unsigned lower Less than
|
||||
AArch64CC_MI = 0x4, // Minus, negative Less than
|
||||
AArch64CC_PL = 0x5, // Plus, positive or zero >, ==, or unordered
|
||||
AArch64CC_VS = 0x6, // Overflow Unordered
|
||||
AArch64CC_VC = 0x7, // No overflow Not unordered
|
||||
AArch64CC_HI = 0x8, // Unsigned higher Greater than, or unordered
|
||||
AArch64CC_LS = 0x9, // Unsigned lower or same Less than or equal
|
||||
AArch64CC_GE = 0xa, // Greater than or equal Greater than or equal
|
||||
AArch64CC_LT = 0xb, // Less than Less than, or unordered
|
||||
AArch64CC_GT = 0xc, // Greater than Greater than
|
||||
AArch64CC_LE = 0xd, // Less than or equal <, ==, or unordered
|
||||
AArch64CC_AL = 0xe, // Always (unconditional) Always (unconditional)
|
||||
AArch64CC_NV = 0xf, // Always (unconditional) Always (unconditional)
|
||||
// Note the NV exists purely to disassemble 0b1111. Execution is "always".
|
||||
A64CC_Invalid
|
||||
} A64CC_CondCode;
|
||||
AArch64CC_Invalid
|
||||
} AArch64CC_CondCode;
|
||||
|
||||
inline static const char *getCondCodeName(A64CC_CondCode CC)
|
||||
inline static AArch64CC_CondCode getInvertedCondCode(AArch64CC_CondCode Code)
|
||||
{
|
||||
// To reverse a condition it's necessary to only invert the low bit:
|
||||
return (AArch64CC_CondCode)((unsigned)Code ^ 0x1);
|
||||
}
|
||||
|
||||
inline static const char *getCondCodeName(AArch64CC_CondCode CC)
|
||||
{
|
||||
switch (CC) {
|
||||
default: return NULL; // never reach
|
||||
case A64CC_EQ: return "eq";
|
||||
case A64CC_NE: return "ne";
|
||||
case A64CC_HS: return "hs";
|
||||
case A64CC_LO: return "lo";
|
||||
case A64CC_MI: return "mi";
|
||||
case A64CC_PL: return "pl";
|
||||
case A64CC_VS: return "vs";
|
||||
case A64CC_VC: return "vc";
|
||||
case A64CC_HI: return "hi";
|
||||
case A64CC_LS: return "ls";
|
||||
case A64CC_GE: return "ge";
|
||||
case A64CC_LT: return "lt";
|
||||
case A64CC_GT: return "gt";
|
||||
case A64CC_LE: return "le";
|
||||
case A64CC_AL: return "al";
|
||||
case A64CC_NV: return "nv";
|
||||
case AArch64CC_EQ: return "eq";
|
||||
case AArch64CC_NE: return "ne";
|
||||
case AArch64CC_HS: return "hs";
|
||||
case AArch64CC_LO: return "lo";
|
||||
case AArch64CC_MI: return "mi";
|
||||
case AArch64CC_PL: return "pl";
|
||||
case AArch64CC_VS: return "vs";
|
||||
case AArch64CC_VC: return "vc";
|
||||
case AArch64CC_HI: return "hi";
|
||||
case AArch64CC_LS: return "ls";
|
||||
case AArch64CC_GE: return "ge";
|
||||
case AArch64CC_LT: return "lt";
|
||||
case AArch64CC_GT: return "gt";
|
||||
case AArch64CC_LE: return "le";
|
||||
case AArch64CC_AL: return "al";
|
||||
case AArch64CC_NV: return "nv";
|
||||
}
|
||||
}
|
||||
|
||||
inline static A64CC_CondCode getInvertedCondCode(A64CC_CondCode Code)
|
||||
{
|
||||
// To reverse a condition it's necessary to only invert the low bit:
|
||||
return (A64CC_CondCode)((unsigned)Code ^ 0x1);
|
||||
}
|
||||
|
||||
/// Given a condition code, return NZCV flags that would satisfy that condition.
|
||||
/// The flag bits are in the format expected by the ccmp instructions.
|
||||
/// Note that many different flag settings can satisfy a given condition code,
|
||||
/// this function just returns one of them.
|
||||
inline static unsigned getNZCVToSatisfyCondCode(CondCode Code)
|
||||
inline static unsigned getNZCVToSatisfyCondCode(AArch64CC_CondCode Code)
|
||||
{
|
||||
// NZCV flags encoded as expected by ccmp instructions, ARMv8 ISA 5.5.7.
|
||||
enum { N = 8, Z = 4, C = 2, V = 1 };
|
||||
switch (Code) {
|
||||
default: // llvm_unreachable("Unknown condition code");
|
||||
case EQ: return Z; // Z == 1
|
||||
case NE: return 0; // Z == 0
|
||||
case HS: return C; // C == 1
|
||||
case LO: return 0; // C == 0
|
||||
case MI: return N; // N == 1
|
||||
case PL: return 0; // N == 0
|
||||
case VS: return V; // V == 1
|
||||
case VC: return 0; // V == 0
|
||||
case HI: return C; // C == 1 && Z == 0
|
||||
case LS: return 0; // C == 0 || Z == 1
|
||||
case GE: return 0; // N == V
|
||||
case LT: return N; // N != V
|
||||
case GT: return 0; // Z == 0 && N == V
|
||||
case LE: return Z; // Z == 1 || N != V
|
||||
case AArch64CC_EQ: return Z; // Z == 1
|
||||
case AArch64CC_NE: return 0; // Z == 0
|
||||
case AArch64CC_HS: return C; // C == 1
|
||||
case AArch64CC_LO: return 0; // C == 0
|
||||
case AArch64CC_MI: return N; // N == 1
|
||||
case AArch64CC_PL: return 0; // N == 0
|
||||
case AArch64CC_VS: return V; // V == 1
|
||||
case AArch64CC_VC: return 0; // V == 0
|
||||
case AArch64CC_HI: return C; // C == 1 && Z == 0
|
||||
case AArch64CC_LS: return 0; // C == 0 || Z == 1
|
||||
case AArch64CC_GE: return 0; // N == V
|
||||
case AArch64CC_LT: return N; // N != V
|
||||
case AArch64CC_GT: return 0; // Z == 0 && N == V
|
||||
case AArch64CC_LE: return Z; // Z == 1 || N != V
|
||||
}
|
||||
}
|
||||
|
||||
@ -301,20 +305,6 @@ typedef struct A64SysRegMapper {
|
||||
size_t NumInstPairs;
|
||||
} A64SysRegMapper;
|
||||
|
||||
extern const A64SysRegMapper AArch64_MSRMapper;
|
||||
extern const A64SysRegMapper AArch64_MRSMapper;
|
||||
|
||||
extern const A64NamedImmMapper A64DB_DBarrierMapper;
|
||||
extern const A64NamedImmMapper A64AT_ATMapper;
|
||||
extern const A64NamedImmMapper A64DC_DCMapper;
|
||||
extern const A64NamedImmMapper A64IC_ICMapper;
|
||||
extern const A64NamedImmMapper A64ISB_ISBMapper;
|
||||
extern const A64NamedImmMapper A64PRFM_PRFMMapper;
|
||||
extern const A64NamedImmMapper A64PState_PStateMapper;
|
||||
extern const A64NamedImmMapper A64TLBI_TLBIMapper;
|
||||
|
||||
#include "AArch64GenSystemOperands.inc"
|
||||
|
||||
typedef enum A64SE_ShiftExtSpecifiers {
|
||||
A64SE_Invalid = -1,
|
||||
A64SE_LSL,
|
||||
@ -354,9 +344,10 @@ typedef enum A64Layout_VectorLayout {
|
||||
A64Layout_VL_D
|
||||
} A64Layout_VectorLayout;
|
||||
|
||||
inline static const char *A64VectorLayoutToString(A64Layout_VectorLayout Layout)
|
||||
inline static const char *AArch64VectorLayoutToString(A64Layout_VectorLayout Layout)
|
||||
{
|
||||
switch (Layout) {
|
||||
default: return NULL; // never reach
|
||||
case A64Layout_VL_8B: return ".8b";
|
||||
case A64Layout_VL_4H: return ".4h";
|
||||
case A64Layout_VL_2S: return ".2s";
|
||||
@ -369,67 +360,167 @@ inline static const char *A64VectorLayoutToString(A64Layout_VectorLayout Layout)
|
||||
case A64Layout_VL_H: return ".h";
|
||||
case A64Layout_VL_S: return ".s";
|
||||
case A64Layout_VL_D: return ".d";
|
||||
default: return NULL; // never reach
|
||||
}
|
||||
}
|
||||
|
||||
bool A64Imms_isLogicalImmBits(unsigned RegWidth, uint32_t Bits, uint64_t *Imm);
|
||||
inline static A64Layout_VectorLayout AArch64StringToVectorLayout(char *LayoutStr)
|
||||
{
|
||||
if (!strcmp(LayoutStr, ".8b"))
|
||||
return A64Layout_VL_8B;
|
||||
|
||||
const char *A64NamedImmMapper_toString(const A64NamedImmMapper *N, uint32_t Value, bool *Valid);
|
||||
if (!strcmp(LayoutStr, ".4h"))
|
||||
return A64Layout_VL_4H;
|
||||
|
||||
uint32_t A64NamedImmMapper_fromString(const A64NamedImmMapper *N, char *Name, bool *Valid);
|
||||
if (!strcmp(LayoutStr, ".2s"))
|
||||
return A64Layout_VL_2S;
|
||||
|
||||
bool A64NamedImmMapper_validImm(const A64NamedImmMapper *N, uint32_t Value);
|
||||
if (!strcmp(LayoutStr, ".1d"))
|
||||
return A64Layout_VL_1D;
|
||||
|
||||
void A64SysRegMapper_toString(const A64SysRegMapper *S, uint32_t Bits, char *result);
|
||||
if (!strcmp(LayoutStr, ".16b"))
|
||||
return A64Layout_VL_16B;
|
||||
|
||||
if (!strcmp(LayoutStr, ".8h"))
|
||||
return A64Layout_VL_8H;
|
||||
|
||||
if (!strcmp(LayoutStr, ".4s"))
|
||||
return A64Layout_VL_4S;
|
||||
|
||||
if (!strcmp(LayoutStr, ".2d"))
|
||||
return A64Layout_VL_2D;
|
||||
|
||||
if (!strcmp(LayoutStr, ".b"))
|
||||
return A64Layout_VL_B;
|
||||
|
||||
if (!strcmp(LayoutStr, ".s"))
|
||||
return A64Layout_VL_S;
|
||||
|
||||
if (!strcmp(LayoutStr, ".d"))
|
||||
return A64Layout_VL_D;
|
||||
|
||||
return A64Layout_Invalid;
|
||||
}
|
||||
|
||||
/// Target Operand Flag enum.
|
||||
enum TOF {
|
||||
//===------------------------------------------------------------------===//
|
||||
// AArch64 Specific MachineOperand flags.
|
||||
|
||||
MO_NO_FLAG,
|
||||
|
||||
MO_FRAGMENT = 0xf,
|
||||
|
||||
/// MO_PAGE - A symbol operand with this flag represents the pc-relative
|
||||
/// offset of the 4K page containing the symbol. This is used with the
|
||||
/// ADRP instruction.
|
||||
MO_PAGE = 1,
|
||||
|
||||
/// MO_PAGEOFF - A symbol operand with this flag represents the offset of
|
||||
/// that symbol within a 4K page. This offset is added to the page address
|
||||
/// to produce the complete address.
|
||||
MO_PAGEOFF = 2,
|
||||
|
||||
/// MO_G3 - A symbol operand with this flag (granule 3) represents the high
|
||||
/// 16-bits of a 64-bit address, used in a MOVZ or MOVK instruction
|
||||
MO_G3 = 3,
|
||||
|
||||
/// MO_G2 - A symbol operand with this flag (granule 2) represents the bits
|
||||
/// 32-47 of a 64-bit address, used in a MOVZ or MOVK instruction
|
||||
MO_G2 = 4,
|
||||
|
||||
/// MO_G1 - A symbol operand with this flag (granule 1) represents the bits
|
||||
/// 16-31 of a 64-bit address, used in a MOVZ or MOVK instruction
|
||||
MO_G1 = 5,
|
||||
|
||||
/// MO_G0 - A symbol operand with this flag (granule 0) represents the bits
|
||||
/// 0-15 of a 64-bit address, used in a MOVZ or MOVK instruction
|
||||
MO_G0 = 6,
|
||||
|
||||
/// MO_HI12 - This flag indicates that a symbol operand represents the bits
|
||||
/// 13-24 of a 64-bit address, used in a arithmetic immediate-shifted-left-
|
||||
/// by-12-bits instruction.
|
||||
MO_HI12 = 7,
|
||||
|
||||
/// MO_GOT - This flag indicates that a symbol operand represents the
|
||||
/// address of the GOT entry for the symbol, rather than the address of
|
||||
/// the symbol itself.
|
||||
MO_GOT = 0x10,
|
||||
|
||||
/// MO_NC - Indicates whether the linker is expected to check the symbol
|
||||
/// reference for overflow. For example in an ADRP/ADD pair of relocations
|
||||
/// the ADRP usually does check, but not the ADD.
|
||||
MO_NC = 0x20,
|
||||
|
||||
/// MO_TLS - Indicates that the operand being accessed is some kind of
|
||||
/// thread-local symbol. On Darwin, only one type of thread-local access
|
||||
/// exists (pre linker-relaxation), but on ELF the TLSModel used for the
|
||||
/// referee will affect interpretation.
|
||||
MO_TLS = 0x40,
|
||||
|
||||
/// MO_DLLIMPORT - On a symbol operand, this represents that the reference
|
||||
/// to the symbol is for an import stub. This is used for DLL import
|
||||
/// storage class indication on Windows.
|
||||
MO_DLLIMPORT = 0x80,
|
||||
};
|
||||
|
||||
typedef struct SysAlias {
|
||||
const char *Name;
|
||||
uint16_t Encoding;
|
||||
} SysAlias;
|
||||
|
||||
#define AT SysAlias
|
||||
#define DB SysAlias
|
||||
#define DC SysAlias
|
||||
#define SVEPRFM SysAlias
|
||||
#define PRFM SysAlias
|
||||
#define PSB SysAlias
|
||||
#define ISB SysAlias
|
||||
#define TSB SysAlias
|
||||
#define PState SysAlias
|
||||
#define SVEPREDPAT SysAlias
|
||||
|
||||
typedef struct SysAliasReg {
|
||||
const char *Name;
|
||||
uint16_t Encoding;
|
||||
bool NeedsReg;
|
||||
} SysAliasReg;
|
||||
|
||||
#define IC SysAliasReg
|
||||
#define TLBI SysAliasReg
|
||||
|
||||
typedef struct SysAliasSysReg {
|
||||
const char *Name;
|
||||
uint16_t Encoding;
|
||||
bool Readable;
|
||||
bool Writeable;
|
||||
} SysAliasSysReg;
|
||||
|
||||
#define SysReg SysAliasSysReg
|
||||
|
||||
typedef struct ExactFPImm {
|
||||
const char *Name;
|
||||
int Enum;
|
||||
const char *Repr;
|
||||
} ExactFPImm;
|
||||
|
||||
const AT *lookupATByEncoding(uint16_t Encoding);
|
||||
const DB *lookupDBByEncoding(uint16_t Encoding);
|
||||
const DC *lookupDCByEncoding(uint16_t Encoding);
|
||||
const IC *lookupICByEncoding(uint16_t Encoding);
|
||||
const TLBI *lookupTLBIByEncoding(uint16_t Encoding);
|
||||
const SVEPRFM *lookupSVEPRFMByEncoding(uint16_t Encoding);
|
||||
const PRFM *lookupPRFMByEncoding(uint16_t Encoding);
|
||||
const PSB *AArch64PSBHint_lookupPSBByEncoding(uint16_t Encoding);
|
||||
const ISB *lookupISBByEncoding(uint16_t Encoding);
|
||||
const TSB *lookupTSBByEncoding(uint16_t Encoding);
|
||||
const SysReg *lookupSysRegByEncoding(uint16_t Encoding);
|
||||
const PState *lookupPStateByEncoding(uint16_t Encoding);
|
||||
const SVEPREDPAT *lookupSVEPREDPATByEncoding(uint16_t Encoding);
|
||||
const ExactFPImm *lookupExactFPImmByEnum(uint16_t Encoding);
|
||||
|
||||
// NOTE: result must be 128 bytes to contain the result
|
||||
void AArch64SysReg_genericRegisterString(uint32_t Bits, char *result);
|
||||
|
||||
#include "AArch64GenSystemOperands_enum.inc"
|
||||
|
||||
#endif
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -13,4 +13,6 @@ void AArch64_init(MCRegisterInfo *MRI);
|
||||
bool AArch64_getInstruction(csh ud, const uint8_t *code, size_t code_len,
|
||||
MCInst *instr, uint16_t *size, uint64_t address, void *info);
|
||||
|
||||
uint64_t AArch64_getFeatureBits(int feature);
|
||||
|
||||
#endif
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
686
arch/AArch64/AArch64GenRegisterName.inc
Normal file
686
arch/AArch64/AArch64GenRegisterName.inc
Normal file
@ -0,0 +1,686 @@
|
||||
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
|
||||
|
||||
/// getRegisterName - This method is automatically generated by tblgen
|
||||
/// from the register set description. This returns the assembler name
|
||||
/// for the specified register.
|
||||
static const char *getRegisterName(unsigned RegNo, unsigned AltIdx)
|
||||
{
|
||||
|
||||
#ifndef CAPSTONE_DIET
|
||||
static const char AsmStrsNoRegAltName[] = {
|
||||
/* 0 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', 0,
|
||||
/* 13 */ 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', 0,
|
||||
/* 26 */ 'W', '9', '_', 'W', '1', '0', 0,
|
||||
/* 33 */ 'X', '9', '_', 'X', '1', '0', 0,
|
||||
/* 40 */ 'Z', '7', '_', 'Z', '8', '_', 'Z', '9', '_', 'Z', '1', '0', 0,
|
||||
/* 53 */ 'b', '1', '0', 0,
|
||||
/* 57 */ 'd', '1', '0', 0,
|
||||
/* 61 */ 'h', '1', '0', 0,
|
||||
/* 65 */ 'p', '1', '0', 0,
|
||||
/* 69 */ 'q', '1', '0', 0,
|
||||
/* 73 */ 's', '1', '0', 0,
|
||||
/* 77 */ 'w', '1', '0', 0,
|
||||
/* 81 */ 'x', '1', '0', 0,
|
||||
/* 85 */ 'z', '1', '0', 0,
|
||||
/* 89 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', 0,
|
||||
/* 105 */ 'Q', '1', '7', '_', 'Q', '1', '8', '_', 'Q', '1', '9', '_', 'Q', '2', '0', 0,
|
||||
/* 121 */ 'W', '1', '9', '_', 'W', '2', '0', 0,
|
||||
/* 129 */ 'X', '1', '9', '_', 'X', '2', '0', 0,
|
||||
/* 137 */ 'Z', '1', '7', '_', 'Z', '1', '8', '_', 'Z', '1', '9', '_', 'Z', '2', '0', 0,
|
||||
/* 153 */ 'b', '2', '0', 0,
|
||||
/* 157 */ 'd', '2', '0', 0,
|
||||
/* 161 */ 'h', '2', '0', 0,
|
||||
/* 165 */ 'q', '2', '0', 0,
|
||||
/* 169 */ 's', '2', '0', 0,
|
||||
/* 173 */ 'w', '2', '0', 0,
|
||||
/* 177 */ 'x', '2', '0', 0,
|
||||
/* 181 */ 'z', '2', '0', 0,
|
||||
/* 185 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', 0,
|
||||
/* 201 */ 'Q', '2', '7', '_', 'Q', '2', '8', '_', 'Q', '2', '9', '_', 'Q', '3', '0', 0,
|
||||
/* 217 */ 'W', '2', '9', '_', 'W', '3', '0', 0,
|
||||
/* 225 */ 'Z', '2', '7', '_', 'Z', '2', '8', '_', 'Z', '2', '9', '_', 'Z', '3', '0', 0,
|
||||
/* 241 */ 'b', '3', '0', 0,
|
||||
/* 245 */ 'd', '3', '0', 0,
|
||||
/* 249 */ 'h', '3', '0', 0,
|
||||
/* 253 */ 'q', '3', '0', 0,
|
||||
/* 257 */ 's', '3', '0', 0,
|
||||
/* 261 */ 'w', '3', '0', 0,
|
||||
/* 265 */ 'x', '3', '0', 0,
|
||||
/* 269 */ 'z', '3', '0', 0,
|
||||
/* 273 */ 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', '_', 'D', '0', 0,
|
||||
/* 288 */ 'Q', '2', '9', '_', 'Q', '3', '0', '_', 'Q', '3', '1', '_', 'Q', '0', 0,
|
||||
/* 303 */ 'W', 'Z', 'R', '_', 'W', '0', 0,
|
||||
/* 310 */ 'X', 'Z', 'R', '_', 'X', '0', 0,
|
||||
/* 317 */ 'Z', '2', '9', '_', 'Z', '3', '0', '_', 'Z', '3', '1', '_', 'Z', '0', 0,
|
||||
/* 332 */ 'b', '0', 0,
|
||||
/* 335 */ 'd', '0', 0,
|
||||
/* 338 */ 'h', '0', 0,
|
||||
/* 341 */ 'p', '0', 0,
|
||||
/* 344 */ 'q', '0', 0,
|
||||
/* 347 */ 's', '0', 0,
|
||||
/* 350 */ 'w', '0', 0,
|
||||
/* 353 */ 'x', '0', 0,
|
||||
/* 356 */ 'z', '0', 0,
|
||||
/* 359 */ 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', 0,
|
||||
/* 373 */ 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', 0,
|
||||
/* 387 */ 'W', '1', '0', '_', 'W', '1', '1', 0,
|
||||
/* 395 */ 'X', '1', '0', '_', 'X', '1', '1', 0,
|
||||
/* 403 */ 'Z', '8', '_', 'Z', '9', '_', 'Z', '1', '0', '_', 'Z', '1', '1', 0,
|
||||
/* 417 */ 'b', '1', '1', 0,
|
||||
/* 421 */ 'd', '1', '1', 0,
|
||||
/* 425 */ 'h', '1', '1', 0,
|
||||
/* 429 */ 'p', '1', '1', 0,
|
||||
/* 433 */ 'q', '1', '1', 0,
|
||||
/* 437 */ 's', '1', '1', 0,
|
||||
/* 441 */ 'w', '1', '1', 0,
|
||||
/* 445 */ 'x', '1', '1', 0,
|
||||
/* 449 */ 'z', '1', '1', 0,
|
||||
/* 453 */ 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', 0,
|
||||
/* 469 */ 'Q', '1', '8', '_', 'Q', '1', '9', '_', 'Q', '2', '0', '_', 'Q', '2', '1', 0,
|
||||
/* 485 */ 'W', '2', '0', '_', 'W', '2', '1', 0,
|
||||
/* 493 */ 'X', '2', '0', '_', 'X', '2', '1', 0,
|
||||
/* 501 */ 'Z', '1', '8', '_', 'Z', '1', '9', '_', 'Z', '2', '0', '_', 'Z', '2', '1', 0,
|
||||
/* 517 */ 'b', '2', '1', 0,
|
||||
/* 521 */ 'd', '2', '1', 0,
|
||||
/* 525 */ 'h', '2', '1', 0,
|
||||
/* 529 */ 'q', '2', '1', 0,
|
||||
/* 533 */ 's', '2', '1', 0,
|
||||
/* 537 */ 'w', '2', '1', 0,
|
||||
/* 541 */ 'x', '2', '1', 0,
|
||||
/* 545 */ 'z', '2', '1', 0,
|
||||
/* 549 */ 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', 0,
|
||||
/* 565 */ 'Q', '2', '8', '_', 'Q', '2', '9', '_', 'Q', '3', '0', '_', 'Q', '3', '1', 0,
|
||||
/* 581 */ 'Z', '2', '8', '_', 'Z', '2', '9', '_', 'Z', '3', '0', '_', 'Z', '3', '1', 0,
|
||||
/* 597 */ 'b', '3', '1', 0,
|
||||
/* 601 */ 'd', '3', '1', 0,
|
||||
/* 605 */ 'h', '3', '1', 0,
|
||||
/* 609 */ 'q', '3', '1', 0,
|
||||
/* 613 */ 's', '3', '1', 0,
|
||||
/* 617 */ 'z', '3', '1', 0,
|
||||
/* 621 */ 'D', '3', '0', '_', 'D', '3', '1', '_', 'D', '0', '_', 'D', '1', 0,
|
||||
/* 635 */ 'Q', '3', '0', '_', 'Q', '3', '1', '_', 'Q', '0', '_', 'Q', '1', 0,
|
||||
/* 649 */ 'W', '0', '_', 'W', '1', 0,
|
||||
/* 655 */ 'X', '0', '_', 'X', '1', 0,
|
||||
/* 661 */ 'Z', '3', '0', '_', 'Z', '3', '1', '_', 'Z', '0', '_', 'Z', '1', 0,
|
||||
/* 675 */ 'b', '1', 0,
|
||||
/* 678 */ 'd', '1', 0,
|
||||
/* 681 */ 'h', '1', 0,
|
||||
/* 684 */ 'p', '1', 0,
|
||||
/* 687 */ 'q', '1', 0,
|
||||
/* 690 */ 's', '1', 0,
|
||||
/* 693 */ 'w', '1', 0,
|
||||
/* 696 */ 'x', '1', 0,
|
||||
/* 699 */ 'z', '1', 0,
|
||||
/* 702 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', 0,
|
||||
/* 717 */ 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', 0,
|
||||
/* 732 */ 'W', '1', '1', '_', 'W', '1', '2', 0,
|
||||
/* 740 */ 'X', '1', '1', '_', 'X', '1', '2', 0,
|
||||
/* 748 */ 'Z', '9', '_', 'Z', '1', '0', '_', 'Z', '1', '1', '_', 'Z', '1', '2', 0,
|
||||
/* 763 */ 'b', '1', '2', 0,
|
||||
/* 767 */ 'd', '1', '2', 0,
|
||||
/* 771 */ 'h', '1', '2', 0,
|
||||
/* 775 */ 'p', '1', '2', 0,
|
||||
/* 779 */ 'q', '1', '2', 0,
|
||||
/* 783 */ 's', '1', '2', 0,
|
||||
/* 787 */ 'w', '1', '2', 0,
|
||||
/* 791 */ 'x', '1', '2', 0,
|
||||
/* 795 */ 'z', '1', '2', 0,
|
||||
/* 799 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', 0,
|
||||
/* 815 */ 'Q', '1', '9', '_', 'Q', '2', '0', '_', 'Q', '2', '1', '_', 'Q', '2', '2', 0,
|
||||
/* 831 */ 'W', '2', '1', '_', 'W', '2', '2', 0,
|
||||
/* 839 */ 'X', '2', '1', '_', 'X', '2', '2', 0,
|
||||
/* 847 */ 'Z', '1', '9', '_', 'Z', '2', '0', '_', 'Z', '2', '1', '_', 'Z', '2', '2', 0,
|
||||
/* 863 */ 'b', '2', '2', 0,
|
||||
/* 867 */ 'd', '2', '2', 0,
|
||||
/* 871 */ 'h', '2', '2', 0,
|
||||
/* 875 */ 'q', '2', '2', 0,
|
||||
/* 879 */ 's', '2', '2', 0,
|
||||
/* 883 */ 'w', '2', '2', 0,
|
||||
/* 887 */ 'x', '2', '2', 0,
|
||||
/* 891 */ 'z', '2', '2', 0,
|
||||
/* 895 */ 'D', '3', '1', '_', 'D', '0', '_', 'D', '1', '_', 'D', '2', 0,
|
||||
/* 908 */ 'Q', '3', '1', '_', 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', 0,
|
||||
/* 921 */ 'W', '1', '_', 'W', '2', 0,
|
||||
/* 927 */ 'X', '1', '_', 'X', '2', 0,
|
||||
/* 933 */ 'Z', '3', '1', '_', 'Z', '0', '_', 'Z', '1', '_', 'Z', '2', 0,
|
||||
/* 946 */ 'b', '2', 0,
|
||||
/* 949 */ 'd', '2', 0,
|
||||
/* 952 */ 'h', '2', 0,
|
||||
/* 955 */ 'p', '2', 0,
|
||||
/* 958 */ 'q', '2', 0,
|
||||
/* 961 */ 's', '2', 0,
|
||||
/* 964 */ 'w', '2', 0,
|
||||
/* 967 */ 'x', '2', 0,
|
||||
/* 970 */ 'z', '2', 0,
|
||||
/* 973 */ 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', 0,
|
||||
/* 989 */ 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', 0,
|
||||
/* 1005 */ 'W', '1', '2', '_', 'W', '1', '3', 0,
|
||||
/* 1013 */ 'X', '1', '2', '_', 'X', '1', '3', 0,
|
||||
/* 1021 */ 'Z', '1', '0', '_', 'Z', '1', '1', '_', 'Z', '1', '2', '_', 'Z', '1', '3', 0,
|
||||
/* 1037 */ 'b', '1', '3', 0,
|
||||
/* 1041 */ 'd', '1', '3', 0,
|
||||
/* 1045 */ 'h', '1', '3', 0,
|
||||
/* 1049 */ 'p', '1', '3', 0,
|
||||
/* 1053 */ 'q', '1', '3', 0,
|
||||
/* 1057 */ 's', '1', '3', 0,
|
||||
/* 1061 */ 'w', '1', '3', 0,
|
||||
/* 1065 */ 'x', '1', '3', 0,
|
||||
/* 1069 */ 'z', '1', '3', 0,
|
||||
/* 1073 */ 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', 0,
|
||||
/* 1089 */ 'Q', '2', '0', '_', 'Q', '2', '1', '_', 'Q', '2', '2', '_', 'Q', '2', '3', 0,
|
||||
/* 1105 */ 'W', '2', '2', '_', 'W', '2', '3', 0,
|
||||
/* 1113 */ 'X', '2', '2', '_', 'X', '2', '3', 0,
|
||||
/* 1121 */ 'Z', '2', '0', '_', 'Z', '2', '1', '_', 'Z', '2', '2', '_', 'Z', '2', '3', 0,
|
||||
/* 1137 */ 'b', '2', '3', 0,
|
||||
/* 1141 */ 'd', '2', '3', 0,
|
||||
/* 1145 */ 'h', '2', '3', 0,
|
||||
/* 1149 */ 'q', '2', '3', 0,
|
||||
/* 1153 */ 's', '2', '3', 0,
|
||||
/* 1157 */ 'w', '2', '3', 0,
|
||||
/* 1161 */ 'x', '2', '3', 0,
|
||||
/* 1165 */ 'z', '2', '3', 0,
|
||||
/* 1169 */ 'D', '0', '_', 'D', '1', '_', 'D', '2', '_', 'D', '3', 0,
|
||||
/* 1181 */ 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', 0,
|
||||
/* 1193 */ 'W', '2', '_', 'W', '3', 0,
|
||||
/* 1199 */ 'X', '2', '_', 'X', '3', 0,
|
||||
/* 1205 */ 'Z', '0', '_', 'Z', '1', '_', 'Z', '2', '_', 'Z', '3', 0,
|
||||
/* 1217 */ 'b', '3', 0,
|
||||
/* 1220 */ 'd', '3', 0,
|
||||
/* 1223 */ 'h', '3', 0,
|
||||
/* 1226 */ 'p', '3', 0,
|
||||
/* 1229 */ 'q', '3', 0,
|
||||
/* 1232 */ 's', '3', 0,
|
||||
/* 1235 */ 'w', '3', 0,
|
||||
/* 1238 */ 'x', '3', 0,
|
||||
/* 1241 */ 'z', '3', 0,
|
||||
/* 1244 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', 0,
|
||||
/* 1260 */ 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', 0,
|
||||
/* 1276 */ 'W', '1', '3', '_', 'W', '1', '4', 0,
|
||||
/* 1284 */ 'X', '1', '3', '_', 'X', '1', '4', 0,
|
||||
/* 1292 */ 'Z', '1', '1', '_', 'Z', '1', '2', '_', 'Z', '1', '3', '_', 'Z', '1', '4', 0,
|
||||
/* 1308 */ 'b', '1', '4', 0,
|
||||
/* 1312 */ 'd', '1', '4', 0,
|
||||
/* 1316 */ 'h', '1', '4', 0,
|
||||
/* 1320 */ 'p', '1', '4', 0,
|
||||
/* 1324 */ 'q', '1', '4', 0,
|
||||
/* 1328 */ 's', '1', '4', 0,
|
||||
/* 1332 */ 'w', '1', '4', 0,
|
||||
/* 1336 */ 'x', '1', '4', 0,
|
||||
/* 1340 */ 'z', '1', '4', 0,
|
||||
/* 1344 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', 0,
|
||||
/* 1360 */ 'Q', '2', '1', '_', 'Q', '2', '2', '_', 'Q', '2', '3', '_', 'Q', '2', '4', 0,
|
||||
/* 1376 */ 'W', '2', '3', '_', 'W', '2', '4', 0,
|
||||
/* 1384 */ 'X', '2', '3', '_', 'X', '2', '4', 0,
|
||||
/* 1392 */ 'Z', '2', '1', '_', 'Z', '2', '2', '_', 'Z', '2', '3', '_', 'Z', '2', '4', 0,
|
||||
/* 1408 */ 'b', '2', '4', 0,
|
||||
/* 1412 */ 'd', '2', '4', 0,
|
||||
/* 1416 */ 'h', '2', '4', 0,
|
||||
/* 1420 */ 'q', '2', '4', 0,
|
||||
/* 1424 */ 's', '2', '4', 0,
|
||||
/* 1428 */ 'w', '2', '4', 0,
|
||||
/* 1432 */ 'x', '2', '4', 0,
|
||||
/* 1436 */ 'z', '2', '4', 0,
|
||||
/* 1440 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', '_', 'D', '4', 0,
|
||||
/* 1452 */ 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', 0,
|
||||
/* 1464 */ 'W', '3', '_', 'W', '4', 0,
|
||||
/* 1470 */ 'X', '3', '_', 'X', '4', 0,
|
||||
/* 1476 */ 'Z', '1', '_', 'Z', '2', '_', 'Z', '3', '_', 'Z', '4', 0,
|
||||
/* 1488 */ 'b', '4', 0,
|
||||
/* 1491 */ 'd', '4', 0,
|
||||
/* 1494 */ 'h', '4', 0,
|
||||
/* 1497 */ 'p', '4', 0,
|
||||
/* 1500 */ 'q', '4', 0,
|
||||
/* 1503 */ 's', '4', 0,
|
||||
/* 1506 */ 'w', '4', 0,
|
||||
/* 1509 */ 'x', '4', 0,
|
||||
/* 1512 */ 'z', '4', 0,
|
||||
/* 1515 */ 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', 0,
|
||||
/* 1531 */ 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', 0,
|
||||
/* 1547 */ 'W', '1', '4', '_', 'W', '1', '5', 0,
|
||||
/* 1555 */ 'X', '1', '4', '_', 'X', '1', '5', 0,
|
||||
/* 1563 */ 'Z', '1', '2', '_', 'Z', '1', '3', '_', 'Z', '1', '4', '_', 'Z', '1', '5', 0,
|
||||
/* 1579 */ 'b', '1', '5', 0,
|
||||
/* 1583 */ 'd', '1', '5', 0,
|
||||
/* 1587 */ 'h', '1', '5', 0,
|
||||
/* 1591 */ 'p', '1', '5', 0,
|
||||
/* 1595 */ 'q', '1', '5', 0,
|
||||
/* 1599 */ 's', '1', '5', 0,
|
||||
/* 1603 */ 'w', '1', '5', 0,
|
||||
/* 1607 */ 'x', '1', '5', 0,
|
||||
/* 1611 */ 'z', '1', '5', 0,
|
||||
/* 1615 */ 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', 0,
|
||||
/* 1631 */ 'Q', '2', '2', '_', 'Q', '2', '3', '_', 'Q', '2', '4', '_', 'Q', '2', '5', 0,
|
||||
/* 1647 */ 'W', '2', '4', '_', 'W', '2', '5', 0,
|
||||
/* 1655 */ 'X', '2', '4', '_', 'X', '2', '5', 0,
|
||||
/* 1663 */ 'Z', '2', '2', '_', 'Z', '2', '3', '_', 'Z', '2', '4', '_', 'Z', '2', '5', 0,
|
||||
/* 1679 */ 'b', '2', '5', 0,
|
||||
/* 1683 */ 'd', '2', '5', 0,
|
||||
/* 1687 */ 'h', '2', '5', 0,
|
||||
/* 1691 */ 'q', '2', '5', 0,
|
||||
/* 1695 */ 's', '2', '5', 0,
|
||||
/* 1699 */ 'w', '2', '5', 0,
|
||||
/* 1703 */ 'x', '2', '5', 0,
|
||||
/* 1707 */ 'z', '2', '5', 0,
|
||||
/* 1711 */ 'D', '2', '_', 'D', '3', '_', 'D', '4', '_', 'D', '5', 0,
|
||||
/* 1723 */ 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', 0,
|
||||
/* 1735 */ 'W', '4', '_', 'W', '5', 0,
|
||||
/* 1741 */ 'X', '4', '_', 'X', '5', 0,
|
||||
/* 1747 */ 'Z', '2', '_', 'Z', '3', '_', 'Z', '4', '_', 'Z', '5', 0,
|
||||
/* 1759 */ 'b', '5', 0,
|
||||
/* 1762 */ 'd', '5', 0,
|
||||
/* 1765 */ 'h', '5', 0,
|
||||
/* 1768 */ 'p', '5', 0,
|
||||
/* 1771 */ 'q', '5', 0,
|
||||
/* 1774 */ 's', '5', 0,
|
||||
/* 1777 */ 'w', '5', 0,
|
||||
/* 1780 */ 'x', '5', 0,
|
||||
/* 1783 */ 'z', '5', 0,
|
||||
/* 1786 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', 0,
|
||||
/* 1802 */ 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', '_', 'Q', '1', '6', 0,
|
||||
/* 1818 */ 'W', '1', '5', '_', 'W', '1', '6', 0,
|
||||
/* 1826 */ 'X', '1', '5', '_', 'X', '1', '6', 0,
|
||||
/* 1834 */ 'Z', '1', '3', '_', 'Z', '1', '4', '_', 'Z', '1', '5', '_', 'Z', '1', '6', 0,
|
||||
/* 1850 */ 'b', '1', '6', 0,
|
||||
/* 1854 */ 'd', '1', '6', 0,
|
||||
/* 1858 */ 'h', '1', '6', 0,
|
||||
/* 1862 */ 'q', '1', '6', 0,
|
||||
/* 1866 */ 's', '1', '6', 0,
|
||||
/* 1870 */ 'w', '1', '6', 0,
|
||||
/* 1874 */ 'x', '1', '6', 0,
|
||||
/* 1878 */ 'z', '1', '6', 0,
|
||||
/* 1882 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', 0,
|
||||
/* 1898 */ 'Q', '2', '3', '_', 'Q', '2', '4', '_', 'Q', '2', '5', '_', 'Q', '2', '6', 0,
|
||||
/* 1914 */ 'W', '2', '5', '_', 'W', '2', '6', 0,
|
||||
/* 1922 */ 'X', '2', '5', '_', 'X', '2', '6', 0,
|
||||
/* 1930 */ 'Z', '2', '3', '_', 'Z', '2', '4', '_', 'Z', '2', '5', '_', 'Z', '2', '6', 0,
|
||||
/* 1946 */ 'b', '2', '6', 0,
|
||||
/* 1950 */ 'd', '2', '6', 0,
|
||||
/* 1954 */ 'h', '2', '6', 0,
|
||||
/* 1958 */ 'q', '2', '6', 0,
|
||||
/* 1962 */ 's', '2', '6', 0,
|
||||
/* 1966 */ 'w', '2', '6', 0,
|
||||
/* 1970 */ 'x', '2', '6', 0,
|
||||
/* 1974 */ 'z', '2', '6', 0,
|
||||
/* 1978 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', '_', 'D', '6', 0,
|
||||
/* 1990 */ 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', 0,
|
||||
/* 2002 */ 'W', '5', '_', 'W', '6', 0,
|
||||
/* 2008 */ 'X', '5', '_', 'X', '6', 0,
|
||||
/* 2014 */ 'Z', '3', '_', 'Z', '4', '_', 'Z', '5', '_', 'Z', '6', 0,
|
||||
/* 2026 */ 'b', '6', 0,
|
||||
/* 2029 */ 'd', '6', 0,
|
||||
/* 2032 */ 'h', '6', 0,
|
||||
/* 2035 */ 'p', '6', 0,
|
||||
/* 2038 */ 'q', '6', 0,
|
||||
/* 2041 */ 's', '6', 0,
|
||||
/* 2044 */ 'w', '6', 0,
|
||||
/* 2047 */ 'x', '6', 0,
|
||||
/* 2050 */ 'z', '6', 0,
|
||||
/* 2053 */ 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', 0,
|
||||
/* 2069 */ 'Q', '1', '4', '_', 'Q', '1', '5', '_', 'Q', '1', '6', '_', 'Q', '1', '7', 0,
|
||||
/* 2085 */ 'W', '1', '6', '_', 'W', '1', '7', 0,
|
||||
/* 2093 */ 'X', '1', '6', '_', 'X', '1', '7', 0,
|
||||
/* 2101 */ 'Z', '1', '4', '_', 'Z', '1', '5', '_', 'Z', '1', '6', '_', 'Z', '1', '7', 0,
|
||||
/* 2117 */ 'b', '1', '7', 0,
|
||||
/* 2121 */ 'd', '1', '7', 0,
|
||||
/* 2125 */ 'h', '1', '7', 0,
|
||||
/* 2129 */ 'q', '1', '7', 0,
|
||||
/* 2133 */ 's', '1', '7', 0,
|
||||
/* 2137 */ 'w', '1', '7', 0,
|
||||
/* 2141 */ 'x', '1', '7', 0,
|
||||
/* 2145 */ 'z', '1', '7', 0,
|
||||
/* 2149 */ 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', 0,
|
||||
/* 2165 */ 'Q', '2', '4', '_', 'Q', '2', '5', '_', 'Q', '2', '6', '_', 'Q', '2', '7', 0,
|
||||
/* 2181 */ 'W', '2', '6', '_', 'W', '2', '7', 0,
|
||||
/* 2189 */ 'X', '2', '6', '_', 'X', '2', '7', 0,
|
||||
/* 2197 */ 'Z', '2', '4', '_', 'Z', '2', '5', '_', 'Z', '2', '6', '_', 'Z', '2', '7', 0,
|
||||
/* 2213 */ 'b', '2', '7', 0,
|
||||
/* 2217 */ 'd', '2', '7', 0,
|
||||
/* 2221 */ 'h', '2', '7', 0,
|
||||
/* 2225 */ 'q', '2', '7', 0,
|
||||
/* 2229 */ 's', '2', '7', 0,
|
||||
/* 2233 */ 'w', '2', '7', 0,
|
||||
/* 2237 */ 'x', '2', '7', 0,
|
||||
/* 2241 */ 'z', '2', '7', 0,
|
||||
/* 2245 */ 'D', '4', '_', 'D', '5', '_', 'D', '6', '_', 'D', '7', 0,
|
||||
/* 2257 */ 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', 0,
|
||||
/* 2269 */ 'W', '6', '_', 'W', '7', 0,
|
||||
/* 2275 */ 'X', '6', '_', 'X', '7', 0,
|
||||
/* 2281 */ 'Z', '4', '_', 'Z', '5', '_', 'Z', '6', '_', 'Z', '7', 0,
|
||||
/* 2293 */ 'b', '7', 0,
|
||||
/* 2296 */ 'd', '7', 0,
|
||||
/* 2299 */ 'h', '7', 0,
|
||||
/* 2302 */ 'p', '7', 0,
|
||||
/* 2305 */ 'q', '7', 0,
|
||||
/* 2308 */ 's', '7', 0,
|
||||
/* 2311 */ 'w', '7', 0,
|
||||
/* 2314 */ 'x', '7', 0,
|
||||
/* 2317 */ 'z', '7', 0,
|
||||
/* 2320 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', 0,
|
||||
/* 2336 */ 'Q', '1', '5', '_', 'Q', '1', '6', '_', 'Q', '1', '7', '_', 'Q', '1', '8', 0,
|
||||
/* 2352 */ 'W', '1', '7', '_', 'W', '1', '8', 0,
|
||||
/* 2360 */ 'X', '1', '7', '_', 'X', '1', '8', 0,
|
||||
/* 2368 */ 'Z', '1', '5', '_', 'Z', '1', '6', '_', 'Z', '1', '7', '_', 'Z', '1', '8', 0,
|
||||
/* 2384 */ 'b', '1', '8', 0,
|
||||
/* 2388 */ 'd', '1', '8', 0,
|
||||
/* 2392 */ 'h', '1', '8', 0,
|
||||
/* 2396 */ 'q', '1', '8', 0,
|
||||
/* 2400 */ 's', '1', '8', 0,
|
||||
/* 2404 */ 'w', '1', '8', 0,
|
||||
/* 2408 */ 'x', '1', '8', 0,
|
||||
/* 2412 */ 'z', '1', '8', 0,
|
||||
/* 2416 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', 0,
|
||||
/* 2432 */ 'Q', '2', '5', '_', 'Q', '2', '6', '_', 'Q', '2', '7', '_', 'Q', '2', '8', 0,
|
||||
/* 2448 */ 'W', '2', '7', '_', 'W', '2', '8', 0,
|
||||
/* 2456 */ 'X', '2', '7', '_', 'X', '2', '8', 0,
|
||||
/* 2464 */ 'Z', '2', '5', '_', 'Z', '2', '6', '_', 'Z', '2', '7', '_', 'Z', '2', '8', 0,
|
||||
/* 2480 */ 'b', '2', '8', 0,
|
||||
/* 2484 */ 'd', '2', '8', 0,
|
||||
/* 2488 */ 'h', '2', '8', 0,
|
||||
/* 2492 */ 'q', '2', '8', 0,
|
||||
/* 2496 */ 's', '2', '8', 0,
|
||||
/* 2500 */ 'w', '2', '8', 0,
|
||||
/* 2504 */ 'x', '2', '8', 0,
|
||||
/* 2508 */ 'z', '2', '8', 0,
|
||||
/* 2512 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', '_', 'D', '8', 0,
|
||||
/* 2524 */ 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', 0,
|
||||
/* 2536 */ 'W', '7', '_', 'W', '8', 0,
|
||||
/* 2542 */ 'X', '7', '_', 'X', '8', 0,
|
||||
/* 2548 */ 'Z', '5', '_', 'Z', '6', '_', 'Z', '7', '_', 'Z', '8', 0,
|
||||
/* 2560 */ 'b', '8', 0,
|
||||
/* 2563 */ 'd', '8', 0,
|
||||
/* 2566 */ 'h', '8', 0,
|
||||
/* 2569 */ 'p', '8', 0,
|
||||
/* 2572 */ 'q', '8', 0,
|
||||
/* 2575 */ 's', '8', 0,
|
||||
/* 2578 */ 'w', '8', 0,
|
||||
/* 2581 */ 'x', '8', 0,
|
||||
/* 2584 */ 'z', '8', 0,
|
||||
/* 2587 */ 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', 0,
|
||||
/* 2603 */ 'Q', '1', '6', '_', 'Q', '1', '7', '_', 'Q', '1', '8', '_', 'Q', '1', '9', 0,
|
||||
/* 2619 */ 'W', '1', '8', '_', 'W', '1', '9', 0,
|
||||
/* 2627 */ 'X', '1', '8', '_', 'X', '1', '9', 0,
|
||||
/* 2635 */ 'Z', '1', '6', '_', 'Z', '1', '7', '_', 'Z', '1', '8', '_', 'Z', '1', '9', 0,
|
||||
/* 2651 */ 'b', '1', '9', 0,
|
||||
/* 2655 */ 'd', '1', '9', 0,
|
||||
/* 2659 */ 'h', '1', '9', 0,
|
||||
/* 2663 */ 'q', '1', '9', 0,
|
||||
/* 2667 */ 's', '1', '9', 0,
|
||||
/* 2671 */ 'w', '1', '9', 0,
|
||||
/* 2675 */ 'x', '1', '9', 0,
|
||||
/* 2679 */ 'z', '1', '9', 0,
|
||||
/* 2683 */ 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', 0,
|
||||
/* 2699 */ 'Q', '2', '6', '_', 'Q', '2', '7', '_', 'Q', '2', '8', '_', 'Q', '2', '9', 0,
|
||||
/* 2715 */ 'W', '2', '8', '_', 'W', '2', '9', 0,
|
||||
/* 2723 */ 'Z', '2', '6', '_', 'Z', '2', '7', '_', 'Z', '2', '8', '_', 'Z', '2', '9', 0,
|
||||
/* 2739 */ 'b', '2', '9', 0,
|
||||
/* 2743 */ 'd', '2', '9', 0,
|
||||
/* 2747 */ 'h', '2', '9', 0,
|
||||
/* 2751 */ 'q', '2', '9', 0,
|
||||
/* 2755 */ 's', '2', '9', 0,
|
||||
/* 2759 */ 'w', '2', '9', 0,
|
||||
/* 2763 */ 'x', '2', '9', 0,
|
||||
/* 2767 */ 'z', '2', '9', 0,
|
||||
/* 2771 */ 'D', '6', '_', 'D', '7', '_', 'D', '8', '_', 'D', '9', 0,
|
||||
/* 2783 */ 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', 0,
|
||||
/* 2795 */ 'W', '8', '_', 'W', '9', 0,
|
||||
/* 2801 */ 'X', '8', '_', 'X', '9', 0,
|
||||
/* 2807 */ 'Z', '6', '_', 'Z', '7', '_', 'Z', '8', '_', 'Z', '9', 0,
|
||||
/* 2819 */ 'b', '9', 0,
|
||||
/* 2822 */ 'd', '9', 0,
|
||||
/* 2825 */ 'h', '9', 0,
|
||||
/* 2828 */ 'p', '9', 0,
|
||||
/* 2831 */ 'q', '9', 0,
|
||||
/* 2834 */ 's', '9', 0,
|
||||
/* 2837 */ 'w', '9', 0,
|
||||
/* 2840 */ 'x', '9', 0,
|
||||
/* 2843 */ 'z', '9', 0,
|
||||
/* 2846 */ 'X', '2', '8', '_', 'F', 'P', 0,
|
||||
/* 2853 */ 'F', 'P', '_', 'L', 'R', 0,
|
||||
/* 2859 */ 'W', '3', '0', '_', 'W', 'Z', 'R', 0,
|
||||
/* 2867 */ 'L', 'R', '_', 'X', 'Z', 'R', 0,
|
||||
/* 2874 */ 'z', '1', '0', '_', 'h', 'i', 0,
|
||||
/* 2881 */ 'z', '2', '0', '_', 'h', 'i', 0,
|
||||
/* 2888 */ 'z', '3', '0', '_', 'h', 'i', 0,
|
||||
/* 2895 */ 'z', '0', '_', 'h', 'i', 0,
|
||||
/* 2901 */ 'z', '1', '1', '_', 'h', 'i', 0,
|
||||
/* 2908 */ 'z', '2', '1', '_', 'h', 'i', 0,
|
||||
/* 2915 */ 'z', '3', '1', '_', 'h', 'i', 0,
|
||||
/* 2922 */ 'z', '1', '_', 'h', 'i', 0,
|
||||
/* 2928 */ 'z', '1', '2', '_', 'h', 'i', 0,
|
||||
/* 2935 */ 'z', '2', '2', '_', 'h', 'i', 0,
|
||||
/* 2942 */ 'z', '2', '_', 'h', 'i', 0,
|
||||
/* 2948 */ 'z', '1', '3', '_', 'h', 'i', 0,
|
||||
/* 2955 */ 'z', '2', '3', '_', 'h', 'i', 0,
|
||||
/* 2962 */ 'z', '3', '_', 'h', 'i', 0,
|
||||
/* 2968 */ 'z', '1', '4', '_', 'h', 'i', 0,
|
||||
/* 2975 */ 'z', '2', '4', '_', 'h', 'i', 0,
|
||||
/* 2982 */ 'z', '4', '_', 'h', 'i', 0,
|
||||
/* 2988 */ 'z', '1', '5', '_', 'h', 'i', 0,
|
||||
/* 2995 */ 'z', '2', '5', '_', 'h', 'i', 0,
|
||||
/* 3002 */ 'z', '5', '_', 'h', 'i', 0,
|
||||
/* 3008 */ 'z', '1', '6', '_', 'h', 'i', 0,
|
||||
/* 3015 */ 'z', '2', '6', '_', 'h', 'i', 0,
|
||||
/* 3022 */ 'z', '6', '_', 'h', 'i', 0,
|
||||
/* 3028 */ 'z', '1', '7', '_', 'h', 'i', 0,
|
||||
/* 3035 */ 'z', '2', '7', '_', 'h', 'i', 0,
|
||||
/* 3042 */ 'z', '7', '_', 'h', 'i', 0,
|
||||
/* 3048 */ 'z', '1', '8', '_', 'h', 'i', 0,
|
||||
/* 3055 */ 'z', '2', '8', '_', 'h', 'i', 0,
|
||||
/* 3062 */ 'z', '8', '_', 'h', 'i', 0,
|
||||
/* 3068 */ 'z', '1', '9', '_', 'h', 'i', 0,
|
||||
/* 3075 */ 'z', '2', '9', '_', 'h', 'i', 0,
|
||||
/* 3082 */ 'z', '9', '_', 'h', 'i', 0,
|
||||
/* 3088 */ 'w', 's', 'p', 0,
|
||||
/* 3092 */ 'f', 'f', 'r', 0,
|
||||
/* 3096 */ 'w', 'z', 'r', 0,
|
||||
/* 3100 */ 'x', 'z', 'r', 0,
|
||||
/* 3104 */ 'n', 'z', 'c', 'v', 0,
|
||||
};
|
||||
|
||||
static const uint16_t RegAsmOffsetNoRegAltName[] = {
|
||||
3092, 2763, 265, 3104, 3089, 3088, 3096, 3100, 332, 675, 946, 1217, 1488, 1759,
|
||||
2026, 2293, 2560, 2819, 53, 417, 763, 1037, 1308, 1579, 1850, 2117, 2384, 2651,
|
||||
153, 517, 863, 1137, 1408, 1679, 1946, 2213, 2480, 2739, 241, 597, 335, 678,
|
||||
949, 1220, 1491, 1762, 2029, 2296, 2563, 2822, 57, 421, 767, 1041, 1312, 1583,
|
||||
1854, 2121, 2388, 2655, 157, 521, 867, 1141, 1412, 1683, 1950, 2217, 2484, 2743,
|
||||
245, 601, 338, 681, 952, 1223, 1494, 1765, 2032, 2299, 2566, 2825, 61, 425,
|
||||
771, 1045, 1316, 1587, 1858, 2125, 2392, 2659, 161, 525, 871, 1145, 1416, 1687,
|
||||
1954, 2221, 2488, 2747, 249, 605, 341, 684, 955, 1226, 1497, 1768, 2035, 2302,
|
||||
2569, 2828, 65, 429, 775, 1049, 1320, 1591, 344, 687, 958, 1229, 1500, 1771,
|
||||
2038, 2305, 2572, 2831, 69, 433, 779, 1053, 1324, 1595, 1862, 2129, 2396, 2663,
|
||||
165, 529, 875, 1149, 1420, 1691, 1958, 2225, 2492, 2751, 253, 609, 347, 690,
|
||||
961, 1232, 1503, 1774, 2041, 2308, 2575, 2834, 73, 437, 783, 1057, 1328, 1599,
|
||||
1866, 2133, 2400, 2667, 169, 533, 879, 1153, 1424, 1695, 1962, 2229, 2496, 2755,
|
||||
257, 613, 350, 693, 964, 1235, 1506, 1777, 2044, 2311, 2578, 2837, 77, 441,
|
||||
787, 1061, 1332, 1603, 1870, 2137, 2404, 2671, 173, 537, 883, 1157, 1428, 1699,
|
||||
1966, 2233, 2500, 2759, 261, 353, 696, 967, 1238, 1509, 1780, 2047, 2314, 2581,
|
||||
2840, 81, 445, 791, 1065, 1336, 1607, 1874, 2141, 2408, 2675, 177, 541, 887,
|
||||
1161, 1432, 1703, 1970, 2237, 2504, 356, 699, 970, 1241, 1512, 1783, 2050, 2317,
|
||||
2584, 2843, 85, 449, 795, 1069, 1340, 1611, 1878, 2145, 2412, 2679, 181, 545,
|
||||
891, 1165, 1436, 1707, 1974, 2241, 2508, 2767, 269, 617, 2895, 2922, 2942, 2962,
|
||||
2982, 3002, 3022, 3042, 3062, 3082, 2874, 2901, 2928, 2948, 2968, 2988, 3008, 3028,
|
||||
3048, 3068, 2881, 2908, 2935, 2955, 2975, 2995, 3015, 3035, 3055, 3075, 2888, 2915,
|
||||
629, 902, 1175, 1446, 1717, 1984, 2251, 2518, 2777, 6, 365, 709, 981, 1252,
|
||||
1523, 1794, 2061, 2328, 2595, 97, 461, 807, 1081, 1352, 1623, 1890, 2157, 2424,
|
||||
2691, 193, 557, 281, 1169, 1440, 1711, 1978, 2245, 2512, 2771, 0, 359, 702,
|
||||
973, 1244, 1515, 1786, 2053, 2320, 2587, 89, 453, 799, 1073, 1344, 1615, 1882,
|
||||
2149, 2416, 2683, 185, 549, 273, 621, 895, 899, 1172, 1443, 1714, 1981, 2248,
|
||||
2515, 2774, 3, 362, 705, 977, 1248, 1519, 1790, 2057, 2324, 2591, 93, 457,
|
||||
803, 1077, 1348, 1619, 1886, 2153, 2420, 2687, 189, 553, 277, 625, 643, 915,
|
||||
1187, 1458, 1729, 1996, 2263, 2530, 2789, 19, 379, 724, 997, 1268, 1539, 1810,
|
||||
2077, 2344, 2611, 113, 477, 823, 1097, 1368, 1639, 1906, 2173, 2440, 2707, 209,
|
||||
573, 296, 1181, 1452, 1723, 1990, 2257, 2524, 2783, 13, 373, 717, 989, 1260,
|
||||
1531, 1802, 2069, 2336, 2603, 105, 469, 815, 1089, 1360, 1631, 1898, 2165, 2432,
|
||||
2699, 201, 565, 288, 635, 908, 912, 1184, 1455, 1726, 1993, 2260, 2527, 2786,
|
||||
16, 376, 720, 993, 1264, 1535, 1806, 2073, 2340, 2607, 109, 473, 819, 1093,
|
||||
1364, 1635, 1902, 2169, 2436, 2703, 205, 569, 292, 639, 303, 2859, 649, 921,
|
||||
1193, 1464, 1735, 2002, 2269, 2536, 2795, 26, 387, 732, 1005, 1276, 1547, 1818,
|
||||
2085, 2352, 2619, 121, 485, 831, 1105, 1376, 1647, 1914, 2181, 2448, 2715, 217,
|
||||
2853, 2867, 310, 2846, 655, 927, 1199, 1470, 1741, 2008, 2275, 2542, 2801, 33,
|
||||
395, 740, 1013, 1284, 1555, 1826, 2093, 2360, 2627, 129, 493, 839, 1113, 1384,
|
||||
1655, 1922, 2189, 2456, 669, 940, 1211, 1482, 1753, 2020, 2287, 2554, 2813, 46,
|
||||
409, 755, 1029, 1300, 1571, 1842, 2109, 2376, 2643, 145, 509, 855, 1129, 1400,
|
||||
1671, 1938, 2205, 2472, 2731, 233, 589, 325, 1205, 1476, 1747, 2014, 2281, 2548,
|
||||
2807, 40, 403, 748, 1021, 1292, 1563, 1834, 2101, 2368, 2635, 137, 501, 847,
|
||||
1121, 1392, 1663, 1930, 2197, 2464, 2723, 225, 581, 317, 661, 933, 937, 1208,
|
||||
1479, 1750, 2017, 2284, 2551, 2810, 43, 406, 751, 1025, 1296, 1567, 1838, 2105,
|
||||
2372, 2639, 141, 505, 851, 1125, 1396, 1667, 1934, 2201, 2468, 2727, 229, 585,
|
||||
321, 665,
|
||||
};
|
||||
|
||||
static const char AsmStrsvlist1[] = {
|
||||
/* 0 */ 0,
|
||||
};
|
||||
|
||||
static const uint8_t RegAsmOffsetvlist1[] = {
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0,
|
||||
};
|
||||
|
||||
static const char AsmStrsvreg[] = {
|
||||
/* 0 */ 'v', '1', '0', 0,
|
||||
/* 4 */ 'v', '2', '0', 0,
|
||||
/* 8 */ 'v', '3', '0', 0,
|
||||
/* 12 */ 'v', '0', 0,
|
||||
/* 15 */ 'v', '1', '1', 0,
|
||||
/* 19 */ 'v', '2', '1', 0,
|
||||
/* 23 */ 'v', '3', '1', 0,
|
||||
/* 27 */ 'v', '1', 0,
|
||||
/* 30 */ 'v', '1', '2', 0,
|
||||
/* 34 */ 'v', '2', '2', 0,
|
||||
/* 38 */ 'v', '2', 0,
|
||||
/* 41 */ 'v', '1', '3', 0,
|
||||
/* 45 */ 'v', '2', '3', 0,
|
||||
/* 49 */ 'v', '3', 0,
|
||||
/* 52 */ 'v', '1', '4', 0,
|
||||
/* 56 */ 'v', '2', '4', 0,
|
||||
/* 60 */ 'v', '4', 0,
|
||||
/* 63 */ 'v', '1', '5', 0,
|
||||
/* 67 */ 'v', '2', '5', 0,
|
||||
/* 71 */ 'v', '5', 0,
|
||||
/* 74 */ 'v', '1', '6', 0,
|
||||
/* 78 */ 'v', '2', '6', 0,
|
||||
/* 82 */ 'v', '6', 0,
|
||||
/* 85 */ 'v', '1', '7', 0,
|
||||
/* 89 */ 'v', '2', '7', 0,
|
||||
/* 93 */ 'v', '7', 0,
|
||||
/* 96 */ 'v', '1', '8', 0,
|
||||
/* 100 */ 'v', '2', '8', 0,
|
||||
/* 104 */ 'v', '8', 0,
|
||||
/* 107 */ 'v', '1', '9', 0,
|
||||
/* 111 */ 'v', '2', '9', 0,
|
||||
/* 115 */ 'v', '9', 0,
|
||||
};
|
||||
|
||||
static const uint8_t RegAsmOffsetvreg[] = {
|
||||
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
||||
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
||||
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 12, 27,
|
||||
38, 49, 60, 71, 82, 93, 104, 115, 0, 15, 30, 41, 52, 63,
|
||||
74, 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, 89, 100, 111,
|
||||
8, 23, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
||||
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
||||
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
||||
3, 3, 3, 3, 3, 3, 3, 3, 12, 27, 38, 49, 60, 71,
|
||||
82, 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 107,
|
||||
4, 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, 23, 3, 3,
|
||||
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
||||
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
||||
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
||||
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
||||
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
||||
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
||||
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
||||
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
||||
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
||||
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
||||
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
||||
12, 27, 38, 49, 60, 71, 82, 93, 104, 115, 0, 15, 30, 41,
|
||||
52, 63, 74, 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, 89,
|
||||
100, 111, 8, 23, 12, 27, 38, 49, 60, 71, 82, 93, 104, 115,
|
||||
0, 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, 45,
|
||||
56, 67, 78, 89, 100, 111, 8, 23, 12, 27, 38, 49, 60, 71,
|
||||
82, 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 107,
|
||||
4, 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, 23, 12, 27,
|
||||
38, 49, 60, 71, 82, 93, 104, 115, 0, 15, 30, 41, 52, 63,
|
||||
74, 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, 89, 100, 111,
|
||||
8, 23, 12, 27, 38, 49, 60, 71, 82, 93, 104, 115, 0, 15,
|
||||
30, 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, 45, 56, 67,
|
||||
78, 89, 100, 111, 8, 23, 12, 27, 38, 49, 60, 71, 82, 93,
|
||||
104, 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 19,
|
||||
34, 45, 56, 67, 78, 89, 100, 111, 8, 23, 3, 3, 3, 3,
|
||||
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
||||
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
||||
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
||||
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
||||
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
||||
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
||||
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
||||
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
||||
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
||||
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
||||
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
||||
3, 3,
|
||||
};
|
||||
|
||||
switch(AltIdx) {
|
||||
default:
|
||||
return (const char *)(sizeof(RegAsmOffsetvreg)/sizeof(RegAsmOffsetvreg[0]));
|
||||
case AArch64_NoRegAltName:
|
||||
return AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1];
|
||||
case AArch64_vlist1:
|
||||
return AsmStrsvlist1+RegAsmOffsetvlist1[RegNo-1];
|
||||
case AArch64_vreg:
|
||||
return AsmStrsvreg+RegAsmOffsetvreg[RegNo-1];
|
||||
}
|
||||
#else
|
||||
return NULL;
|
||||
#endif
|
||||
}
|
||||
660
arch/AArch64/AArch64GenRegisterV.inc
Normal file
660
arch/AArch64/AArch64GenRegisterV.inc
Normal file
@ -0,0 +1,660 @@
|
||||
// size = 660
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
ARM64_REG_V0,
|
||||
ARM64_REG_V1,
|
||||
ARM64_REG_V2,
|
||||
ARM64_REG_V3,
|
||||
ARM64_REG_V4,
|
||||
ARM64_REG_V5,
|
||||
ARM64_REG_V6,
|
||||
ARM64_REG_V7,
|
||||
ARM64_REG_V8,
|
||||
ARM64_REG_V9,
|
||||
ARM64_REG_V10,
|
||||
ARM64_REG_V11,
|
||||
ARM64_REG_V12,
|
||||
ARM64_REG_V13,
|
||||
ARM64_REG_V14,
|
||||
ARM64_REG_V15,
|
||||
ARM64_REG_V16,
|
||||
ARM64_REG_V17,
|
||||
ARM64_REG_V18,
|
||||
ARM64_REG_V19,
|
||||
ARM64_REG_V20,
|
||||
ARM64_REG_V21,
|
||||
ARM64_REG_V22,
|
||||
ARM64_REG_V23,
|
||||
ARM64_REG_V24,
|
||||
ARM64_REG_V25,
|
||||
ARM64_REG_V26,
|
||||
ARM64_REG_V27,
|
||||
ARM64_REG_V28,
|
||||
ARM64_REG_V29,
|
||||
ARM64_REG_V30,
|
||||
ARM64_REG_V31,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
ARM64_REG_V0,
|
||||
ARM64_REG_V1,
|
||||
ARM64_REG_V2,
|
||||
ARM64_REG_V3,
|
||||
ARM64_REG_V4,
|
||||
ARM64_REG_V5,
|
||||
ARM64_REG_V6,
|
||||
ARM64_REG_V7,
|
||||
ARM64_REG_V8,
|
||||
ARM64_REG_V9,
|
||||
ARM64_REG_V10,
|
||||
ARM64_REG_V11,
|
||||
ARM64_REG_V12,
|
||||
ARM64_REG_V13,
|
||||
ARM64_REG_V14,
|
||||
ARM64_REG_V15,
|
||||
ARM64_REG_V16,
|
||||
ARM64_REG_V17,
|
||||
ARM64_REG_V18,
|
||||
ARM64_REG_V19,
|
||||
ARM64_REG_V20,
|
||||
ARM64_REG_V21,
|
||||
ARM64_REG_V22,
|
||||
ARM64_REG_V23,
|
||||
ARM64_REG_V24,
|
||||
ARM64_REG_V25,
|
||||
ARM64_REG_V26,
|
||||
ARM64_REG_V27,
|
||||
ARM64_REG_V28,
|
||||
ARM64_REG_V29,
|
||||
ARM64_REG_V30,
|
||||
ARM64_REG_V31,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
ARM64_REG_V0,
|
||||
ARM64_REG_V1,
|
||||
ARM64_REG_V2,
|
||||
ARM64_REG_V3,
|
||||
ARM64_REG_V4,
|
||||
ARM64_REG_V5,
|
||||
ARM64_REG_V6,
|
||||
ARM64_REG_V7,
|
||||
ARM64_REG_V8,
|
||||
ARM64_REG_V9,
|
||||
ARM64_REG_V10,
|
||||
ARM64_REG_V11,
|
||||
ARM64_REG_V12,
|
||||
ARM64_REG_V13,
|
||||
ARM64_REG_V14,
|
||||
ARM64_REG_V15,
|
||||
ARM64_REG_V16,
|
||||
ARM64_REG_V17,
|
||||
ARM64_REG_V18,
|
||||
ARM64_REG_V19,
|
||||
ARM64_REG_V20,
|
||||
ARM64_REG_V21,
|
||||
ARM64_REG_V22,
|
||||
ARM64_REG_V23,
|
||||
ARM64_REG_V24,
|
||||
ARM64_REG_V25,
|
||||
ARM64_REG_V26,
|
||||
ARM64_REG_V27,
|
||||
ARM64_REG_V28,
|
||||
ARM64_REG_V29,
|
||||
ARM64_REG_V30,
|
||||
ARM64_REG_V31,
|
||||
ARM64_REG_V0,
|
||||
ARM64_REG_V1,
|
||||
ARM64_REG_V2,
|
||||
ARM64_REG_V3,
|
||||
ARM64_REG_V4,
|
||||
ARM64_REG_V5,
|
||||
ARM64_REG_V6,
|
||||
ARM64_REG_V7,
|
||||
ARM64_REG_V8,
|
||||
ARM64_REG_V9,
|
||||
ARM64_REG_V10,
|
||||
ARM64_REG_V11,
|
||||
ARM64_REG_V12,
|
||||
ARM64_REG_V13,
|
||||
ARM64_REG_V14,
|
||||
ARM64_REG_V15,
|
||||
ARM64_REG_V16,
|
||||
ARM64_REG_V17,
|
||||
ARM64_REG_V18,
|
||||
ARM64_REG_V19,
|
||||
ARM64_REG_V20,
|
||||
ARM64_REG_V21,
|
||||
ARM64_REG_V22,
|
||||
ARM64_REG_V23,
|
||||
ARM64_REG_V24,
|
||||
ARM64_REG_V25,
|
||||
ARM64_REG_V26,
|
||||
ARM64_REG_V27,
|
||||
ARM64_REG_V28,
|
||||
ARM64_REG_V29,
|
||||
ARM64_REG_V30,
|
||||
ARM64_REG_V31,
|
||||
ARM64_REG_V0,
|
||||
ARM64_REG_V1,
|
||||
ARM64_REG_V2,
|
||||
ARM64_REG_V3,
|
||||
ARM64_REG_V4,
|
||||
ARM64_REG_V5,
|
||||
ARM64_REG_V6,
|
||||
ARM64_REG_V7,
|
||||
ARM64_REG_V8,
|
||||
ARM64_REG_V9,
|
||||
ARM64_REG_V10,
|
||||
ARM64_REG_V11,
|
||||
ARM64_REG_V12,
|
||||
ARM64_REG_V13,
|
||||
ARM64_REG_V14,
|
||||
ARM64_REG_V15,
|
||||
ARM64_REG_V16,
|
||||
ARM64_REG_V17,
|
||||
ARM64_REG_V18,
|
||||
ARM64_REG_V19,
|
||||
ARM64_REG_V20,
|
||||
ARM64_REG_V21,
|
||||
ARM64_REG_V22,
|
||||
ARM64_REG_V23,
|
||||
ARM64_REG_V24,
|
||||
ARM64_REG_V25,
|
||||
ARM64_REG_V26,
|
||||
ARM64_REG_V27,
|
||||
ARM64_REG_V28,
|
||||
ARM64_REG_V29,
|
||||
ARM64_REG_V30,
|
||||
ARM64_REG_V31,
|
||||
ARM64_REG_V0,
|
||||
ARM64_REG_V1,
|
||||
ARM64_REG_V2,
|
||||
ARM64_REG_V3,
|
||||
ARM64_REG_V4,
|
||||
ARM64_REG_V5,
|
||||
ARM64_REG_V6,
|
||||
ARM64_REG_V7,
|
||||
ARM64_REG_V8,
|
||||
ARM64_REG_V9,
|
||||
ARM64_REG_V10,
|
||||
ARM64_REG_V11,
|
||||
ARM64_REG_V12,
|
||||
ARM64_REG_V13,
|
||||
ARM64_REG_V14,
|
||||
ARM64_REG_V15,
|
||||
ARM64_REG_V16,
|
||||
ARM64_REG_V17,
|
||||
ARM64_REG_V18,
|
||||
ARM64_REG_V19,
|
||||
ARM64_REG_V20,
|
||||
ARM64_REG_V21,
|
||||
ARM64_REG_V22,
|
||||
ARM64_REG_V23,
|
||||
ARM64_REG_V24,
|
||||
ARM64_REG_V25,
|
||||
ARM64_REG_V26,
|
||||
ARM64_REG_V27,
|
||||
ARM64_REG_V28,
|
||||
ARM64_REG_V29,
|
||||
ARM64_REG_V30,
|
||||
ARM64_REG_V31,
|
||||
ARM64_REG_V0,
|
||||
ARM64_REG_V1,
|
||||
ARM64_REG_V2,
|
||||
ARM64_REG_V3,
|
||||
ARM64_REG_V4,
|
||||
ARM64_REG_V5,
|
||||
ARM64_REG_V6,
|
||||
ARM64_REG_V7,
|
||||
ARM64_REG_V8,
|
||||
ARM64_REG_V9,
|
||||
ARM64_REG_V10,
|
||||
ARM64_REG_V11,
|
||||
ARM64_REG_V12,
|
||||
ARM64_REG_V13,
|
||||
ARM64_REG_V14,
|
||||
ARM64_REG_V15,
|
||||
ARM64_REG_V16,
|
||||
ARM64_REG_V17,
|
||||
ARM64_REG_V18,
|
||||
ARM64_REG_V19,
|
||||
ARM64_REG_V20,
|
||||
ARM64_REG_V21,
|
||||
ARM64_REG_V22,
|
||||
ARM64_REG_V23,
|
||||
ARM64_REG_V24,
|
||||
ARM64_REG_V25,
|
||||
ARM64_REG_V26,
|
||||
ARM64_REG_V27,
|
||||
ARM64_REG_V28,
|
||||
ARM64_REG_V29,
|
||||
ARM64_REG_V30,
|
||||
ARM64_REG_V31,
|
||||
ARM64_REG_V0,
|
||||
ARM64_REG_V1,
|
||||
ARM64_REG_V2,
|
||||
ARM64_REG_V3,
|
||||
ARM64_REG_V4,
|
||||
ARM64_REG_V5,
|
||||
ARM64_REG_V6,
|
||||
ARM64_REG_V7,
|
||||
ARM64_REG_V8,
|
||||
ARM64_REG_V9,
|
||||
ARM64_REG_V10,
|
||||
ARM64_REG_V11,
|
||||
ARM64_REG_V12,
|
||||
ARM64_REG_V13,
|
||||
ARM64_REG_V14,
|
||||
ARM64_REG_V15,
|
||||
ARM64_REG_V16,
|
||||
ARM64_REG_V17,
|
||||
ARM64_REG_V18,
|
||||
ARM64_REG_V19,
|
||||
ARM64_REG_V20,
|
||||
ARM64_REG_V21,
|
||||
ARM64_REG_V22,
|
||||
ARM64_REG_V23,
|
||||
ARM64_REG_V24,
|
||||
ARM64_REG_V25,
|
||||
ARM64_REG_V26,
|
||||
ARM64_REG_V27,
|
||||
ARM64_REG_V28,
|
||||
ARM64_REG_V29,
|
||||
ARM64_REG_V30,
|
||||
ARM64_REG_V31,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
@ -1,29 +1,82 @@
|
||||
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|
||||
|* *|
|
||||
|*Subtarget Enumeration Source Fragment *|
|
||||
|
||||
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
|
||||
|
||||
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*|* *|
|
||||
|* Subtarget Enumeration Source Fragment *|
|
||||
|* *|
|
||||
|* Automatically generated file, do not edit! *|
|
||||
|* *|
|
||||
\*===----------------------------------------------------------------------===*/
|
||||
|
||||
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
|
||||
|
||||
|
||||
#ifdef GET_SUBTARGETINFO_ENUM
|
||||
#undef GET_SUBTARGETINFO_ENUM
|
||||
|
||||
enum {
|
||||
AArch64_FeatureCRC = 1ULL << 0,
|
||||
AArch64_FeatureCrypto = 1ULL << 1,
|
||||
AArch64_FeatureFPARMv8 = 1ULL << 2,
|
||||
AArch64_FeatureNEON = 1ULL << 3,
|
||||
AArch64_FeatureZCRegMove = 1ULL << 4,
|
||||
AArch64_FeatureZCZeroing = 1ULL << 5,
|
||||
AArch64_ProcA53 = 1ULL << 6,
|
||||
AArch64_ProcA57 = 1ULL << 7,
|
||||
AArch64_ProcCyclone = 1ULL << 8
|
||||
AArch64_FeatureAES = 0,
|
||||
AArch64_FeatureAggressiveFMA = 1,
|
||||
AArch64_FeatureAlternateSExtLoadCVTF32Pattern = 2,
|
||||
AArch64_FeatureArithmeticBccFusion = 3,
|
||||
AArch64_FeatureArithmeticCbzFusion = 4,
|
||||
AArch64_FeatureBalanceFPOps = 5,
|
||||
AArch64_FeatureCRC = 6,
|
||||
AArch64_FeatureCrypto = 7,
|
||||
AArch64_FeatureCustomCheapAsMoveHandling = 8,
|
||||
AArch64_FeatureDisableLatencySchedHeuristic = 9,
|
||||
AArch64_FeatureDotProd = 10,
|
||||
AArch64_FeatureExynosCheapAsMoveHandling = 11,
|
||||
AArch64_FeatureFPARMv8 = 12,
|
||||
AArch64_FeatureFullFP16 = 13,
|
||||
AArch64_FeatureFuseAES = 14,
|
||||
AArch64_FeatureFuseAddress = 15,
|
||||
AArch64_FeatureFuseCCSelect = 16,
|
||||
AArch64_FeatureFuseLiterals = 17,
|
||||
AArch64_FeatureLSE = 18,
|
||||
AArch64_FeatureLSLFast = 19,
|
||||
AArch64_FeatureNEON = 20,
|
||||
AArch64_FeatureNoNegativeImmediates = 21,
|
||||
AArch64_FeaturePerfMon = 22,
|
||||
AArch64_FeaturePostRAScheduler = 23,
|
||||
AArch64_FeaturePredictableSelectIsExpensive = 24,
|
||||
AArch64_FeatureRAS = 25,
|
||||
AArch64_FeatureRCPC = 26,
|
||||
AArch64_FeatureRDM = 27,
|
||||
AArch64_FeatureReserveX18 = 28,
|
||||
AArch64_FeatureReserveX20 = 29,
|
||||
AArch64_FeatureSHA2 = 30,
|
||||
AArch64_FeatureSHA3 = 31,
|
||||
AArch64_FeatureSM4 = 32,
|
||||
AArch64_FeatureSPE = 33,
|
||||
AArch64_FeatureSVE = 34,
|
||||
AArch64_FeatureSlowMisaligned128Store = 35,
|
||||
AArch64_FeatureSlowPaired128 = 36,
|
||||
AArch64_FeatureSlowSTRQro = 37,
|
||||
AArch64_FeatureStrictAlign = 38,
|
||||
AArch64_FeatureUseAA = 39,
|
||||
AArch64_FeatureUseRSqrt = 40,
|
||||
AArch64_FeatureZCRegMove = 41,
|
||||
AArch64_FeatureZCZeroing = 42,
|
||||
AArch64_FeatureZCZeroingFPWorkaround = 43,
|
||||
AArch64_HasV8_1aOps = 44,
|
||||
AArch64_HasV8_2aOps = 45,
|
||||
AArch64_HasV8_3aOps = 46,
|
||||
AArch64_HasV8_4aOps = 47,
|
||||
AArch64_ProcA35 = 48,
|
||||
AArch64_ProcA53 = 49,
|
||||
AArch64_ProcA55 = 50,
|
||||
AArch64_ProcA57 = 51,
|
||||
AArch64_ProcA72 = 52,
|
||||
AArch64_ProcA73 = 53,
|
||||
AArch64_ProcA75 = 54,
|
||||
AArch64_ProcCyclone = 55,
|
||||
AArch64_ProcExynosM1 = 56,
|
||||
AArch64_ProcExynosM2 = 57,
|
||||
AArch64_ProcExynosM3 = 58,
|
||||
AArch64_ProcFalkor = 59,
|
||||
AArch64_ProcKryo = 60,
|
||||
AArch64_ProcSaphira = 61,
|
||||
AArch64_ProcThunderX = 62,
|
||||
AArch64_ProcThunderX2T99 = 63,
|
||||
AArch64_ProcThunderXT81 = 64,
|
||||
AArch64_ProcThunderXT83 = 65,
|
||||
AArch64_ProcThunderXT88 = 66,
|
||||
};
|
||||
|
||||
#endif // GET_SUBTARGETINFO_ENUM
|
||||
|
||||
|
||||
2049
arch/AArch64/AArch64GenSystemOperands.inc
Normal file
2049
arch/AArch64/AArch64GenSystemOperands.inc
Normal file
File diff suppressed because it is too large
Load Diff
19
arch/AArch64/AArch64GenSystemOperands_enum.inc
Normal file
19
arch/AArch64/AArch64GenSystemOperands_enum.inc
Normal file
@ -0,0 +1,19 @@
|
||||
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
|
||||
|
||||
enum PStateValues {
|
||||
AArch64PState_SPSel = 5,
|
||||
AArch64PState_DAIFSet = 30,
|
||||
AArch64PState_DAIFClr = 31,
|
||||
AArch64PState_PAN = 4,
|
||||
AArch64PState_UAO = 3,
|
||||
AArch64PState_DIT = 26,
|
||||
};
|
||||
|
||||
enum ExactFPImmValues {
|
||||
AArch64ExactFPImm_zero = 0,
|
||||
AArch64ExactFPImm_half = 1,
|
||||
AArch64ExactFPImm_one = 2,
|
||||
AArch64ExactFPImm_two = 3,
|
||||
};
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -14,269 +14,327 @@
|
||||
#include "AArch64GenInstrInfo.inc"
|
||||
|
||||
#ifndef CAPSTONE_DIET
|
||||
static const name_map reg_name_maps[] = {
|
||||
{ ARM64_REG_INVALID, NULL },
|
||||
// NOTE: this reg_name_maps[] reflects the order of registers in arm64_reg
|
||||
static const char *reg_name_maps[] = {
|
||||
NULL, /* ARM64_REG_INVALID */
|
||||
|
||||
{ ARM64_REG_X29, "x29"},
|
||||
{ ARM64_REG_X30, "x30"},
|
||||
{ ARM64_REG_NZCV, "nzcv"},
|
||||
{ ARM64_REG_SP, "sp"},
|
||||
{ ARM64_REG_WSP, "wsp"},
|
||||
{ ARM64_REG_WZR, "wzr"},
|
||||
{ ARM64_REG_XZR, "xzr"},
|
||||
{ ARM64_REG_B0, "b0"},
|
||||
{ ARM64_REG_B1, "b1"},
|
||||
{ ARM64_REG_B2, "b2"},
|
||||
{ ARM64_REG_B3, "b3"},
|
||||
{ ARM64_REG_B4, "b4"},
|
||||
{ ARM64_REG_B5, "b5"},
|
||||
{ ARM64_REG_B6, "b6"},
|
||||
{ ARM64_REG_B7, "b7"},
|
||||
{ ARM64_REG_B8, "b8"},
|
||||
{ ARM64_REG_B9, "b9"},
|
||||
{ ARM64_REG_B10, "b10"},
|
||||
{ ARM64_REG_B11, "b11"},
|
||||
{ ARM64_REG_B12, "b12"},
|
||||
{ ARM64_REG_B13, "b13"},
|
||||
{ ARM64_REG_B14, "b14"},
|
||||
{ ARM64_REG_B15, "b15"},
|
||||
{ ARM64_REG_B16, "b16"},
|
||||
{ ARM64_REG_B17, "b17"},
|
||||
{ ARM64_REG_B18, "b18"},
|
||||
{ ARM64_REG_B19, "b19"},
|
||||
{ ARM64_REG_B20, "b20"},
|
||||
{ ARM64_REG_B21, "b21"},
|
||||
{ ARM64_REG_B22, "b22"},
|
||||
{ ARM64_REG_B23, "b23"},
|
||||
{ ARM64_REG_B24, "b24"},
|
||||
{ ARM64_REG_B25, "b25"},
|
||||
{ ARM64_REG_B26, "b26"},
|
||||
{ ARM64_REG_B27, "b27"},
|
||||
{ ARM64_REG_B28, "b28"},
|
||||
{ ARM64_REG_B29, "b29"},
|
||||
{ ARM64_REG_B30, "b30"},
|
||||
{ ARM64_REG_B31, "b31"},
|
||||
{ ARM64_REG_D0, "d0"},
|
||||
{ ARM64_REG_D1, "d1"},
|
||||
{ ARM64_REG_D2, "d2"},
|
||||
{ ARM64_REG_D3, "d3"},
|
||||
{ ARM64_REG_D4, "d4"},
|
||||
{ ARM64_REG_D5, "d5"},
|
||||
{ ARM64_REG_D6, "d6"},
|
||||
{ ARM64_REG_D7, "d7"},
|
||||
{ ARM64_REG_D8, "d8"},
|
||||
{ ARM64_REG_D9, "d9"},
|
||||
{ ARM64_REG_D10, "d10"},
|
||||
{ ARM64_REG_D11, "d11"},
|
||||
{ ARM64_REG_D12, "d12"},
|
||||
{ ARM64_REG_D13, "d13"},
|
||||
{ ARM64_REG_D14, "d14"},
|
||||
{ ARM64_REG_D15, "d15"},
|
||||
{ ARM64_REG_D16, "d16"},
|
||||
{ ARM64_REG_D17, "d17"},
|
||||
{ ARM64_REG_D18, "d18"},
|
||||
{ ARM64_REG_D19, "d19"},
|
||||
{ ARM64_REG_D20, "d20"},
|
||||
{ ARM64_REG_D21, "d21"},
|
||||
{ ARM64_REG_D22, "d22"},
|
||||
{ ARM64_REG_D23, "d23"},
|
||||
{ ARM64_REG_D24, "d24"},
|
||||
{ ARM64_REG_D25, "d25"},
|
||||
{ ARM64_REG_D26, "d26"},
|
||||
{ ARM64_REG_D27, "d27"},
|
||||
{ ARM64_REG_D28, "d28"},
|
||||
{ ARM64_REG_D29, "d29"},
|
||||
{ ARM64_REG_D30, "d30"},
|
||||
{ ARM64_REG_D31, "d31"},
|
||||
{ ARM64_REG_H0, "h0"},
|
||||
{ ARM64_REG_H1, "h1"},
|
||||
{ ARM64_REG_H2, "h2"},
|
||||
{ ARM64_REG_H3, "h3"},
|
||||
{ ARM64_REG_H4, "h4"},
|
||||
{ ARM64_REG_H5, "h5"},
|
||||
{ ARM64_REG_H6, "h6"},
|
||||
{ ARM64_REG_H7, "h7"},
|
||||
{ ARM64_REG_H8, "h8"},
|
||||
{ ARM64_REG_H9, "h9"},
|
||||
{ ARM64_REG_H10, "h10"},
|
||||
{ ARM64_REG_H11, "h11"},
|
||||
{ ARM64_REG_H12, "h12"},
|
||||
{ ARM64_REG_H13, "h13"},
|
||||
{ ARM64_REG_H14, "h14"},
|
||||
{ ARM64_REG_H15, "h15"},
|
||||
{ ARM64_REG_H16, "h16"},
|
||||
{ ARM64_REG_H17, "h17"},
|
||||
{ ARM64_REG_H18, "h18"},
|
||||
{ ARM64_REG_H19, "h19"},
|
||||
{ ARM64_REG_H20, "h20"},
|
||||
{ ARM64_REG_H21, "h21"},
|
||||
{ ARM64_REG_H22, "h22"},
|
||||
{ ARM64_REG_H23, "h23"},
|
||||
{ ARM64_REG_H24, "h24"},
|
||||
{ ARM64_REG_H25, "h25"},
|
||||
{ ARM64_REG_H26, "h26"},
|
||||
{ ARM64_REG_H27, "h27"},
|
||||
{ ARM64_REG_H28, "h28"},
|
||||
{ ARM64_REG_H29, "h29"},
|
||||
{ ARM64_REG_H30, "h30"},
|
||||
{ ARM64_REG_H31, "h31"},
|
||||
{ ARM64_REG_Q0, "q0"},
|
||||
{ ARM64_REG_Q1, "q1"},
|
||||
{ ARM64_REG_Q2, "q2"},
|
||||
{ ARM64_REG_Q3, "q3"},
|
||||
{ ARM64_REG_Q4, "q4"},
|
||||
{ ARM64_REG_Q5, "q5"},
|
||||
{ ARM64_REG_Q6, "q6"},
|
||||
{ ARM64_REG_Q7, "q7"},
|
||||
{ ARM64_REG_Q8, "q8"},
|
||||
{ ARM64_REG_Q9, "q9"},
|
||||
{ ARM64_REG_Q10, "q10"},
|
||||
{ ARM64_REG_Q11, "q11"},
|
||||
{ ARM64_REG_Q12, "q12"},
|
||||
{ ARM64_REG_Q13, "q13"},
|
||||
{ ARM64_REG_Q14, "q14"},
|
||||
{ ARM64_REG_Q15, "q15"},
|
||||
{ ARM64_REG_Q16, "q16"},
|
||||
{ ARM64_REG_Q17, "q17"},
|
||||
{ ARM64_REG_Q18, "q18"},
|
||||
{ ARM64_REG_Q19, "q19"},
|
||||
{ ARM64_REG_Q20, "q20"},
|
||||
{ ARM64_REG_Q21, "q21"},
|
||||
{ ARM64_REG_Q22, "q22"},
|
||||
{ ARM64_REG_Q23, "q23"},
|
||||
{ ARM64_REG_Q24, "q24"},
|
||||
{ ARM64_REG_Q25, "q25"},
|
||||
{ ARM64_REG_Q26, "q26"},
|
||||
{ ARM64_REG_Q27, "q27"},
|
||||
{ ARM64_REG_Q28, "q28"},
|
||||
{ ARM64_REG_Q29, "q29"},
|
||||
{ ARM64_REG_Q30, "q30"},
|
||||
{ ARM64_REG_Q31, "q31"},
|
||||
{ ARM64_REG_S0, "s0"},
|
||||
{ ARM64_REG_S1, "s1"},
|
||||
{ ARM64_REG_S2, "s2"},
|
||||
{ ARM64_REG_S3, "s3"},
|
||||
{ ARM64_REG_S4, "s4"},
|
||||
{ ARM64_REG_S5, "s5"},
|
||||
{ ARM64_REG_S6, "s6"},
|
||||
{ ARM64_REG_S7, "s7"},
|
||||
{ ARM64_REG_S8, "s8"},
|
||||
{ ARM64_REG_S9, "s9"},
|
||||
{ ARM64_REG_S10, "s10"},
|
||||
{ ARM64_REG_S11, "s11"},
|
||||
{ ARM64_REG_S12, "s12"},
|
||||
{ ARM64_REG_S13, "s13"},
|
||||
{ ARM64_REG_S14, "s14"},
|
||||
{ ARM64_REG_S15, "s15"},
|
||||
{ ARM64_REG_S16, "s16"},
|
||||
{ ARM64_REG_S17, "s17"},
|
||||
{ ARM64_REG_S18, "s18"},
|
||||
{ ARM64_REG_S19, "s19"},
|
||||
{ ARM64_REG_S20, "s20"},
|
||||
{ ARM64_REG_S21, "s21"},
|
||||
{ ARM64_REG_S22, "s22"},
|
||||
{ ARM64_REG_S23, "s23"},
|
||||
{ ARM64_REG_S24, "s24"},
|
||||
{ ARM64_REG_S25, "s25"},
|
||||
{ ARM64_REG_S26, "s26"},
|
||||
{ ARM64_REG_S27, "s27"},
|
||||
{ ARM64_REG_S28, "s28"},
|
||||
{ ARM64_REG_S29, "s29"},
|
||||
{ ARM64_REG_S30, "s30"},
|
||||
{ ARM64_REG_S31, "s31"},
|
||||
{ ARM64_REG_W0, "w0"},
|
||||
{ ARM64_REG_W1, "w1"},
|
||||
{ ARM64_REG_W2, "w2"},
|
||||
{ ARM64_REG_W3, "w3"},
|
||||
{ ARM64_REG_W4, "w4"},
|
||||
{ ARM64_REG_W5, "w5"},
|
||||
{ ARM64_REG_W6, "w6"},
|
||||
{ ARM64_REG_W7, "w7"},
|
||||
{ ARM64_REG_W8, "w8"},
|
||||
{ ARM64_REG_W9, "w9"},
|
||||
{ ARM64_REG_W10, "w10"},
|
||||
{ ARM64_REG_W11, "w11"},
|
||||
{ ARM64_REG_W12, "w12"},
|
||||
{ ARM64_REG_W13, "w13"},
|
||||
{ ARM64_REG_W14, "w14"},
|
||||
{ ARM64_REG_W15, "w15"},
|
||||
{ ARM64_REG_W16, "w16"},
|
||||
{ ARM64_REG_W17, "w17"},
|
||||
{ ARM64_REG_W18, "w18"},
|
||||
{ ARM64_REG_W19, "w19"},
|
||||
{ ARM64_REG_W20, "w20"},
|
||||
{ ARM64_REG_W21, "w21"},
|
||||
{ ARM64_REG_W22, "w22"},
|
||||
{ ARM64_REG_W23, "w23"},
|
||||
{ ARM64_REG_W24, "w24"},
|
||||
{ ARM64_REG_W25, "w25"},
|
||||
{ ARM64_REG_W26, "w26"},
|
||||
{ ARM64_REG_W27, "w27"},
|
||||
{ ARM64_REG_W28, "w28"},
|
||||
{ ARM64_REG_W29, "w29"},
|
||||
{ ARM64_REG_W30, "w30"},
|
||||
{ ARM64_REG_X0, "x0"},
|
||||
{ ARM64_REG_X1, "x1"},
|
||||
{ ARM64_REG_X2, "x2"},
|
||||
{ ARM64_REG_X3, "x3"},
|
||||
{ ARM64_REG_X4, "x4"},
|
||||
{ ARM64_REG_X5, "x5"},
|
||||
{ ARM64_REG_X6, "x6"},
|
||||
{ ARM64_REG_X7, "x7"},
|
||||
{ ARM64_REG_X8, "x8"},
|
||||
{ ARM64_REG_X9, "x9"},
|
||||
{ ARM64_REG_X10, "x10"},
|
||||
{ ARM64_REG_X11, "x11"},
|
||||
{ ARM64_REG_X12, "x12"},
|
||||
{ ARM64_REG_X13, "x13"},
|
||||
{ ARM64_REG_X14, "x14"},
|
||||
{ ARM64_REG_X15, "x15"},
|
||||
{ ARM64_REG_X16, "x16"},
|
||||
{ ARM64_REG_X17, "x17"},
|
||||
{ ARM64_REG_X18, "x18"},
|
||||
{ ARM64_REG_X19, "x19"},
|
||||
{ ARM64_REG_X20, "x20"},
|
||||
{ ARM64_REG_X21, "x21"},
|
||||
{ ARM64_REG_X22, "x22"},
|
||||
{ ARM64_REG_X23, "x23"},
|
||||
{ ARM64_REG_X24, "x24"},
|
||||
{ ARM64_REG_X25, "x25"},
|
||||
{ ARM64_REG_X26, "x26"},
|
||||
{ ARM64_REG_X27, "x27"},
|
||||
{ ARM64_REG_X28, "x28"},
|
||||
"ffr",
|
||||
"fp",
|
||||
"lr",
|
||||
"nzcv",
|
||||
"sp",
|
||||
"wsp",
|
||||
"wzr",
|
||||
"xzr",
|
||||
|
||||
{ ARM64_REG_V0, "v0"},
|
||||
{ ARM64_REG_V1, "v1"},
|
||||
{ ARM64_REG_V2, "v2"},
|
||||
{ ARM64_REG_V3, "v3"},
|
||||
{ ARM64_REG_V4, "v4"},
|
||||
{ ARM64_REG_V5, "v5"},
|
||||
{ ARM64_REG_V6, "v6"},
|
||||
{ ARM64_REG_V7, "v7"},
|
||||
{ ARM64_REG_V8, "v8"},
|
||||
{ ARM64_REG_V9, "v9"},
|
||||
{ ARM64_REG_V10, "v10"},
|
||||
{ ARM64_REG_V11, "v11"},
|
||||
{ ARM64_REG_V12, "v12"},
|
||||
{ ARM64_REG_V13, "v13"},
|
||||
{ ARM64_REG_V14, "v14"},
|
||||
{ ARM64_REG_V15, "v15"},
|
||||
{ ARM64_REG_V16, "v16"},
|
||||
{ ARM64_REG_V17, "v17"},
|
||||
{ ARM64_REG_V18, "v18"},
|
||||
{ ARM64_REG_V19, "v19"},
|
||||
{ ARM64_REG_V20, "v20"},
|
||||
{ ARM64_REG_V21, "v21"},
|
||||
{ ARM64_REG_V22, "v22"},
|
||||
{ ARM64_REG_V23, "v23"},
|
||||
{ ARM64_REG_V24, "v24"},
|
||||
{ ARM64_REG_V25, "v25"},
|
||||
{ ARM64_REG_V26, "v26"},
|
||||
{ ARM64_REG_V27, "v27"},
|
||||
{ ARM64_REG_V28, "v28"},
|
||||
{ ARM64_REG_V29, "v29"},
|
||||
{ ARM64_REG_V30, "v30"},
|
||||
{ ARM64_REG_V31, "v31"},
|
||||
"b0",
|
||||
"b1",
|
||||
"b2",
|
||||
"b3",
|
||||
"b4",
|
||||
"b5",
|
||||
"b6",
|
||||
"b7",
|
||||
"b8",
|
||||
"b9",
|
||||
"b10",
|
||||
"b11",
|
||||
"b12",
|
||||
"b13",
|
||||
"b14",
|
||||
"b15",
|
||||
"b16",
|
||||
"b17",
|
||||
"b18",
|
||||
"b19",
|
||||
"b20",
|
||||
"b21",
|
||||
"b22",
|
||||
"b23",
|
||||
"b24",
|
||||
"b25",
|
||||
"b26",
|
||||
"b27",
|
||||
"b28",
|
||||
"b29",
|
||||
"b30",
|
||||
"b31",
|
||||
|
||||
"d0",
|
||||
"d1",
|
||||
"d2",
|
||||
"d3",
|
||||
"d4",
|
||||
"d5",
|
||||
"d6",
|
||||
"d7",
|
||||
"d8",
|
||||
"d9",
|
||||
"d10",
|
||||
"d11",
|
||||
"d12",
|
||||
"d13",
|
||||
"d14",
|
||||
"d15",
|
||||
"d16",
|
||||
"d17",
|
||||
"d18",
|
||||
"d19",
|
||||
"d20",
|
||||
"d21",
|
||||
"d22",
|
||||
"d23",
|
||||
"d24",
|
||||
"d25",
|
||||
"d26",
|
||||
"d27",
|
||||
"d28",
|
||||
"d29",
|
||||
"d30",
|
||||
"d31",
|
||||
|
||||
"h0",
|
||||
"h1",
|
||||
"h2",
|
||||
"h3",
|
||||
"h4",
|
||||
"h5",
|
||||
"h6",
|
||||
"h7",
|
||||
"h8",
|
||||
"h9",
|
||||
"h10",
|
||||
"h11",
|
||||
"h12",
|
||||
"h13",
|
||||
"h14",
|
||||
"h15",
|
||||
"h16",
|
||||
"h17",
|
||||
"h18",
|
||||
"h19",
|
||||
"h20",
|
||||
"h21",
|
||||
"h22",
|
||||
"h23",
|
||||
"h24",
|
||||
"h25",
|
||||
"h26",
|
||||
"h27",
|
||||
"h28",
|
||||
"h29",
|
||||
"h30",
|
||||
"h31",
|
||||
|
||||
"p0",
|
||||
"p1",
|
||||
"p2",
|
||||
"p3",
|
||||
"p4",
|
||||
"p5",
|
||||
"p6",
|
||||
"p7",
|
||||
"p8",
|
||||
"p9",
|
||||
"p10",
|
||||
"p11",
|
||||
"p12",
|
||||
"p13",
|
||||
"p14",
|
||||
"p15",
|
||||
|
||||
"q0",
|
||||
"q1",
|
||||
"q2",
|
||||
"q3",
|
||||
"q4",
|
||||
"q5",
|
||||
"q6",
|
||||
"q7",
|
||||
"q8",
|
||||
"q9",
|
||||
"q10",
|
||||
"q11",
|
||||
"q12",
|
||||
"q13",
|
||||
"q14",
|
||||
"q15",
|
||||
"q16",
|
||||
"q17",
|
||||
"q18",
|
||||
"q19",
|
||||
"q20",
|
||||
"q21",
|
||||
"q22",
|
||||
"q23",
|
||||
"q24",
|
||||
"q25",
|
||||
"q26",
|
||||
"q27",
|
||||
"q28",
|
||||
"q29",
|
||||
"q30",
|
||||
"q31",
|
||||
"s0",
|
||||
"s1",
|
||||
"s2",
|
||||
"s3",
|
||||
"s4",
|
||||
"s5",
|
||||
"s6",
|
||||
"s7",
|
||||
"s8",
|
||||
"s9",
|
||||
"s10",
|
||||
"s11",
|
||||
"s12",
|
||||
"s13",
|
||||
"s14",
|
||||
"s15",
|
||||
"s16",
|
||||
"s17",
|
||||
"s18",
|
||||
"s19",
|
||||
"s20",
|
||||
"s21",
|
||||
"s22",
|
||||
"s23",
|
||||
"s24",
|
||||
"s25",
|
||||
"s26",
|
||||
"s27",
|
||||
"s28",
|
||||
"s29",
|
||||
"s30",
|
||||
"s31",
|
||||
|
||||
"w0",
|
||||
"w1",
|
||||
"w2",
|
||||
"w3",
|
||||
"w4",
|
||||
"w5",
|
||||
"w6",
|
||||
"w7",
|
||||
"w8",
|
||||
"w9",
|
||||
"w10",
|
||||
"w11",
|
||||
"w12",
|
||||
"w13",
|
||||
"w14",
|
||||
"w15",
|
||||
"w16",
|
||||
"w17",
|
||||
"w18",
|
||||
"w19",
|
||||
"w20",
|
||||
"w21",
|
||||
"w22",
|
||||
"w23",
|
||||
"w24",
|
||||
"w25",
|
||||
"w26",
|
||||
"w27",
|
||||
"w28",
|
||||
"w29",
|
||||
"w30",
|
||||
|
||||
"x0",
|
||||
"x1",
|
||||
"x2",
|
||||
"x3",
|
||||
"x4",
|
||||
"x5",
|
||||
"x6",
|
||||
"x7",
|
||||
"x8",
|
||||
"x9",
|
||||
"x10",
|
||||
"x11",
|
||||
"x12",
|
||||
"x13",
|
||||
"x14",
|
||||
"x15",
|
||||
"x16",
|
||||
"x17",
|
||||
"x18",
|
||||
"x19",
|
||||
"x20",
|
||||
"x21",
|
||||
"x22",
|
||||
"x23",
|
||||
"x24",
|
||||
"x25",
|
||||
"x26",
|
||||
"x27",
|
||||
"x28",
|
||||
|
||||
"z0",
|
||||
"z1",
|
||||
"z2",
|
||||
"z3",
|
||||
"z4",
|
||||
"z5",
|
||||
"z6",
|
||||
"z7",
|
||||
"z8",
|
||||
"z9",
|
||||
"z10",
|
||||
"z11",
|
||||
"z12",
|
||||
"z13",
|
||||
"z14",
|
||||
"z15",
|
||||
"z16",
|
||||
"z17",
|
||||
"z18",
|
||||
"z19",
|
||||
"z20",
|
||||
"z21",
|
||||
"z22",
|
||||
"z23",
|
||||
"z24",
|
||||
"z25",
|
||||
"z26",
|
||||
"z27",
|
||||
"z28",
|
||||
"z29",
|
||||
"z30",
|
||||
"z31",
|
||||
|
||||
"v0",
|
||||
"v1",
|
||||
"v2",
|
||||
"v3",
|
||||
"v4",
|
||||
"v5",
|
||||
"v6",
|
||||
"v7",
|
||||
"v8",
|
||||
"v9",
|
||||
"v10",
|
||||
"v11",
|
||||
"v12",
|
||||
"v13",
|
||||
"v14",
|
||||
"v15",
|
||||
"v16",
|
||||
"v17",
|
||||
"v18",
|
||||
"v19",
|
||||
"v20",
|
||||
"v21",
|
||||
"v22",
|
||||
"v23",
|
||||
"v24",
|
||||
"v25",
|
||||
"v26",
|
||||
"v27",
|
||||
"v28",
|
||||
"v29",
|
||||
"v30",
|
||||
"v31",
|
||||
};
|
||||
#endif
|
||||
|
||||
@ -286,7 +344,7 @@ const char *AArch64_reg_name(csh handle, unsigned int reg)
|
||||
if (reg >= ARR_SIZE(reg_name_maps))
|
||||
return NULL;
|
||||
|
||||
return reg_name_maps[reg].name;
|
||||
return reg_name_maps[reg];
|
||||
#else
|
||||
return NULL;
|
||||
#endif
|
||||
@ -331,82 +389,20 @@ void AArch64_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
|
||||
}
|
||||
}
|
||||
|
||||
#ifndef CAPSTONE_DIET
|
||||
static const name_map insn_name_maps[] = {
|
||||
{ ARM64_INS_INVALID, NULL },
|
||||
|
||||
#include "AArch64GenInsnNameMaps.inc"
|
||||
static const char *insn_name_maps[] = {
|
||||
NULL, // ARM64_INS_INVALID
|
||||
#include "AArch64MappingInsnName.inc"
|
||||
};
|
||||
|
||||
// map *S & alias instructions back to original id
|
||||
static const name_map alias_insn_name_maps[] = {
|
||||
{ ARM64_INS_ADC, "adcs" },
|
||||
{ ARM64_INS_AND, "ands" },
|
||||
{ ARM64_INS_ADD, "adds" },
|
||||
{ ARM64_INS_BIC, "bics" },
|
||||
{ ARM64_INS_SBC, "sbcs" },
|
||||
{ ARM64_INS_SUB, "subs" },
|
||||
|
||||
// alias insn
|
||||
{ ARM64_INS_MNEG, "mneg" },
|
||||
{ ARM64_INS_UMNEGL, "umnegl" },
|
||||
{ ARM64_INS_SMNEGL, "smnegl" },
|
||||
{ ARM64_INS_NOP, "nop" },
|
||||
{ ARM64_INS_YIELD, "yield" },
|
||||
{ ARM64_INS_WFE, "wfe" },
|
||||
{ ARM64_INS_WFI, "wfi" },
|
||||
{ ARM64_INS_SEV, "sev" },
|
||||
{ ARM64_INS_SEVL, "sevl" },
|
||||
{ ARM64_INS_NGC, "ngc" },
|
||||
{ ARM64_INS_NGCS, "ngcs" },
|
||||
{ ARM64_INS_NEGS, "negs" },
|
||||
|
||||
{ ARM64_INS_SBFIZ, "sbfiz" },
|
||||
{ ARM64_INS_UBFIZ, "ubfiz" },
|
||||
{ ARM64_INS_SBFX, "sbfx" },
|
||||
{ ARM64_INS_UBFX, "ubfx" },
|
||||
{ ARM64_INS_BFI, "bfi" },
|
||||
{ ARM64_INS_BFXIL, "bfxil" },
|
||||
{ ARM64_INS_CMN, "cmn" },
|
||||
{ ARM64_INS_MVN, "mvn" },
|
||||
{ ARM64_INS_TST, "tst" },
|
||||
{ ARM64_INS_CSET, "cset" },
|
||||
{ ARM64_INS_CINC, "cinc" },
|
||||
{ ARM64_INS_CSETM, "csetm" },
|
||||
{ ARM64_INS_CINV, "cinv" },
|
||||
{ ARM64_INS_CNEG, "cneg" },
|
||||
{ ARM64_INS_SXTB, "sxtb" },
|
||||
{ ARM64_INS_SXTH, "sxth" },
|
||||
{ ARM64_INS_SXTW, "sxtw" },
|
||||
{ ARM64_INS_CMP, "cmp" },
|
||||
{ ARM64_INS_UXTB, "uxtb" },
|
||||
{ ARM64_INS_UXTH, "uxth" },
|
||||
{ ARM64_INS_UXTW, "uxtw" },
|
||||
|
||||
{ ARM64_INS_IC, "ic" },
|
||||
{ ARM64_INS_DC, "dc" },
|
||||
{ ARM64_INS_AT, "at" },
|
||||
{ ARM64_INS_TLBI, "tlbi" },
|
||||
};
|
||||
#endif
|
||||
|
||||
const char *AArch64_insn_name(csh handle, unsigned int id)
|
||||
{
|
||||
#ifndef CAPSTONE_DIET
|
||||
unsigned int i;
|
||||
|
||||
if (id >= ARM64_INS_ENDING)
|
||||
return NULL;
|
||||
|
||||
if (id < ARR_SIZE(insn_name_maps))
|
||||
return insn_name_maps[id];
|
||||
|
||||
// then find alias insn
|
||||
for (i = 0; i < ARR_SIZE(alias_insn_name_maps); i++) {
|
||||
if (alias_insn_name_maps[i].id == id)
|
||||
return alias_insn_name_maps[i].name;
|
||||
}
|
||||
|
||||
// not found
|
||||
return NULL;
|
||||
#else
|
||||
@ -431,23 +427,19 @@ static const name_map group_name_maps[] = {
|
||||
{ ARM64_GRP_NEON, "neon" },
|
||||
{ ARM64_GRP_CRC, "crc" },
|
||||
|
||||
// new
|
||||
{ ARM64_GRP_HASAES, "hasaes" },
|
||||
{ ARM64_GRP_HASCRC, "hascrc" },
|
||||
{ ARM64_GRP_HASDOTPROD, "hasdotprod" },
|
||||
{ ARM64_GRP_HASFPARMV8, "hasfparmv8" },
|
||||
{ ARM64_GRP_HASFULLFP16, "hasfullfp16" },
|
||||
{ ARM64_GRP_HASLSE, "haslse" },
|
||||
{ ARM64_GRP_HASNEON, "hasneon" },
|
||||
{ ARM64_GRP_HASRCPC, "hasrcpc" },
|
||||
{ ARM64_GRP_HASRDM, "hasrdm" },
|
||||
{ ARM64_GRP_HASSHA2, "hassha2" },
|
||||
{ ARM64_GRP_HASSHA3, "hassha3" },
|
||||
{ ARM64_GRP_HASSM4, "hassm4" },
|
||||
{ ARM64_GRP_HASSVE, "hassve" },
|
||||
{ ARM64_GRP_HASV8_1A, "hasv8_1a" },
|
||||
{ ARM64_GRP_HASV8_3A, "hasv8_3a" },
|
||||
{ ARM64_GRP_HASV8_4A, "hasv8_4a" },
|
||||
{ ARM64_GRP_AES, "aes" },
|
||||
{ ARM64_GRP_DOTPROD, "dotprod" },
|
||||
{ ARM64_GRP_FULLFP16, "fullfp16" },
|
||||
{ ARM64_GRP_LSE, "lse" },
|
||||
{ ARM64_GRP_RCPC, "rcpc" },
|
||||
{ ARM64_GRP_RDM, "rdm" },
|
||||
{ ARM64_GRP_SHA2, "sha2" },
|
||||
{ ARM64_GRP_SHA3, "sha3" },
|
||||
{ ARM64_GRP_SM4, "sm4" },
|
||||
{ ARM64_GRP_SVE, "sve" },
|
||||
{ ARM64_GRP_V8_1A, "v8_1a" },
|
||||
{ ARM64_GRP_V8_3A, "v8_3a" },
|
||||
{ ARM64_GRP_V8_4A, "v8_4a" },
|
||||
};
|
||||
#endif
|
||||
|
||||
@ -461,108 +453,28 @@ const char *AArch64_group_name(csh handle, unsigned int id)
|
||||
}
|
||||
|
||||
// map instruction name to public instruction ID
|
||||
arm64_reg AArch64_map_insn(const char *name)
|
||||
arm64_insn AArch64_map_insn(const char *name)
|
||||
{
|
||||
// NOTE: skip first NULL name in insn_name_maps
|
||||
int i = name2id(&insn_name_maps[1], ARR_SIZE(insn_name_maps) - 1, name);
|
||||
unsigned int i;
|
||||
|
||||
if (i == -1)
|
||||
// try again with 'special' insn that is not available in insn_name_maps
|
||||
i = name2id(alias_insn_name_maps, ARR_SIZE(alias_insn_name_maps), name);
|
||||
for(i = 1; i < ARR_SIZE(insn_name_maps); i++) {
|
||||
if (!strcmp(name, insn_name_maps[i]))
|
||||
return i;
|
||||
}
|
||||
|
||||
return (i != -1)? i : ARM64_REG_INVALID;
|
||||
// not found
|
||||
return ARM64_INS_INVALID;
|
||||
}
|
||||
|
||||
// map internal raw vregister to 'public' register
|
||||
arm64_reg AArch64_map_vregister(unsigned int r)
|
||||
{
|
||||
// for some reasons different Arm64 can map different register number to
|
||||
// the same register. this function handles the issue for exposing Mips
|
||||
// operands by mapping internal registers to 'public' register.
|
||||
static const unsigned int map[] = { 0,
|
||||
0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, ARM64_REG_V0,
|
||||
ARM64_REG_V1, ARM64_REG_V2, ARM64_REG_V3, ARM64_REG_V4, ARM64_REG_V5,
|
||||
ARM64_REG_V6, ARM64_REG_V7, ARM64_REG_V8, ARM64_REG_V9, ARM64_REG_V10,
|
||||
ARM64_REG_V11, ARM64_REG_V12, ARM64_REG_V13, ARM64_REG_V14, ARM64_REG_V15,
|
||||
ARM64_REG_V16, ARM64_REG_V17, ARM64_REG_V18, ARM64_REG_V19, ARM64_REG_V20,
|
||||
ARM64_REG_V21, ARM64_REG_V22, ARM64_REG_V23, ARM64_REG_V24, ARM64_REG_V25,
|
||||
ARM64_REG_V26, ARM64_REG_V27, ARM64_REG_V28, ARM64_REG_V29, ARM64_REG_V30,
|
||||
ARM64_REG_V31, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, ARM64_REG_V0, ARM64_REG_V1,
|
||||
ARM64_REG_V2, ARM64_REG_V3, ARM64_REG_V4, ARM64_REG_V5, ARM64_REG_V6,
|
||||
ARM64_REG_V7, ARM64_REG_V8, ARM64_REG_V9, ARM64_REG_V10, ARM64_REG_V11,
|
||||
ARM64_REG_V12, ARM64_REG_V13, ARM64_REG_V14, ARM64_REG_V15, ARM64_REG_V16,
|
||||
ARM64_REG_V17, ARM64_REG_V18, ARM64_REG_V19, ARM64_REG_V20, ARM64_REG_V21,
|
||||
ARM64_REG_V22, ARM64_REG_V23, ARM64_REG_V24, ARM64_REG_V25, ARM64_REG_V26,
|
||||
ARM64_REG_V27, ARM64_REG_V28, ARM64_REG_V29, ARM64_REG_V30, ARM64_REG_V31,
|
||||
0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0,
|
||||
0, 0, ARM64_REG_V0, ARM64_REG_V1, ARM64_REG_V2,
|
||||
ARM64_REG_V3, ARM64_REG_V4, ARM64_REG_V5, ARM64_REG_V6, ARM64_REG_V7,
|
||||
ARM64_REG_V8, ARM64_REG_V9, ARM64_REG_V10, ARM64_REG_V11, ARM64_REG_V12,
|
||||
ARM64_REG_V13, ARM64_REG_V14, ARM64_REG_V15, ARM64_REG_V16, ARM64_REG_V17,
|
||||
ARM64_REG_V18, ARM64_REG_V19, ARM64_REG_V20, ARM64_REG_V21, ARM64_REG_V22,
|
||||
ARM64_REG_V23, ARM64_REG_V24, ARM64_REG_V25, ARM64_REG_V26, ARM64_REG_V27,
|
||||
ARM64_REG_V28, ARM64_REG_V29, ARM64_REG_V30, ARM64_REG_V31, ARM64_REG_V0,
|
||||
ARM64_REG_V1, ARM64_REG_V2, ARM64_REG_V3, ARM64_REG_V4, ARM64_REG_V5,
|
||||
ARM64_REG_V6, ARM64_REG_V7, ARM64_REG_V8, ARM64_REG_V9, ARM64_REG_V10,
|
||||
ARM64_REG_V11, ARM64_REG_V12, ARM64_REG_V13, ARM64_REG_V14, ARM64_REG_V15,
|
||||
ARM64_REG_V16, ARM64_REG_V17, ARM64_REG_V18, ARM64_REG_V19, ARM64_REG_V20,
|
||||
ARM64_REG_V21, ARM64_REG_V22, ARM64_REG_V23, ARM64_REG_V24, ARM64_REG_V25,
|
||||
ARM64_REG_V26, ARM64_REG_V27, ARM64_REG_V28, ARM64_REG_V29, ARM64_REG_V30,
|
||||
ARM64_REG_V31, ARM64_REG_V0, ARM64_REG_V1, ARM64_REG_V2, ARM64_REG_V3,
|
||||
ARM64_REG_V4, ARM64_REG_V5, ARM64_REG_V6, ARM64_REG_V7, ARM64_REG_V8,
|
||||
ARM64_REG_V9, ARM64_REG_V10, ARM64_REG_V11, ARM64_REG_V12, ARM64_REG_V13,
|
||||
ARM64_REG_V14, ARM64_REG_V15, ARM64_REG_V16, ARM64_REG_V17, ARM64_REG_V18,
|
||||
ARM64_REG_V19, ARM64_REG_V20, ARM64_REG_V21, ARM64_REG_V22, ARM64_REG_V23,
|
||||
ARM64_REG_V24, ARM64_REG_V25, ARM64_REG_V26, ARM64_REG_V27, ARM64_REG_V28,
|
||||
ARM64_REG_V29, ARM64_REG_V30, ARM64_REG_V31, ARM64_REG_V0, ARM64_REG_V1,
|
||||
ARM64_REG_V2, ARM64_REG_V3, ARM64_REG_V4, ARM64_REG_V5, ARM64_REG_V6,
|
||||
ARM64_REG_V7, ARM64_REG_V8, ARM64_REG_V9, ARM64_REG_V10, ARM64_REG_V11,
|
||||
ARM64_REG_V12, ARM64_REG_V13, ARM64_REG_V14, ARM64_REG_V15, ARM64_REG_V16,
|
||||
ARM64_REG_V17, ARM64_REG_V18, ARM64_REG_V19, ARM64_REG_V20, ARM64_REG_V21,
|
||||
ARM64_REG_V22, ARM64_REG_V23, ARM64_REG_V24, ARM64_REG_V25, ARM64_REG_V26,
|
||||
ARM64_REG_V27, ARM64_REG_V28, ARM64_REG_V29, ARM64_REG_V30, ARM64_REG_V31,
|
||||
ARM64_REG_V0, ARM64_REG_V1, ARM64_REG_V2, ARM64_REG_V3, ARM64_REG_V4,
|
||||
ARM64_REG_V5, ARM64_REG_V6, ARM64_REG_V7, ARM64_REG_V8, ARM64_REG_V9,
|
||||
ARM64_REG_V10, ARM64_REG_V11, ARM64_REG_V12, ARM64_REG_V13, ARM64_REG_V14,
|
||||
ARM64_REG_V15, ARM64_REG_V16, ARM64_REG_V17, ARM64_REG_V18, ARM64_REG_V19,
|
||||
ARM64_REG_V20, ARM64_REG_V21, ARM64_REG_V22, ARM64_REG_V23, ARM64_REG_V24,
|
||||
ARM64_REG_V25, ARM64_REG_V26, ARM64_REG_V27, ARM64_REG_V28, ARM64_REG_V29,
|
||||
ARM64_REG_V30, ARM64_REG_V31, ARM64_REG_V0, ARM64_REG_V1, ARM64_REG_V2,
|
||||
ARM64_REG_V3, ARM64_REG_V4, ARM64_REG_V5, ARM64_REG_V6, ARM64_REG_V7,
|
||||
ARM64_REG_V8, ARM64_REG_V9, ARM64_REG_V10, ARM64_REG_V11, ARM64_REG_V12,
|
||||
ARM64_REG_V13, ARM64_REG_V14, ARM64_REG_V15, ARM64_REG_V16, ARM64_REG_V17,
|
||||
ARM64_REG_V18, ARM64_REG_V19, ARM64_REG_V20, ARM64_REG_V21, ARM64_REG_V22,
|
||||
ARM64_REG_V23, ARM64_REG_V24, ARM64_REG_V25, ARM64_REG_V26, ARM64_REG_V27,
|
||||
ARM64_REG_V28, ARM64_REG_V29, ARM64_REG_V30, ARM64_REG_V31, };
|
||||
static const unsigned short RegAsmOffsetvreg[] = {
|
||||
#include "AArch64GenRegisterV.inc"
|
||||
};
|
||||
|
||||
if (r < ARR_SIZE(map))
|
||||
return map[r];
|
||||
if (r < ARR_SIZE(RegAsmOffsetvreg))
|
||||
return RegAsmOffsetvreg[r - 1];
|
||||
|
||||
// cannot find this register
|
||||
return 0;
|
||||
@ -575,13 +487,6 @@ void arm64_op_addVectorArrSpecifier(MCInst * MI, int sp)
|
||||
}
|
||||
}
|
||||
|
||||
void arm64_op_addVectorElementSizeSpecifier(MCInst * MI, int sp)
|
||||
{
|
||||
if (MI->csh->detail) {
|
||||
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].vess = sp;
|
||||
}
|
||||
}
|
||||
|
||||
void arm64_op_addFP(MCInst *MI, float fp)
|
||||
{
|
||||
if (MI->csh->detail) {
|
||||
@ -681,4 +586,4 @@ void AArch64_reg_access(const cs_insn *insn,
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
||||
@ -6,6 +6,8 @@
|
||||
|
||||
#include "capstone/capstone.h"
|
||||
|
||||
#define ARR_SIZE(a) (sizeof(a)/sizeof(a[0]))
|
||||
|
||||
// return name of regiser in friendly string
|
||||
const char *AArch64_reg_name(csh handle, unsigned int reg);
|
||||
|
||||
@ -17,7 +19,7 @@ const char *AArch64_insn_name(csh handle, unsigned int id);
|
||||
const char *AArch64_group_name(csh handle, unsigned int id);
|
||||
|
||||
// map instruction name to public instruction ID
|
||||
arm64_reg AArch64_map_insn(const char *name);
|
||||
arm64_insn AArch64_map_insn(const char *name);
|
||||
|
||||
// map internal vregister to public register
|
||||
arm64_reg AArch64_map_vregister(unsigned int r);
|
||||
@ -26,8 +28,6 @@ void arm64_op_addReg(MCInst *MI, int reg);
|
||||
|
||||
void arm64_op_addVectorArrSpecifier(MCInst * MI, int sp);
|
||||
|
||||
void arm64_op_addVectorElementSizeSpecifier(MCInst * MI, int sp);
|
||||
|
||||
void arm64_op_addFP(MCInst *MI, float fp);
|
||||
|
||||
void arm64_op_addImm(MCInst *MI, int64_t imm);
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
943
arch/AArch64/AArch64MappingInsnName.inc
Normal file
943
arch/AArch64/AArch64MappingInsnName.inc
Normal file
@ -0,0 +1,943 @@
|
||||
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
|
||||
/* This is auto-gen data for Capstone disassembly engine (www.capstone-engine.org) */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
|
||||
|
||||
"abs", // ARM64_INS_ABS,
|
||||
"adc", // ARM64_INS_ADC,
|
||||
"adcs", // ARM64_INS_ADCS,
|
||||
"add", // ARM64_INS_ADD,
|
||||
"addhn", // ARM64_INS_ADDHN,
|
||||
"addhn2", // ARM64_INS_ADDHN2,
|
||||
"addp", // ARM64_INS_ADDP,
|
||||
"addpl", // ARM64_INS_ADDPL,
|
||||
"adds", // ARM64_INS_ADDS,
|
||||
"addv", // ARM64_INS_ADDV,
|
||||
"addvl", // ARM64_INS_ADDVL,
|
||||
"adr", // ARM64_INS_ADR,
|
||||
"adrp", // ARM64_INS_ADRP,
|
||||
"aesd", // ARM64_INS_AESD,
|
||||
"aese", // ARM64_INS_AESE,
|
||||
"aesimc", // ARM64_INS_AESIMC,
|
||||
"aesmc", // ARM64_INS_AESMC,
|
||||
"and", // ARM64_INS_AND,
|
||||
"ands", // ARM64_INS_ANDS,
|
||||
"andv", // ARM64_INS_ANDV,
|
||||
"asr", // ARM64_INS_ASR,
|
||||
"asrd", // ARM64_INS_ASRD,
|
||||
"asrr", // ARM64_INS_ASRR,
|
||||
"asrv", // ARM64_INS_ASRV,
|
||||
"autda", // ARM64_INS_AUTDA,
|
||||
"autdb", // ARM64_INS_AUTDB,
|
||||
"autdza", // ARM64_INS_AUTDZA,
|
||||
"autdzb", // ARM64_INS_AUTDZB,
|
||||
"autia", // ARM64_INS_AUTIA,
|
||||
"autia1716", // ARM64_INS_AUTIA1716,
|
||||
"autiasp", // ARM64_INS_AUTIASP,
|
||||
"autiaz", // ARM64_INS_AUTIAZ,
|
||||
"autib", // ARM64_INS_AUTIB,
|
||||
"autib1716", // ARM64_INS_AUTIB1716,
|
||||
"autibsp", // ARM64_INS_AUTIBSP,
|
||||
"autibz", // ARM64_INS_AUTIBZ,
|
||||
"autiza", // ARM64_INS_AUTIZA,
|
||||
"autizb", // ARM64_INS_AUTIZB,
|
||||
"b", // ARM64_INS_B,
|
||||
"bcax", // ARM64_INS_BCAX,
|
||||
"bfm", // ARM64_INS_BFM,
|
||||
"bic", // ARM64_INS_BIC,
|
||||
"bics", // ARM64_INS_BICS,
|
||||
"bif", // ARM64_INS_BIF,
|
||||
"bit", // ARM64_INS_BIT,
|
||||
"bl", // ARM64_INS_BL,
|
||||
"blr", // ARM64_INS_BLR,
|
||||
"blraa", // ARM64_INS_BLRAA,
|
||||
"blraaz", // ARM64_INS_BLRAAZ,
|
||||
"blrab", // ARM64_INS_BLRAB,
|
||||
"blrabz", // ARM64_INS_BLRABZ,
|
||||
"br", // ARM64_INS_BR,
|
||||
"braa", // ARM64_INS_BRAA,
|
||||
"braaz", // ARM64_INS_BRAAZ,
|
||||
"brab", // ARM64_INS_BRAB,
|
||||
"brabz", // ARM64_INS_BRABZ,
|
||||
"brk", // ARM64_INS_BRK,
|
||||
"brka", // ARM64_INS_BRKA,
|
||||
"brkas", // ARM64_INS_BRKAS,
|
||||
"brkb", // ARM64_INS_BRKB,
|
||||
"brkbs", // ARM64_INS_BRKBS,
|
||||
"brkn", // ARM64_INS_BRKN,
|
||||
"brkns", // ARM64_INS_BRKNS,
|
||||
"brkpa", // ARM64_INS_BRKPA,
|
||||
"brkpas", // ARM64_INS_BRKPAS,
|
||||
"brkpb", // ARM64_INS_BRKPB,
|
||||
"brkpbs", // ARM64_INS_BRKPBS,
|
||||
"bsl", // ARM64_INS_BSL,
|
||||
"cas", // ARM64_INS_CAS,
|
||||
"casa", // ARM64_INS_CASA,
|
||||
"casab", // ARM64_INS_CASAB,
|
||||
"casah", // ARM64_INS_CASAH,
|
||||
"casal", // ARM64_INS_CASAL,
|
||||
"casalb", // ARM64_INS_CASALB,
|
||||
"casalh", // ARM64_INS_CASALH,
|
||||
"casb", // ARM64_INS_CASB,
|
||||
"cash", // ARM64_INS_CASH,
|
||||
"casl", // ARM64_INS_CASL,
|
||||
"caslb", // ARM64_INS_CASLB,
|
||||
"caslh", // ARM64_INS_CASLH,
|
||||
"casp", // ARM64_INS_CASP,
|
||||
"caspa", // ARM64_INS_CASPA,
|
||||
"caspal", // ARM64_INS_CASPAL,
|
||||
"caspl", // ARM64_INS_CASPL,
|
||||
"cbnz", // ARM64_INS_CBNZ,
|
||||
"cbz", // ARM64_INS_CBZ,
|
||||
"ccmn", // ARM64_INS_CCMN,
|
||||
"ccmp", // ARM64_INS_CCMP,
|
||||
"cfinv", // ARM64_INS_CFINV,
|
||||
"cinc", // ARM64_INS_CINC,
|
||||
"cinv", // ARM64_INS_CINV,
|
||||
"clasta", // ARM64_INS_CLASTA,
|
||||
"clastb", // ARM64_INS_CLASTB,
|
||||
"clrex", // ARM64_INS_CLREX,
|
||||
"cls", // ARM64_INS_CLS,
|
||||
"clz", // ARM64_INS_CLZ,
|
||||
"cmeq", // ARM64_INS_CMEQ,
|
||||
"cmge", // ARM64_INS_CMGE,
|
||||
"cmgt", // ARM64_INS_CMGT,
|
||||
"cmhi", // ARM64_INS_CMHI,
|
||||
"cmhs", // ARM64_INS_CMHS,
|
||||
"cmle", // ARM64_INS_CMLE,
|
||||
"cmlo", // ARM64_INS_CMLO,
|
||||
"cmls", // ARM64_INS_CMLS,
|
||||
"cmlt", // ARM64_INS_CMLT,
|
||||
"cmn", // ARM64_INS_CMN,
|
||||
"cmp", // ARM64_INS_CMP,
|
||||
"cmpeq", // ARM64_INS_CMPEQ,
|
||||
"cmpge", // ARM64_INS_CMPGE,
|
||||
"cmpgt", // ARM64_INS_CMPGT,
|
||||
"cmphi", // ARM64_INS_CMPHI,
|
||||
"cmphs", // ARM64_INS_CMPHS,
|
||||
"cmple", // ARM64_INS_CMPLE,
|
||||
"cmplo", // ARM64_INS_CMPLO,
|
||||
"cmpls", // ARM64_INS_CMPLS,
|
||||
"cmplt", // ARM64_INS_CMPLT,
|
||||
"cmpne", // ARM64_INS_CMPNE,
|
||||
"cmtst", // ARM64_INS_CMTST,
|
||||
"cneg", // ARM64_INS_CNEG,
|
||||
"cnot", // ARM64_INS_CNOT,
|
||||
"cnt", // ARM64_INS_CNT,
|
||||
"cntb", // ARM64_INS_CNTB,
|
||||
"cntd", // ARM64_INS_CNTD,
|
||||
"cnth", // ARM64_INS_CNTH,
|
||||
"cntp", // ARM64_INS_CNTP,
|
||||
"cntw", // ARM64_INS_CNTW,
|
||||
"compact", // ARM64_INS_COMPACT,
|
||||
"cpy", // ARM64_INS_CPY,
|
||||
"crc32b", // ARM64_INS_CRC32B,
|
||||
"crc32cb", // ARM64_INS_CRC32CB,
|
||||
"crc32ch", // ARM64_INS_CRC32CH,
|
||||
"crc32cw", // ARM64_INS_CRC32CW,
|
||||
"crc32cx", // ARM64_INS_CRC32CX,
|
||||
"crc32h", // ARM64_INS_CRC32H,
|
||||
"crc32w", // ARM64_INS_CRC32W,
|
||||
"crc32x", // ARM64_INS_CRC32X,
|
||||
"csdb", // ARM64_INS_CSDB,
|
||||
"csel", // ARM64_INS_CSEL,
|
||||
"cset", // ARM64_INS_CSET,
|
||||
"csetm", // ARM64_INS_CSETM,
|
||||
"csinc", // ARM64_INS_CSINC,
|
||||
"csinv", // ARM64_INS_CSINV,
|
||||
"csneg", // ARM64_INS_CSNEG,
|
||||
"ctermeq", // ARM64_INS_CTERMEQ,
|
||||
"ctermne", // ARM64_INS_CTERMNE,
|
||||
"dcps1", // ARM64_INS_DCPS1,
|
||||
"dcps2", // ARM64_INS_DCPS2,
|
||||
"dcps3", // ARM64_INS_DCPS3,
|
||||
"decb", // ARM64_INS_DECB,
|
||||
"decd", // ARM64_INS_DECD,
|
||||
"dech", // ARM64_INS_DECH,
|
||||
"decp", // ARM64_INS_DECP,
|
||||
"decw", // ARM64_INS_DECW,
|
||||
"dmb", // ARM64_INS_DMB,
|
||||
"drps", // ARM64_INS_DRPS,
|
||||
"dsb", // ARM64_INS_DSB,
|
||||
"dup", // ARM64_INS_DUP,
|
||||
"dupm", // ARM64_INS_DUPM,
|
||||
"eon", // ARM64_INS_EON,
|
||||
"eor", // ARM64_INS_EOR,
|
||||
"eor3", // ARM64_INS_EOR3,
|
||||
"eors", // ARM64_INS_EORS,
|
||||
"eorv", // ARM64_INS_EORV,
|
||||
"eret", // ARM64_INS_ERET,
|
||||
"eretaa", // ARM64_INS_ERETAA,
|
||||
"eretab", // ARM64_INS_ERETAB,
|
||||
"esb", // ARM64_INS_ESB,
|
||||
"ext", // ARM64_INS_EXT,
|
||||
"extr", // ARM64_INS_EXTR,
|
||||
"fabd", // ARM64_INS_FABD,
|
||||
"fabs", // ARM64_INS_FABS,
|
||||
"facge", // ARM64_INS_FACGE,
|
||||
"facgt", // ARM64_INS_FACGT,
|
||||
"facle", // ARM64_INS_FACLE,
|
||||
"faclt", // ARM64_INS_FACLT,
|
||||
"fadd", // ARM64_INS_FADD,
|
||||
"fadda", // ARM64_INS_FADDA,
|
||||
"faddp", // ARM64_INS_FADDP,
|
||||
"faddv", // ARM64_INS_FADDV,
|
||||
"fcadd", // ARM64_INS_FCADD,
|
||||
"fccmp", // ARM64_INS_FCCMP,
|
||||
"fccmpe", // ARM64_INS_FCCMPE,
|
||||
"fcmeq", // ARM64_INS_FCMEQ,
|
||||
"fcmge", // ARM64_INS_FCMGE,
|
||||
"fcmgt", // ARM64_INS_FCMGT,
|
||||
"fcmla", // ARM64_INS_FCMLA,
|
||||
"fcmle", // ARM64_INS_FCMLE,
|
||||
"fcmlt", // ARM64_INS_FCMLT,
|
||||
"fcmne", // ARM64_INS_FCMNE,
|
||||
"fcmp", // ARM64_INS_FCMP,
|
||||
"fcmpe", // ARM64_INS_FCMPE,
|
||||
"fcmuo", // ARM64_INS_FCMUO,
|
||||
"fcpy", // ARM64_INS_FCPY,
|
||||
"fcsel", // ARM64_INS_FCSEL,
|
||||
"fcvt", // ARM64_INS_FCVT,
|
||||
"fcvtas", // ARM64_INS_FCVTAS,
|
||||
"fcvtau", // ARM64_INS_FCVTAU,
|
||||
"fcvtl", // ARM64_INS_FCVTL,
|
||||
"fcvtl2", // ARM64_INS_FCVTL2,
|
||||
"fcvtms", // ARM64_INS_FCVTMS,
|
||||
"fcvtmu", // ARM64_INS_FCVTMU,
|
||||
"fcvtn", // ARM64_INS_FCVTN,
|
||||
"fcvtn2", // ARM64_INS_FCVTN2,
|
||||
"fcvtns", // ARM64_INS_FCVTNS,
|
||||
"fcvtnu", // ARM64_INS_FCVTNU,
|
||||
"fcvtps", // ARM64_INS_FCVTPS,
|
||||
"fcvtpu", // ARM64_INS_FCVTPU,
|
||||
"fcvtxn", // ARM64_INS_FCVTXN,
|
||||
"fcvtxn2", // ARM64_INS_FCVTXN2,
|
||||
"fcvtzs", // ARM64_INS_FCVTZS,
|
||||
"fcvtzu", // ARM64_INS_FCVTZU,
|
||||
"fdiv", // ARM64_INS_FDIV,
|
||||
"fdivr", // ARM64_INS_FDIVR,
|
||||
"fdup", // ARM64_INS_FDUP,
|
||||
"fexpa", // ARM64_INS_FEXPA,
|
||||
"fjcvtzs", // ARM64_INS_FJCVTZS,
|
||||
"fmad", // ARM64_INS_FMAD,
|
||||
"fmadd", // ARM64_INS_FMADD,
|
||||
"fmax", // ARM64_INS_FMAX,
|
||||
"fmaxnm", // ARM64_INS_FMAXNM,
|
||||
"fmaxnmp", // ARM64_INS_FMAXNMP,
|
||||
"fmaxnmv", // ARM64_INS_FMAXNMV,
|
||||
"fmaxp", // ARM64_INS_FMAXP,
|
||||
"fmaxv", // ARM64_INS_FMAXV,
|
||||
"fmin", // ARM64_INS_FMIN,
|
||||
"fminnm", // ARM64_INS_FMINNM,
|
||||
"fminnmp", // ARM64_INS_FMINNMP,
|
||||
"fminnmv", // ARM64_INS_FMINNMV,
|
||||
"fminp", // ARM64_INS_FMINP,
|
||||
"fminv", // ARM64_INS_FMINV,
|
||||
"fmla", // ARM64_INS_FMLA,
|
||||
"fmls", // ARM64_INS_FMLS,
|
||||
"fmov", // ARM64_INS_FMOV,
|
||||
"fmsb", // ARM64_INS_FMSB,
|
||||
"fmsub", // ARM64_INS_FMSUB,
|
||||
"fmul", // ARM64_INS_FMUL,
|
||||
"fmulx", // ARM64_INS_FMULX,
|
||||
"fneg", // ARM64_INS_FNEG,
|
||||
"fnmad", // ARM64_INS_FNMAD,
|
||||
"fnmadd", // ARM64_INS_FNMADD,
|
||||
"fnmla", // ARM64_INS_FNMLA,
|
||||
"fnmls", // ARM64_INS_FNMLS,
|
||||
"fnmsb", // ARM64_INS_FNMSB,
|
||||
"fnmsub", // ARM64_INS_FNMSUB,
|
||||
"fnmul", // ARM64_INS_FNMUL,
|
||||
"frecpe", // ARM64_INS_FRECPE,
|
||||
"frecps", // ARM64_INS_FRECPS,
|
||||
"frecpx", // ARM64_INS_FRECPX,
|
||||
"frinta", // ARM64_INS_FRINTA,
|
||||
"frinti", // ARM64_INS_FRINTI,
|
||||
"frintm", // ARM64_INS_FRINTM,
|
||||
"frintn", // ARM64_INS_FRINTN,
|
||||
"frintp", // ARM64_INS_FRINTP,
|
||||
"frintx", // ARM64_INS_FRINTX,
|
||||
"frintz", // ARM64_INS_FRINTZ,
|
||||
"frsqrte", // ARM64_INS_FRSQRTE,
|
||||
"frsqrts", // ARM64_INS_FRSQRTS,
|
||||
"fscale", // ARM64_INS_FSCALE,
|
||||
"fsqrt", // ARM64_INS_FSQRT,
|
||||
"fsub", // ARM64_INS_FSUB,
|
||||
"fsubr", // ARM64_INS_FSUBR,
|
||||
"ftmad", // ARM64_INS_FTMAD,
|
||||
"ftsmul", // ARM64_INS_FTSMUL,
|
||||
"ftssel", // ARM64_INS_FTSSEL,
|
||||
"hint", // ARM64_INS_HINT,
|
||||
"hlt", // ARM64_INS_HLT,
|
||||
"hvc", // ARM64_INS_HVC,
|
||||
"incb", // ARM64_INS_INCB,
|
||||
"incd", // ARM64_INS_INCD,
|
||||
"inch", // ARM64_INS_INCH,
|
||||
"incp", // ARM64_INS_INCP,
|
||||
"incw", // ARM64_INS_INCW,
|
||||
"index", // ARM64_INS_INDEX,
|
||||
"ins", // ARM64_INS_INS,
|
||||
"insr", // ARM64_INS_INSR,
|
||||
"isb", // ARM64_INS_ISB,
|
||||
"lasta", // ARM64_INS_LASTA,
|
||||
"lastb", // ARM64_INS_LASTB,
|
||||
"ld1", // ARM64_INS_LD1,
|
||||
"ld1b", // ARM64_INS_LD1B,
|
||||
"ld1d", // ARM64_INS_LD1D,
|
||||
"ld1h", // ARM64_INS_LD1H,
|
||||
"ld1r", // ARM64_INS_LD1R,
|
||||
"ld1rb", // ARM64_INS_LD1RB,
|
||||
"ld1rd", // ARM64_INS_LD1RD,
|
||||
"ld1rh", // ARM64_INS_LD1RH,
|
||||
"ld1rqb", // ARM64_INS_LD1RQB,
|
||||
"ld1rqd", // ARM64_INS_LD1RQD,
|
||||
"ld1rqh", // ARM64_INS_LD1RQH,
|
||||
"ld1rqw", // ARM64_INS_LD1RQW,
|
||||
"ld1rsb", // ARM64_INS_LD1RSB,
|
||||
"ld1rsh", // ARM64_INS_LD1RSH,
|
||||
"ld1rsw", // ARM64_INS_LD1RSW,
|
||||
"ld1rw", // ARM64_INS_LD1RW,
|
||||
"ld1sb", // ARM64_INS_LD1SB,
|
||||
"ld1sh", // ARM64_INS_LD1SH,
|
||||
"ld1sw", // ARM64_INS_LD1SW,
|
||||
"ld1w", // ARM64_INS_LD1W,
|
||||
"ld2", // ARM64_INS_LD2,
|
||||
"ld2b", // ARM64_INS_LD2B,
|
||||
"ld2d", // ARM64_INS_LD2D,
|
||||
"ld2h", // ARM64_INS_LD2H,
|
||||
"ld2r", // ARM64_INS_LD2R,
|
||||
"ld2w", // ARM64_INS_LD2W,
|
||||
"ld3", // ARM64_INS_LD3,
|
||||
"ld3b", // ARM64_INS_LD3B,
|
||||
"ld3d", // ARM64_INS_LD3D,
|
||||
"ld3h", // ARM64_INS_LD3H,
|
||||
"ld3r", // ARM64_INS_LD3R,
|
||||
"ld3w", // ARM64_INS_LD3W,
|
||||
"ld4", // ARM64_INS_LD4,
|
||||
"ld4b", // ARM64_INS_LD4B,
|
||||
"ld4d", // ARM64_INS_LD4D,
|
||||
"ld4h", // ARM64_INS_LD4H,
|
||||
"ld4r", // ARM64_INS_LD4R,
|
||||
"ld4w", // ARM64_INS_LD4W,
|
||||
"ldadd", // ARM64_INS_LDADD,
|
||||
"ldadda", // ARM64_INS_LDADDA,
|
||||
"ldaddab", // ARM64_INS_LDADDAB,
|
||||
"ldaddah", // ARM64_INS_LDADDAH,
|
||||
"ldaddal", // ARM64_INS_LDADDAL,
|
||||
"ldaddalb", // ARM64_INS_LDADDALB,
|
||||
"ldaddalh", // ARM64_INS_LDADDALH,
|
||||
"ldaddb", // ARM64_INS_LDADDB,
|
||||
"ldaddh", // ARM64_INS_LDADDH,
|
||||
"ldaddl", // ARM64_INS_LDADDL,
|
||||
"ldaddlb", // ARM64_INS_LDADDLB,
|
||||
"ldaddlh", // ARM64_INS_LDADDLH,
|
||||
"ldapr", // ARM64_INS_LDAPR,
|
||||
"ldaprb", // ARM64_INS_LDAPRB,
|
||||
"ldaprh", // ARM64_INS_LDAPRH,
|
||||
"ldapur", // ARM64_INS_LDAPUR,
|
||||
"ldapurb", // ARM64_INS_LDAPURB,
|
||||
"ldapurh", // ARM64_INS_LDAPURH,
|
||||
"ldapursb", // ARM64_INS_LDAPURSB,
|
||||
"ldapursh", // ARM64_INS_LDAPURSH,
|
||||
"ldapursw", // ARM64_INS_LDAPURSW,
|
||||
"ldar", // ARM64_INS_LDAR,
|
||||
"ldarb", // ARM64_INS_LDARB,
|
||||
"ldarh", // ARM64_INS_LDARH,
|
||||
"ldaxp", // ARM64_INS_LDAXP,
|
||||
"ldaxr", // ARM64_INS_LDAXR,
|
||||
"ldaxrb", // ARM64_INS_LDAXRB,
|
||||
"ldaxrh", // ARM64_INS_LDAXRH,
|
||||
"ldclr", // ARM64_INS_LDCLR,
|
||||
"ldclra", // ARM64_INS_LDCLRA,
|
||||
"ldclrab", // ARM64_INS_LDCLRAB,
|
||||
"ldclrah", // ARM64_INS_LDCLRAH,
|
||||
"ldclral", // ARM64_INS_LDCLRAL,
|
||||
"ldclralb", // ARM64_INS_LDCLRALB,
|
||||
"ldclralh", // ARM64_INS_LDCLRALH,
|
||||
"ldclrb", // ARM64_INS_LDCLRB,
|
||||
"ldclrh", // ARM64_INS_LDCLRH,
|
||||
"ldclrl", // ARM64_INS_LDCLRL,
|
||||
"ldclrlb", // ARM64_INS_LDCLRLB,
|
||||
"ldclrlh", // ARM64_INS_LDCLRLH,
|
||||
"ldeor", // ARM64_INS_LDEOR,
|
||||
"ldeora", // ARM64_INS_LDEORA,
|
||||
"ldeorab", // ARM64_INS_LDEORAB,
|
||||
"ldeorah", // ARM64_INS_LDEORAH,
|
||||
"ldeoral", // ARM64_INS_LDEORAL,
|
||||
"ldeoralb", // ARM64_INS_LDEORALB,
|
||||
"ldeoralh", // ARM64_INS_LDEORALH,
|
||||
"ldeorb", // ARM64_INS_LDEORB,
|
||||
"ldeorh", // ARM64_INS_LDEORH,
|
||||
"ldeorl", // ARM64_INS_LDEORL,
|
||||
"ldeorlb", // ARM64_INS_LDEORLB,
|
||||
"ldeorlh", // ARM64_INS_LDEORLH,
|
||||
"ldff1b", // ARM64_INS_LDFF1B,
|
||||
"ldff1d", // ARM64_INS_LDFF1D,
|
||||
"ldff1h", // ARM64_INS_LDFF1H,
|
||||
"ldff1sb", // ARM64_INS_LDFF1SB,
|
||||
"ldff1sh", // ARM64_INS_LDFF1SH,
|
||||
"ldff1sw", // ARM64_INS_LDFF1SW,
|
||||
"ldff1w", // ARM64_INS_LDFF1W,
|
||||
"ldlar", // ARM64_INS_LDLAR,
|
||||
"ldlarb", // ARM64_INS_LDLARB,
|
||||
"ldlarh", // ARM64_INS_LDLARH,
|
||||
"ldnf1b", // ARM64_INS_LDNF1B,
|
||||
"ldnf1d", // ARM64_INS_LDNF1D,
|
||||
"ldnf1h", // ARM64_INS_LDNF1H,
|
||||
"ldnf1sb", // ARM64_INS_LDNF1SB,
|
||||
"ldnf1sh", // ARM64_INS_LDNF1SH,
|
||||
"ldnf1sw", // ARM64_INS_LDNF1SW,
|
||||
"ldnf1w", // ARM64_INS_LDNF1W,
|
||||
"ldnp", // ARM64_INS_LDNP,
|
||||
"ldnt1b", // ARM64_INS_LDNT1B,
|
||||
"ldnt1d", // ARM64_INS_LDNT1D,
|
||||
"ldnt1h", // ARM64_INS_LDNT1H,
|
||||
"ldnt1w", // ARM64_INS_LDNT1W,
|
||||
"ldp", // ARM64_INS_LDP,
|
||||
"ldpsw", // ARM64_INS_LDPSW,
|
||||
"ldr", // ARM64_INS_LDR,
|
||||
"ldraa", // ARM64_INS_LDRAA,
|
||||
"ldrab", // ARM64_INS_LDRAB,
|
||||
"ldrb", // ARM64_INS_LDRB,
|
||||
"ldrh", // ARM64_INS_LDRH,
|
||||
"ldrsb", // ARM64_INS_LDRSB,
|
||||
"ldrsh", // ARM64_INS_LDRSH,
|
||||
"ldrsw", // ARM64_INS_LDRSW,
|
||||
"ldset", // ARM64_INS_LDSET,
|
||||
"ldseta", // ARM64_INS_LDSETA,
|
||||
"ldsetab", // ARM64_INS_LDSETAB,
|
||||
"ldsetah", // ARM64_INS_LDSETAH,
|
||||
"ldsetal", // ARM64_INS_LDSETAL,
|
||||
"ldsetalb", // ARM64_INS_LDSETALB,
|
||||
"ldsetalh", // ARM64_INS_LDSETALH,
|
||||
"ldsetb", // ARM64_INS_LDSETB,
|
||||
"ldseth", // ARM64_INS_LDSETH,
|
||||
"ldsetl", // ARM64_INS_LDSETL,
|
||||
"ldsetlb", // ARM64_INS_LDSETLB,
|
||||
"ldsetlh", // ARM64_INS_LDSETLH,
|
||||
"ldsmax", // ARM64_INS_LDSMAX,
|
||||
"ldsmaxa", // ARM64_INS_LDSMAXA,
|
||||
"ldsmaxab", // ARM64_INS_LDSMAXAB,
|
||||
"ldsmaxah", // ARM64_INS_LDSMAXAH,
|
||||
"ldsmaxal", // ARM64_INS_LDSMAXAL,
|
||||
"ldsmaxalb", // ARM64_INS_LDSMAXALB,
|
||||
"ldsmaxalh", // ARM64_INS_LDSMAXALH,
|
||||
"ldsmaxb", // ARM64_INS_LDSMAXB,
|
||||
"ldsmaxh", // ARM64_INS_LDSMAXH,
|
||||
"ldsmaxl", // ARM64_INS_LDSMAXL,
|
||||
"ldsmaxlb", // ARM64_INS_LDSMAXLB,
|
||||
"ldsmaxlh", // ARM64_INS_LDSMAXLH,
|
||||
"ldsmin", // ARM64_INS_LDSMIN,
|
||||
"ldsmina", // ARM64_INS_LDSMINA,
|
||||
"ldsminab", // ARM64_INS_LDSMINAB,
|
||||
"ldsminah", // ARM64_INS_LDSMINAH,
|
||||
"ldsminal", // ARM64_INS_LDSMINAL,
|
||||
"ldsminalb", // ARM64_INS_LDSMINALB,
|
||||
"ldsminalh", // ARM64_INS_LDSMINALH,
|
||||
"ldsminb", // ARM64_INS_LDSMINB,
|
||||
"ldsminh", // ARM64_INS_LDSMINH,
|
||||
"ldsminl", // ARM64_INS_LDSMINL,
|
||||
"ldsminlb", // ARM64_INS_LDSMINLB,
|
||||
"ldsminlh", // ARM64_INS_LDSMINLH,
|
||||
"ldtr", // ARM64_INS_LDTR,
|
||||
"ldtrb", // ARM64_INS_LDTRB,
|
||||
"ldtrh", // ARM64_INS_LDTRH,
|
||||
"ldtrsb", // ARM64_INS_LDTRSB,
|
||||
"ldtrsh", // ARM64_INS_LDTRSH,
|
||||
"ldtrsw", // ARM64_INS_LDTRSW,
|
||||
"ldumax", // ARM64_INS_LDUMAX,
|
||||
"ldumaxa", // ARM64_INS_LDUMAXA,
|
||||
"ldumaxab", // ARM64_INS_LDUMAXAB,
|
||||
"ldumaxah", // ARM64_INS_LDUMAXAH,
|
||||
"ldumaxal", // ARM64_INS_LDUMAXAL,
|
||||
"ldumaxalb", // ARM64_INS_LDUMAXALB,
|
||||
"ldumaxalh", // ARM64_INS_LDUMAXALH,
|
||||
"ldumaxb", // ARM64_INS_LDUMAXB,
|
||||
"ldumaxh", // ARM64_INS_LDUMAXH,
|
||||
"ldumaxl", // ARM64_INS_LDUMAXL,
|
||||
"ldumaxlb", // ARM64_INS_LDUMAXLB,
|
||||
"ldumaxlh", // ARM64_INS_LDUMAXLH,
|
||||
"ldumin", // ARM64_INS_LDUMIN,
|
||||
"ldumina", // ARM64_INS_LDUMINA,
|
||||
"lduminab", // ARM64_INS_LDUMINAB,
|
||||
"lduminah", // ARM64_INS_LDUMINAH,
|
||||
"lduminal", // ARM64_INS_LDUMINAL,
|
||||
"lduminalb", // ARM64_INS_LDUMINALB,
|
||||
"lduminalh", // ARM64_INS_LDUMINALH,
|
||||
"lduminb", // ARM64_INS_LDUMINB,
|
||||
"lduminh", // ARM64_INS_LDUMINH,
|
||||
"lduminl", // ARM64_INS_LDUMINL,
|
||||
"lduminlb", // ARM64_INS_LDUMINLB,
|
||||
"lduminlh", // ARM64_INS_LDUMINLH,
|
||||
"ldur", // ARM64_INS_LDUR,
|
||||
"ldurb", // ARM64_INS_LDURB,
|
||||
"ldurh", // ARM64_INS_LDURH,
|
||||
"ldursb", // ARM64_INS_LDURSB,
|
||||
"ldursh", // ARM64_INS_LDURSH,
|
||||
"ldursw", // ARM64_INS_LDURSW,
|
||||
"ldxp", // ARM64_INS_LDXP,
|
||||
"ldxr", // ARM64_INS_LDXR,
|
||||
"ldxrb", // ARM64_INS_LDXRB,
|
||||
"ldxrh", // ARM64_INS_LDXRH,
|
||||
"lsl", // ARM64_INS_LSL,
|
||||
"lslr", // ARM64_INS_LSLR,
|
||||
"lslv", // ARM64_INS_LSLV,
|
||||
"lsr", // ARM64_INS_LSR,
|
||||
"lsrr", // ARM64_INS_LSRR,
|
||||
"lsrv", // ARM64_INS_LSRV,
|
||||
"mad", // ARM64_INS_MAD,
|
||||
"madd", // ARM64_INS_MADD,
|
||||
"mla", // ARM64_INS_MLA,
|
||||
"mls", // ARM64_INS_MLS,
|
||||
"mneg", // ARM64_INS_MNEG,
|
||||
"mov", // ARM64_INS_MOV,
|
||||
"movi", // ARM64_INS_MOVI,
|
||||
"movk", // ARM64_INS_MOVK,
|
||||
"movn", // ARM64_INS_MOVN,
|
||||
"movprfx", // ARM64_INS_MOVPRFX,
|
||||
"movs", // ARM64_INS_MOVS,
|
||||
"movz", // ARM64_INS_MOVZ,
|
||||
"mrs", // ARM64_INS_MRS,
|
||||
"msb", // ARM64_INS_MSB,
|
||||
"msr", // ARM64_INS_MSR,
|
||||
"msub", // ARM64_INS_MSUB,
|
||||
"mul", // ARM64_INS_MUL,
|
||||
"mvn", // ARM64_INS_MVN,
|
||||
"mvni", // ARM64_INS_MVNI,
|
||||
"nand", // ARM64_INS_NAND,
|
||||
"nands", // ARM64_INS_NANDS,
|
||||
"neg", // ARM64_INS_NEG,
|
||||
"negs", // ARM64_INS_NEGS,
|
||||
"ngc", // ARM64_INS_NGC,
|
||||
"ngcs", // ARM64_INS_NGCS,
|
||||
"nop", // ARM64_INS_NOP,
|
||||
"nor", // ARM64_INS_NOR,
|
||||
"nors", // ARM64_INS_NORS,
|
||||
"not", // ARM64_INS_NOT,
|
||||
"nots", // ARM64_INS_NOTS,
|
||||
"orn", // ARM64_INS_ORN,
|
||||
"orns", // ARM64_INS_ORNS,
|
||||
"orr", // ARM64_INS_ORR,
|
||||
"orrs", // ARM64_INS_ORRS,
|
||||
"orv", // ARM64_INS_ORV,
|
||||
"pacda", // ARM64_INS_PACDA,
|
||||
"pacdb", // ARM64_INS_PACDB,
|
||||
"pacdza", // ARM64_INS_PACDZA,
|
||||
"pacdzb", // ARM64_INS_PACDZB,
|
||||
"pacga", // ARM64_INS_PACGA,
|
||||
"pacia", // ARM64_INS_PACIA,
|
||||
"pacia1716", // ARM64_INS_PACIA1716,
|
||||
"paciasp", // ARM64_INS_PACIASP,
|
||||
"paciaz", // ARM64_INS_PACIAZ,
|
||||
"pacib", // ARM64_INS_PACIB,
|
||||
"pacib1716", // ARM64_INS_PACIB1716,
|
||||
"pacibsp", // ARM64_INS_PACIBSP,
|
||||
"pacibz", // ARM64_INS_PACIBZ,
|
||||
"paciza", // ARM64_INS_PACIZA,
|
||||
"pacizb", // ARM64_INS_PACIZB,
|
||||
"pfalse", // ARM64_INS_PFALSE,
|
||||
"pfirst", // ARM64_INS_PFIRST,
|
||||
"pmul", // ARM64_INS_PMUL,
|
||||
"pmull", // ARM64_INS_PMULL,
|
||||
"pmull2", // ARM64_INS_PMULL2,
|
||||
"pnext", // ARM64_INS_PNEXT,
|
||||
"prfb", // ARM64_INS_PRFB,
|
||||
"prfd", // ARM64_INS_PRFD,
|
||||
"prfh", // ARM64_INS_PRFH,
|
||||
"prfm", // ARM64_INS_PRFM,
|
||||
"prfum", // ARM64_INS_PRFUM,
|
||||
"prfw", // ARM64_INS_PRFW,
|
||||
"psb", // ARM64_INS_PSB,
|
||||
"ptest", // ARM64_INS_PTEST,
|
||||
"ptrue", // ARM64_INS_PTRUE,
|
||||
"ptrues", // ARM64_INS_PTRUES,
|
||||
"punpkhi", // ARM64_INS_PUNPKHI,
|
||||
"punpklo", // ARM64_INS_PUNPKLO,
|
||||
"raddhn", // ARM64_INS_RADDHN,
|
||||
"raddhn2", // ARM64_INS_RADDHN2,
|
||||
"rax1", // ARM64_INS_RAX1,
|
||||
"rbit", // ARM64_INS_RBIT,
|
||||
"rdffr", // ARM64_INS_RDFFR,
|
||||
"rdffrs", // ARM64_INS_RDFFRS,
|
||||
"rdvl", // ARM64_INS_RDVL,
|
||||
"ret", // ARM64_INS_RET,
|
||||
"retaa", // ARM64_INS_RETAA,
|
||||
"retab", // ARM64_INS_RETAB,
|
||||
"rev", // ARM64_INS_REV,
|
||||
"rev16", // ARM64_INS_REV16,
|
||||
"rev32", // ARM64_INS_REV32,
|
||||
"rev64", // ARM64_INS_REV64,
|
||||
"revb", // ARM64_INS_REVB,
|
||||
"revh", // ARM64_INS_REVH,
|
||||
"revw", // ARM64_INS_REVW,
|
||||
"rmif", // ARM64_INS_RMIF,
|
||||
"ror", // ARM64_INS_ROR,
|
||||
"rorv", // ARM64_INS_RORV,
|
||||
"rshrn", // ARM64_INS_RSHRN,
|
||||
"rshrn2", // ARM64_INS_RSHRN2,
|
||||
"rsubhn", // ARM64_INS_RSUBHN,
|
||||
"rsubhn2", // ARM64_INS_RSUBHN2,
|
||||
"saba", // ARM64_INS_SABA,
|
||||
"sabal", // ARM64_INS_SABAL,
|
||||
"sabal2", // ARM64_INS_SABAL2,
|
||||
"sabd", // ARM64_INS_SABD,
|
||||
"sabdl", // ARM64_INS_SABDL,
|
||||
"sabdl2", // ARM64_INS_SABDL2,
|
||||
"sadalp", // ARM64_INS_SADALP,
|
||||
"saddl", // ARM64_INS_SADDL,
|
||||
"saddl2", // ARM64_INS_SADDL2,
|
||||
"saddlp", // ARM64_INS_SADDLP,
|
||||
"saddlv", // ARM64_INS_SADDLV,
|
||||
"saddv", // ARM64_INS_SADDV,
|
||||
"saddw", // ARM64_INS_SADDW,
|
||||
"saddw2", // ARM64_INS_SADDW2,
|
||||
"sbc", // ARM64_INS_SBC,
|
||||
"sbcs", // ARM64_INS_SBCS,
|
||||
"sbfm", // ARM64_INS_SBFM,
|
||||
"scvtf", // ARM64_INS_SCVTF,
|
||||
"sdiv", // ARM64_INS_SDIV,
|
||||
"sdivr", // ARM64_INS_SDIVR,
|
||||
"sdot", // ARM64_INS_SDOT,
|
||||
"sel", // ARM64_INS_SEL,
|
||||
"setf16", // ARM64_INS_SETF16,
|
||||
"setf8", // ARM64_INS_SETF8,
|
||||
"setffr", // ARM64_INS_SETFFR,
|
||||
"sev", // ARM64_INS_SEV,
|
||||
"sevl", // ARM64_INS_SEVL,
|
||||
"sha1c", // ARM64_INS_SHA1C,
|
||||
"sha1h", // ARM64_INS_SHA1H,
|
||||
"sha1m", // ARM64_INS_SHA1M,
|
||||
"sha1p", // ARM64_INS_SHA1P,
|
||||
"sha1su0", // ARM64_INS_SHA1SU0,
|
||||
"sha1su1", // ARM64_INS_SHA1SU1,
|
||||
"sha256h", // ARM64_INS_SHA256H,
|
||||
"sha256h2", // ARM64_INS_SHA256H2,
|
||||
"sha256su0", // ARM64_INS_SHA256SU0,
|
||||
"sha256su1", // ARM64_INS_SHA256SU1,
|
||||
"sha512h", // ARM64_INS_SHA512H,
|
||||
"sha512h2", // ARM64_INS_SHA512H2,
|
||||
"sha512su0", // ARM64_INS_SHA512SU0,
|
||||
"sha512su1", // ARM64_INS_SHA512SU1,
|
||||
"shadd", // ARM64_INS_SHADD,
|
||||
"shl", // ARM64_INS_SHL,
|
||||
"shll", // ARM64_INS_SHLL,
|
||||
"shll2", // ARM64_INS_SHLL2,
|
||||
"shrn", // ARM64_INS_SHRN,
|
||||
"shrn2", // ARM64_INS_SHRN2,
|
||||
"shsub", // ARM64_INS_SHSUB,
|
||||
"sli", // ARM64_INS_SLI,
|
||||
"sm3partw1", // ARM64_INS_SM3PARTW1,
|
||||
"sm3partw2", // ARM64_INS_SM3PARTW2,
|
||||
"sm3ss1", // ARM64_INS_SM3SS1,
|
||||
"sm3tt1a", // ARM64_INS_SM3TT1A,
|
||||
"sm3tt1b", // ARM64_INS_SM3TT1B,
|
||||
"sm3tt2a", // ARM64_INS_SM3TT2A,
|
||||
"sm3tt2b", // ARM64_INS_SM3TT2B,
|
||||
"sm4e", // ARM64_INS_SM4E,
|
||||
"sm4ekey", // ARM64_INS_SM4EKEY,
|
||||
"smaddl", // ARM64_INS_SMADDL,
|
||||
"smax", // ARM64_INS_SMAX,
|
||||
"smaxp", // ARM64_INS_SMAXP,
|
||||
"smaxv", // ARM64_INS_SMAXV,
|
||||
"smc", // ARM64_INS_SMC,
|
||||
"smin", // ARM64_INS_SMIN,
|
||||
"sminp", // ARM64_INS_SMINP,
|
||||
"sminv", // ARM64_INS_SMINV,
|
||||
"smlal", // ARM64_INS_SMLAL,
|
||||
"smlal2", // ARM64_INS_SMLAL2,
|
||||
"smlsl", // ARM64_INS_SMLSL,
|
||||
"smlsl2", // ARM64_INS_SMLSL2,
|
||||
"smnegl", // ARM64_INS_SMNEGL,
|
||||
"smov", // ARM64_INS_SMOV,
|
||||
"smsubl", // ARM64_INS_SMSUBL,
|
||||
"smulh", // ARM64_INS_SMULH,
|
||||
"smull", // ARM64_INS_SMULL,
|
||||
"smull2", // ARM64_INS_SMULL2,
|
||||
"splice", // ARM64_INS_SPLICE,
|
||||
"sqabs", // ARM64_INS_SQABS,
|
||||
"sqadd", // ARM64_INS_SQADD,
|
||||
"sqdecb", // ARM64_INS_SQDECB,
|
||||
"sqdecd", // ARM64_INS_SQDECD,
|
||||
"sqdech", // ARM64_INS_SQDECH,
|
||||
"sqdecp", // ARM64_INS_SQDECP,
|
||||
"sqdecw", // ARM64_INS_SQDECW,
|
||||
"sqdmlal", // ARM64_INS_SQDMLAL,
|
||||
"sqdmlal2", // ARM64_INS_SQDMLAL2,
|
||||
"sqdmlsl", // ARM64_INS_SQDMLSL,
|
||||
"sqdmlsl2", // ARM64_INS_SQDMLSL2,
|
||||
"sqdmulh", // ARM64_INS_SQDMULH,
|
||||
"sqdmull", // ARM64_INS_SQDMULL,
|
||||
"sqdmull2", // ARM64_INS_SQDMULL2,
|
||||
"sqincb", // ARM64_INS_SQINCB,
|
||||
"sqincd", // ARM64_INS_SQINCD,
|
||||
"sqinch", // ARM64_INS_SQINCH,
|
||||
"sqincp", // ARM64_INS_SQINCP,
|
||||
"sqincw", // ARM64_INS_SQINCW,
|
||||
"sqneg", // ARM64_INS_SQNEG,
|
||||
"sqrdmlah", // ARM64_INS_SQRDMLAH,
|
||||
"sqrdmlsh", // ARM64_INS_SQRDMLSH,
|
||||
"sqrdmulh", // ARM64_INS_SQRDMULH,
|
||||
"sqrshl", // ARM64_INS_SQRSHL,
|
||||
"sqrshrn", // ARM64_INS_SQRSHRN,
|
||||
"sqrshrn2", // ARM64_INS_SQRSHRN2,
|
||||
"sqrshrun", // ARM64_INS_SQRSHRUN,
|
||||
"sqrshrun2", // ARM64_INS_SQRSHRUN2,
|
||||
"sqshl", // ARM64_INS_SQSHL,
|
||||
"sqshlu", // ARM64_INS_SQSHLU,
|
||||
"sqshrn", // ARM64_INS_SQSHRN,
|
||||
"sqshrn2", // ARM64_INS_SQSHRN2,
|
||||
"sqshrun", // ARM64_INS_SQSHRUN,
|
||||
"sqshrun2", // ARM64_INS_SQSHRUN2,
|
||||
"sqsub", // ARM64_INS_SQSUB,
|
||||
"sqxtn", // ARM64_INS_SQXTN,
|
||||
"sqxtn2", // ARM64_INS_SQXTN2,
|
||||
"sqxtun", // ARM64_INS_SQXTUN,
|
||||
"sqxtun2", // ARM64_INS_SQXTUN2,
|
||||
"srhadd", // ARM64_INS_SRHADD,
|
||||
"sri", // ARM64_INS_SRI,
|
||||
"srshl", // ARM64_INS_SRSHL,
|
||||
"srshr", // ARM64_INS_SRSHR,
|
||||
"srsra", // ARM64_INS_SRSRA,
|
||||
"sshl", // ARM64_INS_SSHL,
|
||||
"sshll", // ARM64_INS_SSHLL,
|
||||
"sshll2", // ARM64_INS_SSHLL2,
|
||||
"sshr", // ARM64_INS_SSHR,
|
||||
"ssra", // ARM64_INS_SSRA,
|
||||
"ssubl", // ARM64_INS_SSUBL,
|
||||
"ssubl2", // ARM64_INS_SSUBL2,
|
||||
"ssubw", // ARM64_INS_SSUBW,
|
||||
"ssubw2", // ARM64_INS_SSUBW2,
|
||||
"st1", // ARM64_INS_ST1,
|
||||
"st1b", // ARM64_INS_ST1B,
|
||||
"st1d", // ARM64_INS_ST1D,
|
||||
"st1h", // ARM64_INS_ST1H,
|
||||
"st1w", // ARM64_INS_ST1W,
|
||||
"st2", // ARM64_INS_ST2,
|
||||
"st2b", // ARM64_INS_ST2B,
|
||||
"st2d", // ARM64_INS_ST2D,
|
||||
"st2h", // ARM64_INS_ST2H,
|
||||
"st2w", // ARM64_INS_ST2W,
|
||||
"st3", // ARM64_INS_ST3,
|
||||
"st3b", // ARM64_INS_ST3B,
|
||||
"st3d", // ARM64_INS_ST3D,
|
||||
"st3h", // ARM64_INS_ST3H,
|
||||
"st3w", // ARM64_INS_ST3W,
|
||||
"st4", // ARM64_INS_ST4,
|
||||
"st4b", // ARM64_INS_ST4B,
|
||||
"st4d", // ARM64_INS_ST4D,
|
||||
"st4h", // ARM64_INS_ST4H,
|
||||
"st4w", // ARM64_INS_ST4W,
|
||||
"stadd", // ARM64_INS_STADD,
|
||||
"staddb", // ARM64_INS_STADDB,
|
||||
"staddh", // ARM64_INS_STADDH,
|
||||
"staddl", // ARM64_INS_STADDL,
|
||||
"staddlb", // ARM64_INS_STADDLB,
|
||||
"staddlh", // ARM64_INS_STADDLH,
|
||||
"stclr", // ARM64_INS_STCLR,
|
||||
"stclrb", // ARM64_INS_STCLRB,
|
||||
"stclrh", // ARM64_INS_STCLRH,
|
||||
"stclrl", // ARM64_INS_STCLRL,
|
||||
"stclrlb", // ARM64_INS_STCLRLB,
|
||||
"stclrlh", // ARM64_INS_STCLRLH,
|
||||
"steor", // ARM64_INS_STEOR,
|
||||
"steorb", // ARM64_INS_STEORB,
|
||||
"steorh", // ARM64_INS_STEORH,
|
||||
"steorl", // ARM64_INS_STEORL,
|
||||
"steorlb", // ARM64_INS_STEORLB,
|
||||
"steorlh", // ARM64_INS_STEORLH,
|
||||
"stllr", // ARM64_INS_STLLR,
|
||||
"stllrb", // ARM64_INS_STLLRB,
|
||||
"stllrh", // ARM64_INS_STLLRH,
|
||||
"stlr", // ARM64_INS_STLR,
|
||||
"stlrb", // ARM64_INS_STLRB,
|
||||
"stlrh", // ARM64_INS_STLRH,
|
||||
"stlur", // ARM64_INS_STLUR,
|
||||
"stlurb", // ARM64_INS_STLURB,
|
||||
"stlurh", // ARM64_INS_STLURH,
|
||||
"stlxp", // ARM64_INS_STLXP,
|
||||
"stlxr", // ARM64_INS_STLXR,
|
||||
"stlxrb", // ARM64_INS_STLXRB,
|
||||
"stlxrh", // ARM64_INS_STLXRH,
|
||||
"stnp", // ARM64_INS_STNP,
|
||||
"stnt1b", // ARM64_INS_STNT1B,
|
||||
"stnt1d", // ARM64_INS_STNT1D,
|
||||
"stnt1h", // ARM64_INS_STNT1H,
|
||||
"stnt1w", // ARM64_INS_STNT1W,
|
||||
"stp", // ARM64_INS_STP,
|
||||
"str", // ARM64_INS_STR,
|
||||
"strb", // ARM64_INS_STRB,
|
||||
"strh", // ARM64_INS_STRH,
|
||||
"stset", // ARM64_INS_STSET,
|
||||
"stsetb", // ARM64_INS_STSETB,
|
||||
"stseth", // ARM64_INS_STSETH,
|
||||
"stsetl", // ARM64_INS_STSETL,
|
||||
"stsetlb", // ARM64_INS_STSETLB,
|
||||
"stsetlh", // ARM64_INS_STSETLH,
|
||||
"stsmax", // ARM64_INS_STSMAX,
|
||||
"stsmaxb", // ARM64_INS_STSMAXB,
|
||||
"stsmaxh", // ARM64_INS_STSMAXH,
|
||||
"stsmaxl", // ARM64_INS_STSMAXL,
|
||||
"stsmaxlb", // ARM64_INS_STSMAXLB,
|
||||
"stsmaxlh", // ARM64_INS_STSMAXLH,
|
||||
"stsmin", // ARM64_INS_STSMIN,
|
||||
"stsminb", // ARM64_INS_STSMINB,
|
||||
"stsminh", // ARM64_INS_STSMINH,
|
||||
"stsminl", // ARM64_INS_STSMINL,
|
||||
"stsminlb", // ARM64_INS_STSMINLB,
|
||||
"stsminlh", // ARM64_INS_STSMINLH,
|
||||
"sttr", // ARM64_INS_STTR,
|
||||
"sttrb", // ARM64_INS_STTRB,
|
||||
"sttrh", // ARM64_INS_STTRH,
|
||||
"stumax", // ARM64_INS_STUMAX,
|
||||
"stumaxb", // ARM64_INS_STUMAXB,
|
||||
"stumaxh", // ARM64_INS_STUMAXH,
|
||||
"stumaxl", // ARM64_INS_STUMAXL,
|
||||
"stumaxlb", // ARM64_INS_STUMAXLB,
|
||||
"stumaxlh", // ARM64_INS_STUMAXLH,
|
||||
"stumin", // ARM64_INS_STUMIN,
|
||||
"stuminb", // ARM64_INS_STUMINB,
|
||||
"stuminh", // ARM64_INS_STUMINH,
|
||||
"stuminl", // ARM64_INS_STUMINL,
|
||||
"stuminlb", // ARM64_INS_STUMINLB,
|
||||
"stuminlh", // ARM64_INS_STUMINLH,
|
||||
"stur", // ARM64_INS_STUR,
|
||||
"sturb", // ARM64_INS_STURB,
|
||||
"sturh", // ARM64_INS_STURH,
|
||||
"stxp", // ARM64_INS_STXP,
|
||||
"stxr", // ARM64_INS_STXR,
|
||||
"stxrb", // ARM64_INS_STXRB,
|
||||
"stxrh", // ARM64_INS_STXRH,
|
||||
"sub", // ARM64_INS_SUB,
|
||||
"subhn", // ARM64_INS_SUBHN,
|
||||
"subhn2", // ARM64_INS_SUBHN2,
|
||||
"subr", // ARM64_INS_SUBR,
|
||||
"subs", // ARM64_INS_SUBS,
|
||||
"sunpkhi", // ARM64_INS_SUNPKHI,
|
||||
"sunpklo", // ARM64_INS_SUNPKLO,
|
||||
"suqadd", // ARM64_INS_SUQADD,
|
||||
"svc", // ARM64_INS_SVC,
|
||||
"swp", // ARM64_INS_SWP,
|
||||
"swpa", // ARM64_INS_SWPA,
|
||||
"swpab", // ARM64_INS_SWPAB,
|
||||
"swpah", // ARM64_INS_SWPAH,
|
||||
"swpal", // ARM64_INS_SWPAL,
|
||||
"swpalb", // ARM64_INS_SWPALB,
|
||||
"swpalh", // ARM64_INS_SWPALH,
|
||||
"swpb", // ARM64_INS_SWPB,
|
||||
"swph", // ARM64_INS_SWPH,
|
||||
"swpl", // ARM64_INS_SWPL,
|
||||
"swplb", // ARM64_INS_SWPLB,
|
||||
"swplh", // ARM64_INS_SWPLH,
|
||||
"sxtb", // ARM64_INS_SXTB,
|
||||
"sxth", // ARM64_INS_SXTH,
|
||||
"sxtl", // ARM64_INS_SXTL,
|
||||
"sxtl2", // ARM64_INS_SXTL2,
|
||||
"sxtw", // ARM64_INS_SXTW,
|
||||
"sys", // ARM64_INS_SYS,
|
||||
"sysl", // ARM64_INS_SYSL,
|
||||
"tbl", // ARM64_INS_TBL,
|
||||
"tbnz", // ARM64_INS_TBNZ,
|
||||
"tbx", // ARM64_INS_TBX,
|
||||
"tbz", // ARM64_INS_TBZ,
|
||||
"trn1", // ARM64_INS_TRN1,
|
||||
"trn2", // ARM64_INS_TRN2,
|
||||
"tsb", // ARM64_INS_TSB,
|
||||
"tst", // ARM64_INS_TST,
|
||||
"uaba", // ARM64_INS_UABA,
|
||||
"uabal", // ARM64_INS_UABAL,
|
||||
"uabal2", // ARM64_INS_UABAL2,
|
||||
"uabd", // ARM64_INS_UABD,
|
||||
"uabdl", // ARM64_INS_UABDL,
|
||||
"uabdl2", // ARM64_INS_UABDL2,
|
||||
"uadalp", // ARM64_INS_UADALP,
|
||||
"uaddl", // ARM64_INS_UADDL,
|
||||
"uaddl2", // ARM64_INS_UADDL2,
|
||||
"uaddlp", // ARM64_INS_UADDLP,
|
||||
"uaddlv", // ARM64_INS_UADDLV,
|
||||
"uaddv", // ARM64_INS_UADDV,
|
||||
"uaddw", // ARM64_INS_UADDW,
|
||||
"uaddw2", // ARM64_INS_UADDW2,
|
||||
"ubfm", // ARM64_INS_UBFM,
|
||||
"ucvtf", // ARM64_INS_UCVTF,
|
||||
"udiv", // ARM64_INS_UDIV,
|
||||
"udivr", // ARM64_INS_UDIVR,
|
||||
"udot", // ARM64_INS_UDOT,
|
||||
"uhadd", // ARM64_INS_UHADD,
|
||||
"uhsub", // ARM64_INS_UHSUB,
|
||||
"umaddl", // ARM64_INS_UMADDL,
|
||||
"umax", // ARM64_INS_UMAX,
|
||||
"umaxp", // ARM64_INS_UMAXP,
|
||||
"umaxv", // ARM64_INS_UMAXV,
|
||||
"umin", // ARM64_INS_UMIN,
|
||||
"uminp", // ARM64_INS_UMINP,
|
||||
"uminv", // ARM64_INS_UMINV,
|
||||
"umlal", // ARM64_INS_UMLAL,
|
||||
"umlal2", // ARM64_INS_UMLAL2,
|
||||
"umlsl", // ARM64_INS_UMLSL,
|
||||
"umlsl2", // ARM64_INS_UMLSL2,
|
||||
"umnegl", // ARM64_INS_UMNEGL,
|
||||
"umov", // ARM64_INS_UMOV,
|
||||
"umsubl", // ARM64_INS_UMSUBL,
|
||||
"umulh", // ARM64_INS_UMULH,
|
||||
"umull", // ARM64_INS_UMULL,
|
||||
"umull2", // ARM64_INS_UMULL2,
|
||||
"uqadd", // ARM64_INS_UQADD,
|
||||
"uqdecb", // ARM64_INS_UQDECB,
|
||||
"uqdecd", // ARM64_INS_UQDECD,
|
||||
"uqdech", // ARM64_INS_UQDECH,
|
||||
"uqdecp", // ARM64_INS_UQDECP,
|
||||
"uqdecw", // ARM64_INS_UQDECW,
|
||||
"uqincb", // ARM64_INS_UQINCB,
|
||||
"uqincd", // ARM64_INS_UQINCD,
|
||||
"uqinch", // ARM64_INS_UQINCH,
|
||||
"uqincp", // ARM64_INS_UQINCP,
|
||||
"uqincw", // ARM64_INS_UQINCW,
|
||||
"uqrshl", // ARM64_INS_UQRSHL,
|
||||
"uqrshrn", // ARM64_INS_UQRSHRN,
|
||||
"uqrshrn2", // ARM64_INS_UQRSHRN2,
|
||||
"uqshl", // ARM64_INS_UQSHL,
|
||||
"uqshrn", // ARM64_INS_UQSHRN,
|
||||
"uqshrn2", // ARM64_INS_UQSHRN2,
|
||||
"uqsub", // ARM64_INS_UQSUB,
|
||||
"uqxtn", // ARM64_INS_UQXTN,
|
||||
"uqxtn2", // ARM64_INS_UQXTN2,
|
||||
"urecpe", // ARM64_INS_URECPE,
|
||||
"urhadd", // ARM64_INS_URHADD,
|
||||
"urshl", // ARM64_INS_URSHL,
|
||||
"urshr", // ARM64_INS_URSHR,
|
||||
"ursqrte", // ARM64_INS_URSQRTE,
|
||||
"ursra", // ARM64_INS_URSRA,
|
||||
"ushl", // ARM64_INS_USHL,
|
||||
"ushll", // ARM64_INS_USHLL,
|
||||
"ushll2", // ARM64_INS_USHLL2,
|
||||
"ushr", // ARM64_INS_USHR,
|
||||
"usqadd", // ARM64_INS_USQADD,
|
||||
"usra", // ARM64_INS_USRA,
|
||||
"usubl", // ARM64_INS_USUBL,
|
||||
"usubl2", // ARM64_INS_USUBL2,
|
||||
"usubw", // ARM64_INS_USUBW,
|
||||
"usubw2", // ARM64_INS_USUBW2,
|
||||
"uunpkhi", // ARM64_INS_UUNPKHI,
|
||||
"uunpklo", // ARM64_INS_UUNPKLO,
|
||||
"uxtb", // ARM64_INS_UXTB,
|
||||
"uxth", // ARM64_INS_UXTH,
|
||||
"uxtl", // ARM64_INS_UXTL,
|
||||
"uxtl2", // ARM64_INS_UXTL2,
|
||||
"uxtw", // ARM64_INS_UXTW,
|
||||
"uzp1", // ARM64_INS_UZP1,
|
||||
"uzp2", // ARM64_INS_UZP2,
|
||||
"wfe", // ARM64_INS_WFE,
|
||||
"wfi", // ARM64_INS_WFI,
|
||||
"whilele", // ARM64_INS_WHILELE,
|
||||
"whilelo", // ARM64_INS_WHILELO,
|
||||
"whilels", // ARM64_INS_WHILELS,
|
||||
"whilelt", // ARM64_INS_WHILELT,
|
||||
"wrffr", // ARM64_INS_WRFFR,
|
||||
"xar", // ARM64_INS_XAR,
|
||||
"xpacd", // ARM64_INS_XPACD,
|
||||
"xpaci", // ARM64_INS_XPACI,
|
||||
"xpaclri", // ARM64_INS_XPACLRI,
|
||||
"xtn", // ARM64_INS_XTN,
|
||||
"xtn2", // ARM64_INS_XTN2,
|
||||
"yield", // ARM64_INS_YIELD,
|
||||
"zip1", // ARM64_INS_ZIP1,
|
||||
"zip2", // ARM64_INS_ZIP2,
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -165,7 +165,7 @@ MClassSysReg *lookupMClassSysRegByM2M3Encoding8(uint16_t encoding)
|
||||
{ 0x303, 7 },
|
||||
};
|
||||
|
||||
i = binsearch_IndexType(Index, ARR_SIZE(Index), encoding);
|
||||
i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), encoding);
|
||||
if (i == -1)
|
||||
return NULL;
|
||||
else
|
||||
@ -215,7 +215,7 @@ MClassSysReg *lookupMClassSysRegByM1Encoding12(uint16_t encoding)
|
||||
{ 0x1803, 15 },
|
||||
};
|
||||
|
||||
i = binsearch_IndexType(Index, ARR_SIZE(Index), encoding);
|
||||
i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), encoding);
|
||||
if (i == -1)
|
||||
return NULL;
|
||||
else
|
||||
@ -261,7 +261,7 @@ BankedReg *lookupBankedRegByEncoding(uint8_t encoding)
|
||||
{ 0x3E, 32 },
|
||||
};
|
||||
|
||||
i = binsearch_IndexType(Index, ARR_SIZE(Index), encoding);
|
||||
i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), encoding);
|
||||
if (i == -1)
|
||||
return NULL;
|
||||
else
|
||||
|
||||
@ -515,35 +515,4 @@ void ARM_reg_access(const cs_insn *insn,
|
||||
}
|
||||
#endif
|
||||
|
||||
// binary search for encoding in IndexType array
|
||||
// return -1 if not found, or index if found
|
||||
unsigned int binsearch_IndexType(const struct IndexType *index, size_t size, uint16_t encoding)
|
||||
{
|
||||
// binary searching since the index is sorted in encoding order
|
||||
size_t left, right, m;
|
||||
|
||||
right = size - 1;
|
||||
|
||||
if (encoding < index[0].encoding || encoding > index[right].encoding)
|
||||
// not found
|
||||
return -1;
|
||||
|
||||
left = 0;
|
||||
|
||||
while(left <= right) {
|
||||
m = (left + right) / 2;
|
||||
if (encoding == index[m].encoding) {
|
||||
return m;
|
||||
}
|
||||
|
||||
if (encoding < index[m].encoding)
|
||||
right = m - 1;
|
||||
else
|
||||
left = m + 1;
|
||||
}
|
||||
|
||||
// not found
|
||||
return -1;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
@ -29,15 +29,6 @@ void ARM_reg_access(const cs_insn *insn,
|
||||
cs_regs regs_read, uint8_t *regs_read_count,
|
||||
cs_regs regs_write, uint8_t *regs_write_count);
|
||||
|
||||
struct IndexType {
|
||||
uint16_t encoding;
|
||||
unsigned index;
|
||||
};
|
||||
|
||||
// binary search for encoding in IndexType array
|
||||
// return -1 if not found, or index if found
|
||||
unsigned int binsearch_IndexType(const struct IndexType *index, size_t size, uint16_t encoding);
|
||||
|
||||
typedef struct BankedReg {
|
||||
const char *Name;
|
||||
arm_sysreg sysreg;
|
||||
|
||||
@ -75,8 +75,6 @@ public class TestArm64 {
|
||||
System.out.printf("\t\t\tExt: %d\n", i.ext);
|
||||
if (i.vas != ARM64_VAS_INVALID)
|
||||
System.out.printf("\t\t\tVector Arrangement Specifier: 0x%x\n", i.vas);
|
||||
if (i.vess != ARM64_VESS_INVALID)
|
||||
System.out.printf("\t\t\tVector Element Size Specifier: %d\n", i.vess);
|
||||
if (i.vector_index != -1)
|
||||
System.out.printf("\t\t\tVector Index: %d\n", i.vector_index);
|
||||
|
||||
|
||||
@ -53,7 +53,6 @@ public class Arm64 {
|
||||
public static class Operand extends Structure {
|
||||
public int vector_index;
|
||||
public int vas;
|
||||
public int vess;
|
||||
public OpShift shift;
|
||||
public int ext;
|
||||
public int type;
|
||||
@ -72,14 +71,13 @@ public class Arm64 {
|
||||
readField("value");
|
||||
readField("ext");
|
||||
readField("shift");
|
||||
readField("vess");
|
||||
readField("vas");
|
||||
readField("vector_index");
|
||||
}
|
||||
|
||||
@Override
|
||||
public List getFieldOrder() {
|
||||
return Arrays.asList("vector_index", "vas", "vess", "shift", "ext", "type", "value");
|
||||
return Arrays.asList("vector_index", "vas", "shift", "ext", "type", "value");
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -32,7 +32,6 @@ type arm64_op_value =
|
||||
type arm64_op = {
|
||||
vector_index: int;
|
||||
vas: int;
|
||||
vess: int;
|
||||
shift: arm64_op_shift;
|
||||
ext: int;
|
||||
value: arm64_op_value;
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -122,7 +122,7 @@ CAMLprim value _cs_disasm(cs_arch arch, csh handle, const uint8_t * code, size_t
|
||||
if (lcount > 0) {
|
||||
array = caml_alloc(lcount, 0);
|
||||
for (i = 0; i < lcount; i++) {
|
||||
tmp2 = caml_alloc(6, 0);
|
||||
tmp2 = caml_alloc(5, 0);
|
||||
switch(insn[j-1].detail->arm.operands[i].type) {
|
||||
case ARM_OP_REG:
|
||||
case ARM_OP_SYSREG:
|
||||
@ -253,10 +253,9 @@ CAMLprim value _cs_disasm(cs_arch arch, csh handle, const uint8_t * code, size_t
|
||||
|
||||
Store_field(tmp2, 0, Val_int(insn[j-1].detail->arm64.operands[i].vector_index));
|
||||
Store_field(tmp2, 1, Val_int(insn[j-1].detail->arm64.operands[i].vas));
|
||||
Store_field(tmp2, 2, Val_int(insn[j-1].detail->arm64.operands[i].vess));
|
||||
Store_field(tmp2, 3, tmp3);
|
||||
Store_field(tmp2, 4, Val_int(insn[j-1].detail->arm64.operands[i].ext));
|
||||
Store_field(tmp2, 5, tmp);
|
||||
Store_field(tmp2, 2, tmp3);
|
||||
Store_field(tmp2, 3, Val_int(insn[j-1].detail->arm64.operands[i].ext));
|
||||
Store_field(tmp2, 4, tmp);
|
||||
|
||||
Store_field(array, i, tmp2);
|
||||
}
|
||||
|
||||
@ -34,7 +34,6 @@ class Arm64Op(ctypes.Structure):
|
||||
_fields_ = (
|
||||
('vector_index', ctypes.c_int),
|
||||
('vas', ctypes.c_int),
|
||||
('vess', ctypes.c_int),
|
||||
('shift', Arm64OpShift),
|
||||
('ext', ctypes.c_uint),
|
||||
('type', ctypes.c_uint),
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -69,9 +69,6 @@ def print_insn_detail(insn):
|
||||
if i.vas != ARM64_VAS_INVALID:
|
||||
print("\t\t\tVector Arrangement Specifier: 0x%x" % i.vas)
|
||||
|
||||
if i.vess != ARM64_VESS_INVALID:
|
||||
print("\t\t\tVector Element Size Specifier: %u" % i.vess)
|
||||
|
||||
if i.vector_index != -1:
|
||||
print("\t\t\tVector Index: %u" % i.vector_index)
|
||||
|
||||
|
||||
@ -102,9 +102,6 @@ void print_insn_detail_arm64(csh handle, cs_insn *ins)
|
||||
if (op->vas != ARM64_VAS_INVALID)
|
||||
printf("\t\t\tVector Arrangement Specifier: 0x%x\n", op->vas);
|
||||
|
||||
if (op->vess != ARM64_VESS_INVALID)
|
||||
printf("\t\t\tVector Element Size Specifier: %u\n", op->vess);
|
||||
|
||||
if (op->vector_index != -1)
|
||||
printf("\t\t\tVector Index: %u\n", op->vector_index);
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,3 +1,19 @@
|
||||
!# issue 1452
|
||||
!# CS_ARCH_ARM64, CS_MODE_LITTLE_ENDIAN, CS_OPT_DETAIL
|
||||
0x20,0x3c,0x0c,0x0e == mov w0, v1.s[1] ; Vector Arrangement Specifier: 0xb
|
||||
|
||||
!# issue 1452
|
||||
!# CS_ARCH_ARM64, CS_MODE_LITTLE_ENDIAN, CS_OPT_DETAIL
|
||||
0x20,0x3c,0x18,0x4e == mov x0, v1.d[1] ; Vector Arrangement Specifier: 0xd
|
||||
|
||||
!# issue 1452
|
||||
!# CS_ARCH_ARM64, CS_MODE_LITTLE_ENDIAN, CS_OPT_DETAIL
|
||||
0x20,0x3c,0x03,0x0e == umov w0, v1.b[1] ; Vector Arrangement Specifier: 0x4
|
||||
|
||||
!# issue 1452
|
||||
!# CS_ARCH_ARM64, CS_MODE_LITTLE_ENDIAN, CS_OPT_DETAIL
|
||||
0x20,0x3c,0x06,0x0e == umov w0, v1.h[1] ; Vector Arrangement Specifier: 0x8
|
||||
|
||||
!# issue x86 BND register (OSS-fuzz #13467)
|
||||
!# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL
|
||||
0x0f,0x1a,0x1a == bndldx bnd3, [edx] ; operands[0].type: REG = bnd3
|
||||
|
||||
@ -33,7 +33,7 @@ char *get_detail_arm64(csh *handle, cs_mode mode, cs_insn *ins)
|
||||
add_str(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg));
|
||||
break;
|
||||
case ARM64_OP_IMM:
|
||||
add_str(&result, " ; operands[%u].type: IMM = 0x%" PRIx64 "", i, op->imm);
|
||||
add_str(&result, " ; operands[%u].type: IMM = 0x%" PRIx64, i, op->imm);
|
||||
break;
|
||||
case ARM64_OP_FP:
|
||||
#if defined(_KERNEL_MODE)
|
||||
@ -75,7 +75,7 @@ char *get_detail_arm64(csh *handle, cs_mode mode, cs_insn *ins)
|
||||
add_str(&result, " ; operands[%u].type: BARRIER = 0x%x", i, op->barrier);
|
||||
break;
|
||||
}
|
||||
|
||||
|
||||
access = op->access;
|
||||
switch(access) {
|
||||
default:
|
||||
@ -90,9 +90,11 @@ char *get_detail_arm64(csh *handle, cs_mode mode, cs_insn *ins)
|
||||
add_str(&result, " ; operands[%u].access: READ | WRITE", i);
|
||||
break;
|
||||
}
|
||||
|
||||
if (op->shift.type != ARM64_SFT_INVALID && op->shift.value)
|
||||
add_str(&result, " ; Shift: type = %u, value = %u", op->shift.type, op->shift.value);
|
||||
|
||||
if (op->shift.type != ARM64_SFT_INVALID &&
|
||||
op->shift.value)
|
||||
add_str(&result, " ; Shift: type = %u, value = %u",
|
||||
op->shift.type, op->shift.value);
|
||||
|
||||
if (op->ext != ARM64_EXT_INVALID)
|
||||
add_str(&result, " ; Ext: %u", op->ext);
|
||||
@ -100,9 +102,6 @@ char *get_detail_arm64(csh *handle, cs_mode mode, cs_insn *ins)
|
||||
if (op->vas != ARM64_VAS_INVALID)
|
||||
add_str(&result, " ; Vector Arrangement Specifier: 0x%x", op->vas);
|
||||
|
||||
if (op->vess != ARM64_VESS_INVALID)
|
||||
add_str(&result, " ; Vector Element Size Specifier: %u", op->vess);
|
||||
|
||||
if (op->vector_index != -1)
|
||||
add_str(&result, " ; Vector Index: %u", op->vector_index);
|
||||
}
|
||||
@ -116,14 +115,17 @@ char *get_detail_arm64(csh *handle, cs_mode mode, cs_insn *ins)
|
||||
if (arm64->cc)
|
||||
add_str(&result, " ; Code-condition: %u", arm64->cc);
|
||||
|
||||
if (!cs_regs_access(*handle, ins, regs_read, ®s_read_count, regs_write, ®s_write_count)) {
|
||||
// Print out all registers accessed by this instruction (either implicit or explicit)
|
||||
if (!cs_regs_access(*handle, ins,
|
||||
regs_read, ®s_read_count,
|
||||
regs_write, ®s_write_count)) {
|
||||
if (regs_read_count) {
|
||||
add_str(&result, " ; Registers read:");
|
||||
for(i = 0; i < regs_read_count; i++) {
|
||||
add_str(&result, " %s", cs_reg_name(*handle, regs_read[i]));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
if (regs_write_count) {
|
||||
add_str(&result, " ; Registers modified:");
|
||||
for(i = 0; i < regs_write_count; i++) {
|
||||
|
||||
@ -123,9 +123,6 @@ static void print_insn_detail(cs_insn *ins)
|
||||
if (op->vas != ARM64_VAS_INVALID)
|
||||
printf("\t\t\tVector Arrangement Specifier: 0x%x\n", op->vas);
|
||||
|
||||
if (op->vess != ARM64_VESS_INVALID)
|
||||
printf("\t\t\tVector Element Size Specifier: %u\n", op->vess);
|
||||
|
||||
if (op->vector_index != -1)
|
||||
printf("\t\t\tVector Index: %u\n", op->vector_index);
|
||||
}
|
||||
|
||||
30
utils.c
30
utils.c
@ -137,3 +137,33 @@ bool arr_exist(uint16_t *arr, unsigned char max, unsigned int id)
|
||||
return false;
|
||||
}
|
||||
|
||||
// binary search for encoding in IndexType array
|
||||
// return -1 if not found, or index if found
|
||||
unsigned int binsearch_IndexTypeEncoding(const struct IndexType *index, size_t size, uint16_t encoding)
|
||||
{
|
||||
// binary searching since the index is sorted in encoding order
|
||||
size_t left, right, m;
|
||||
|
||||
right = size - 1;
|
||||
|
||||
if (encoding < index[0].encoding || encoding > index[right].encoding)
|
||||
// not found
|
||||
return -1;
|
||||
|
||||
left = 0;
|
||||
|
||||
while(left <= right) {
|
||||
m = (left + right) / 2;
|
||||
if (encoding == index[m].encoding) {
|
||||
return m;
|
||||
}
|
||||
|
||||
if (encoding < index[m].encoding)
|
||||
right = m - 1;
|
||||
else
|
||||
left = m + 1;
|
||||
}
|
||||
|
||||
// not found
|
||||
return -1;
|
||||
}
|
||||
|
||||
9
utils.h
9
utils.h
@ -68,5 +68,14 @@ bool arr_exist8(unsigned char *arr, unsigned char max, unsigned int id);
|
||||
|
||||
bool arr_exist(uint16_t *arr, unsigned char max, unsigned int id);
|
||||
|
||||
struct IndexType {
|
||||
uint16_t encoding;
|
||||
unsigned index;
|
||||
};
|
||||
|
||||
// binary search for encoding in IndexType array
|
||||
// return -1 if not found, or index if found
|
||||
unsigned int binsearch_IndexTypeEncoding(const struct IndexType *index, size_t size, uint16_t encoding);
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user