* mos65xx: use imm field for immediate operand value
using the wrong field works on little-endian hosts, but on big-endian the wrong value would be read
* mos65xx: set operand mem field to address also in relative modes
previously the last operand would have an offset, which doesn't match the printed operand
* mos65xx: add bpl instruction to test
this demonstrates an address operand with relative addressing
* Fix a few registry access mode mappings
* Fix rollback of operand access changes
Re-fix operand access of three mov instructions
* Remove binding breaking #if 0
The python script for generating constants in the bindings does not know how to handle the #if 0 statements included in these files.
* Add files via upload
Update registry access mode for several versions of pop such as POPDS, POPSS, etc
* Fix a few registry access mode mappings
* Fix rollback of operand access changes
Re-fix operand access of three mov instructions
* Remove binding breaking #if 0
The python script for generating constants in the bindings does not know how to handle the #if 0 statements included in these files.
* Updated registry access on cmov instructions
Registry access for the destination operand of the conditional move (cmov) opcodes were incorrectly listed as READ | WRITE. Although you would expect the two operands to be compared in this opcode, it instead relies on the associated flag in EFLAGS regardless of the value in the destination operand.
* riscv: Fix printAliasInstr
We do not want to append the entire string, only the
single non-argument character.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* riscv: Implement printCSRSystemRegister
While upstream LLVM probably has a tablegen thing for these
somewhere, the current import doesn't include them. Take the
list from riscv-privileged-v1.10.pdf.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* update const generator for swift
* groups constants by enum
* use pascal case for enum names
* use camel case for enum values
* values are always literals
* add extra options for some enums
* use different types for some enums
* generate option sets instead of enums for some types
* renaming constants according to regex pattern
* don't output documentation comments for non-exported defines
* add Swift binding to readme
* RISCV: Check CS_MODE_RISCVC in getFeatureBits
Enable compressed instruction extension with RISCVC.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* RISCV: Fix skipdata_size for CS_MODE_RISCVC
RISC-V compressed instructions are 2 bytes, not 1.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
if integer is 32-bit, and numeric literals default to int type,
the following applies (from The C Standard, 6.5.7, paragraph 4
[ISO/IEC 9899:2011]):
If E1 has a signed type and nonnegative value, and E1 × 2^E2 is
representable in the result type, then that is the resulting value;
otherwise, the behavior is undefined.
which means that the only way to safely shift is unsigned, so
use 1U to indicate the shifted bit is unsigned.
On x86_64-linux gentoo system capstone was installing
it's files to 'lib64' libdir, but was referring 'lib' libdir:
```
$ cat /usr/lib64/pkgconfig/capstone.pc
...
libdir=${prefix}/lib
...
```
On radare2 built it means injecting -L/usr/lib into a 64-build
and pulling in 32-bit libraries. 'ld.lld' is not able to resolve
the ambiguity.
It happens because @LIBSUFFIX@ is not present in cmake-3.17.3.
Let's fix the paths by using @CMAKE_INSTALL_LIBDIR@.
This variable is already used in capstone's build system,
thus should be safe to rely on.
Reported-by: Agostino Sarubbo
Bug: https://bugs.gentoo.org/730722
Signed-off-by: Sergei Trofimovich <slyfox@gentoo.org>
This commit adds some registers to the list of implicit used registers and
implicit modified registers for several AArch64 instructions.
This commit also maps the `ARM64_GRP_CALL` group to the BL* instruction family.
It should fix issue #1606.
* Add __repr__ for capstone.CsInsn
Currently, a `print(instruction)` displays a not very useful string like `<capstone.CsInsn object at 0x7f3759d88128>`.
This PR enhances adds a `__repr__` magic method to the `capstone.CsInsn` class so it displays as follows:
```
<cs.CsInsn: address=0x5555555545fa, size=1, mnemonic=push, op_str=rbp>
```
* Update __init__.py
