Nguyen Anh Quynh
8c7cbaf415
x86: operand access for BND instructions
2019-03-04 16:12:56 +08:00
Nguyen Anh Quynh
f2233b7f44
x86: new files X86GenRegisterName.inc & X86GenRegisterName1.inc
2019-03-04 00:56:07 +08:00
Đỗ Minh Tuấn
5812414b2a
normalize in issue mode ( #1414 )
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* normalize tab character in cs
* normalize in issue mode
2019-03-03 19:10:55 +08:00
Đỗ Minh Tuấn
2fbc238e85
normalize tab character in cs ( #1413 )
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* normalize tab character in cs
2019-03-03 18:09:20 +08:00
Travis Finkenauer
31d0de4552
[M68K] store correct register value in op.reg_pair ( #1411 )
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* m68k: store correct m68k_reg value in op.reg_pair
Originally, value - M68K_REG_D0 was stored and the print logic added
M68K_REG_D0.
* m68k: fix license typo
2019-03-02 17:40:29 +08:00
Nguyen Anh Quynh
7e1efae487
x86: remove PRINT_ALIAS_INSTR
2019-03-02 15:32:07 +08:00
Nguyen Anh Quynh
cb2b1bda53
x86: add BND registers to regsize_map_32 & regsize_map_64
2019-03-02 15:16:48 +08:00
Nguyen Anh Quynh
9058367c07
fuzz_disasm: declare cs_fuzz_arch()
2019-03-02 15:07:28 +08:00
Nguyen Anh Quynh
ee237e128a
bingdings: update X86 consts
2019-03-02 14:59:16 +08:00
Nguyen Anh Quynh
3dd39b0bc5
x86: add BND registers. this fixes OSS-fuzz issue 13467
2019-03-02 14:58:29 +08:00
Daniel Collin
9f53e3b0d4
Made instruction table static ( #1408 )
2019-03-02 10:53:30 +08:00
Catena cyber
1f0ff5e437
Fuzz more modes and ATT syntax ( #1410 )
2019-03-02 10:52:09 +08:00
Alexey Nurmukhametov
91f6189f97
cstest: add issue #1263 ( #1407 )
2019-03-01 18:08:21 +08:00
Nguyen Anh Quynh
21ee872b85
cmake: update HEADERS_X86
2019-03-01 12:54:08 +08:00
z
6eaf37cf87
fix SystemZRegDesc&SystemZMCRegisterClasses number of SystemZ InitMCRegisterInfo ( #1405 )
2019-03-01 09:55:11 +08:00
Stephen
228c733950
add xenial tests ( #1404 )
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* add xenial tests
* add cmocka remove reminder
2019-03-01 09:55:02 +08:00
Nguyen Anh Quynh
b7ed33a1a0
Merge branch 'next' of github.com:aquynh/capstone into next
2019-03-01 01:12:50 +08:00
Nguyen Anh Quynh
0e3dc97fd9
Merge branch 'next-x86' into next
2019-03-01 01:12:32 +08:00
Nguyen Anh Quynh
2dc77357e1
x86: update ISA & mapping tables
2019-03-01 01:05:52 +08:00
Nguyen Anh Quynh
650b26e324
cstest: add 1 more test for #1335
2019-02-28 08:03:12 +08:00
Nguyen Anh Quynh
16f70fc354
cstest: add issue #1335
2019-02-28 08:01:23 +08:00
Nguyen Anh Quynh
ac311fd7f6
cstest: add issue #1259
2019-02-28 07:57:58 +08:00
Sebastian Macke
6ba9f001b9
MOS65XX: Fix instruction length for indirect addressing modes ( #1402 )
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Signed-off-by: Sebastian Macke <sebastian@macke.de>
2019-02-28 07:39:59 +08:00
Nguyen Anh Quynh
3e624c0e02
sync cs.c
2019-02-28 06:14:50 +08:00
Philippe Antoine
e3bcb06681
Make travis print the fuzzed input to be used with cstool
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Adds architectures and modes to cstool as well
2019-02-28 00:59:33 +08:00
Nguyen Anh Quynh
2defd57568
bindings: update X86 consts
2019-02-27 23:04:14 +08:00
Nguyen Anh Quynh
357ef8e535
x86: X86_insn_name checks array boundary with ARR_SIZE
2019-02-27 00:19:43 +08:00
Nguyen Anh Quynh
49d46e6a52
x86: optimize X86MappingInsnName.inc to have only instruction names
2019-02-26 23:47:05 +08:00
Nguyen Anh Quynh
1d8a1eeca1
MC: uncomment some valid AVX testcases of X86
2019-02-26 23:05:10 +08:00
Nguyen Anh Quynh
9836779db9
x64: fix binary searching functions in arch/X86/X86Mapping.c
2019-02-26 22:59:52 +08:00
Nguyen Anh Quynh
1e82cc5b36
x86: fix issue #1304
2019-02-26 22:16:39 +08:00
Nguyen Anh Quynh
7c9090e542
Makefile: indentation
2019-02-26 21:51:30 +08:00
Đỗ Minh Tuấn
51a03d6108
fix mode "c" in report_cstest ( #1398 )
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* fix mode "c" in report_cstest
2019-02-26 21:45:48 +08:00
Nguyen Anh Quynh
c829a8bfd4
x86: fix is64Bit(), so it access insns array after ID lookup
2019-02-26 16:31:02 +08:00
Nguyen Anh Quynh
7c0b7efc27
sync cs.c
2019-02-26 15:52:11 +08:00
Nguyen Anh Quynh
4de2e288c8
fix MC
2019-02-26 15:41:04 +08:00
Nguyen Anh Quynh
3dcdcfa713
sync with LLVM 7.0.1. X86 is first
2019-02-26 15:19:51 +08:00
Nguyen Anh Quynh
17f252ea96
x86: ENDBR64 & ENDBR32 are unavailable in REDUCE mode
2019-02-23 00:02:09 +08:00
Nguyen Anh Quynh
b227825267
x86: fix X86_BEXTRI64ri in X86MappingInsnOp_reduce.inc
2019-02-22 23:58:33 +08:00
Nguyen Anh Quynh
260bc7e44f
trimming MCInstrDesc (ARM)
2019-02-21 23:30:38 +08:00
Nguyen Anh Quynh
de420ec49a
trimming MCRegisterClass
2019-02-21 22:33:15 +08:00
Nguyen Anh Quynh
7131b7a8ad
Revert "x86: trimming MCRegisterClass usage"
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This reverts commit 1d71b36348447545d5f2aa13f0325ff23fb6b37a.
2019-02-21 21:11:56 +08:00
Nguyen Anh Quynh
8b1a140db2
x86: trimming MCRegisterClass usage
2019-02-21 21:08:00 +08:00
Nguyen Anh Quynh
e0b9ca7329
Revert "trimming MCRegisterClass usage"
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This reverts commit 86743f83cdb40338d840a646b288fad31511ff75.
2019-02-21 21:06:01 +08:00
Nguyen Anh Quynh
9426405822
trimming MCRegisterClass usage
2019-02-21 20:55:25 +08:00
Nguyen Anh Quynh
38e9716275
wasm: remove unused variable
2019-02-21 20:52:59 +08:00
Nguyen Anh Quynh
f59dac2237
Merge branch 'next' of github.com:aquynh/capstone into next
2019-02-21 15:33:54 +08:00
Nguyen Anh Quynh
85cac968ef
X86: X86_insn_reg_att uses a wrong mapping array of Intel syntax
2019-02-21 15:33:14 +08:00
Catena cyber
5f20fba9de
Adds corpus generation for bpf architecture ( #1396 )
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* Adds corpus generation for bpf architecture
* Updes HACK.txt with MC files to be added with a new architecture
2019-02-21 10:42:31 +08:00
Catena cyber
e5fa5f8735
Avoids leak in wasm details ( #1372 )
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* Avoids leak in wasm details
Extending cs_detail in capstone.h
* Safety checks before allocating memory for brtable in WASM
* Revert "Avoids leak in wasm details"
This reverts commit 03f822b34a03f23554aaffb2951b62c62645e5e5.
* Refactoring brtable for WASM
* Fix undefined shift in WASM get_varuint64
2019-02-20 23:38:11 +08:00
