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303 Commits

Author SHA1 Message Date
Nguyen Anh Quynh
93a007dc0e m68k: fix prototype guard for m68k.h 2015-10-04 14:52:38 +08:00
Nguyen Anh Quynh
ac63d5b995 m68k: cleanup & code style 2015-10-04 14:34:51 +08:00
Daniel Collin
2ee675c10a This adds M68K support to Capstone 2015-10-02 20:47:00 +02:00
pancake
8848ea3f68 Fix build for cygwin 2015-09-22 16:33:27 +02:00
Nguyen Anh Quynh
8aba4cd913 add error code CS_ERR_X86_MASM 2015-08-09 10:52:18 -07:00
Nguyen Anh Quynh
62918abb60 support new syntax CS_OPT_SYNTAX_MASM for X86 2015-08-09 10:34:19 -07:00
Zach Riggle
1e882cf542 Add ARM64_GRP_INT to AArch64 for SVC instruction 2015-07-27 12:42:06 -04:00
Gabriel Corona
8102aacfda Make PowerPC imm 64 bit (instad 32 bit) 2015-05-14 23:16:55 +02:00
Nguyen Anh Quynh
c85a0e4f44 arm: correct value of ARM_GRP_INT (=CS_GRP_INT=4) 2015-05-08 23:54:37 +08:00
derrek
01a744c329 arm: Added instruction group ARM_GRP_INT, ARM_INS_SVC is now using it. 2015-05-08 13:08:55 +02:00
derrek
2dbe2e6847 Merge branch 'next' of https://github.com/aquynh/capstone into next 2015-05-08 13:04:15 +02:00
Taras Tsugrii
a5199bd0ce Fix spelling nits 2015-05-06 06:05:35 +08:00
Nguyen Anh Quynh
bbde6d5c63 python: support option CS_OPT_MNEMONIC 2015-04-27 11:34:44 +08:00
Nguyen Anh Quynh
de654dd238 rename MNEMONIC_SIZE to CS_MNEMONIC_SIZE 2015-04-27 09:47:59 +08:00
Nguyen Anh Quynh
1b26a3c530 bump CS_NEXT_VERSION to 3 due to newly added option CS_OPT_MNEMONIC 2015-04-26 22:55:18 +08:00
Nguyen Anh Quynh
0b96545f66 new option CS_OPT_MNEMONIC to customize instruction mnemonic 2015-04-26 22:54:41 +08:00
mrexodia
31e8c0bf75 Update capstone.h 2015-04-24 22:56:55 +02:00
derrek
67aee91887 arm: Changed CS_GRP_ prefix to ARM_GRP_ prefix, added ARM_GRP_CALL group. 2015-04-23 12:15:04 +02:00
Vincent Bénony
b5e0f13cb0 Merge branch 'next' of https://github.com/aquynh/capstone into next 2015-04-17 11:43:15 +02:00
Vincent Bénony
d2f47d065f Remove enum for ASRS, LSRS, SUBS and MOVS 
These instructions are now disassembled ASR, LSR, SUB and MOV, with the "update_flags" bit set.
 2015-04-17 11:42:45 +02:00
Vincent Bénony
68d7f723da remove some variants 2015-04-17 11:25:23 +02:00
Nguyen Anh Quynh
de693e48e1 delete a trailing whitespace in x86.h 2015-04-16 21:49:56 +08:00
remittor
556f4fe41a [x86] Replace "enum x86_eflags_type" to #define 
Needed for compatible with MS VS 2008 compiler.
 2015-04-15 13:15:53 +03:00
remittor
3a75479a65 Changed type for segment,base,index in struct x86_op_mem 2015-04-15 13:09:46 +03:00
remittor
68e948b2c1 Changed type for cs_x86_op.reg 
Fixed type for cs_x86_op reg to be a x86_reg instead of unsigned int.  This makes it easier to understand that reg is a x86_reg enumeration versus something else.  It is currently not clear which type reg is.
 2015-04-15 13:04:39 +03:00
reverser
160e198584 Add support to embed Capstone 3.x branch into OS X kernel extensions. 2015-04-09 18:28:19 +01:00
Nguyen Anh Quynh
fa17d871f1 remove stdio.h from capstone.h. this is to make it possible to embed to OSX kernel. issue reported by Pedro 2015-04-09 22:56:15 +08:00
Nguyen Anh Quynh
29f777bdd9 arm: support cs_regs_access() API 2015-04-07 11:59:26 +08:00
Nguyen Anh Quynh
53ccc2cf38 bump CS_NEXT_VERSION up due to the newly added API cs_regs_access() 2015-03-25 15:23:58 +08:00
Nguyen Anh Quynh
efffe787d1 Add new API and start to provide access information for instruction operands 
- New API cs_regs_access() that provide registers being read & modified by instruction

- New field cs_x86_op.access provides access info (READ, WRITE) for each operand

- New field cs_x86.eflags provides EFLAGS affected by instruction

- Extend cs_detail.{regs_read, regs_write} from uint8_t to uint16_t type
 2015-03-25 15:02:13 +08:00
David Callahan
9092e5295f Change AArch64 GRP_JUMP to use a static table implementation 
Added support for GRP_CALL and GRP_RETURN to AArch64
 2015-03-15 18:01:48 -07:00
Nguyen Anh Quynh
21bf9cee90 Merge branch 'next' of https://github.com/aquynh/capstone into next 2015-03-12 18:17:24 +08:00
Nguyen Anh Quynh
681070ccf4 Merge pull request #279 from radare/arm64-priv 
add ARM64_GRP_PRIVILEGE group and tag some instructions
 2015-03-12 17:42:14 +08:00
Nguyen Anh Quynh
b8ffb86b02 ppc: fix a bug in QPX mode & add some QPX alias instructions. 2015-03-12 16:52:31 +08:00
pancake
a089e1445c Fix ARM64_GRP_PRIVILEGE 2015-03-11 03:31:30 +01:00
pancake
307973f2b1 Fix ARM_GRP_PRIVILEGE 2015-03-11 03:30:42 +01:00
pancake
dae7c3ee9f add ARM64_GRP_PRIVILEGE group and tag some instructions 2015-03-11 00:23:22 +01:00
pancake
cf74a14b43 add ARM_GRP_PRIVILEGE group and tag some instructions 2015-03-11 00:13:53 +01:00
Nguyen Anh Quynh
bf97e21bb5 core: add CS_NEXT_VERSION to version the latest code in the 'next' branch 2015-03-09 10:11:06 +08:00
Nguyen Anh Quynh
4dd0dcb9d4 add CS_GRP_PRIVILEGE group, and also add X86_GRP_PRIVILEGE group for bunch of X86 privileged instructions 2015-03-09 00:04:45 +08:00
Nguyen Anh Quynh
e4ca35d561 x86: delete the fiction instruction X86_INS_VPCOM 2015-03-07 16:05:06 +08:00
Nguyen Anh Quynh
7a94483452 x86: remove another fiction instruction VCMP 2015-03-07 14:37:59 +08:00
Nguyen Anh Quynh
e402e021b8 x86: remove unreal instruction VPCMP 2015-03-07 14:33:40 +08:00
Nguyen Anh Quynh
a81bf4247c x86: add new field @xop_cc to struct @cs_x86 2015-03-07 13:37:32 +08:00
Nguyen Anh Quynh
ad42f16b14 mips: remove the confusing mode CS_MODE_MIPSGP64 2015-03-07 00:48:06 +08:00
Nguyen Anh Quynh
54d5071288 x86: update core. also update all the bindings Java, Ocaml & Python 2015-03-06 00:52:49 +08:00
Nguyen Anh Quynh
bfcaba5851 2015 2015-03-04 17:45:23 +08:00
Nguyen Anh Quynh
0be9eab6ba ppc: update core 2015-03-04 17:06:48 +08:00
Nguyen Anh Quynh
7e25609ad3 arm: fix bugs in the last commit 2015-03-03 18:28:10 +08:00
Nguyen Anh Quynh
d1fc2bd3b9 arm: update core 2015-03-03 16:26:32 +08:00