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Author SHA1 Message Date
Nguyen Anh Quynh
e95a76611c x86: remove some instructions unsupported in 3.x version 2015-01-13 14:35:43 +08:00
Nguyen Anh Quynh
273c6f4a9e arm64 & sparc: fix some warnings reported by MSVC 2015-01-13 14:33:09 +08:00
Nguyen Anh Quynh
9a1238d353 suite: fix an compilation warning reported by MSVC on test_arm_regression.c 2015-01-13 14:21:15 +08:00
Nguyen Anh Quynh
25525fb20c x86: remove some instructions irrelevant for LOCK prefix in invalidPrefix() 2015-01-13 12:14:46 +08:00
Nguyen Anh Quynh
08482e106d x86: remove some instructions irrelevant for LOCK prefix in invalidPrefix() 2015-01-13 12:14:19 +08:00
Nguyen Anh Quynh
7de172d6ec x86: properly handle REP, REPNE & REPNZ prefixes 2015-01-13 12:04:19 +08:00
Andrew Wesie
29f41da4c2 x86: add more valid instructions for LOCK prefix 2015-01-13 12:04:12 +08:00
Nguyen Anh Quynh
5323128ed2 x86: check for invalid instructions with LOCK prefix 2015-01-13 12:04:02 +08:00
Nguyen Anh Quynh
b3e26fdaa6 x86: add prefix constant REPE 2015-01-13 12:03:15 +08:00
Nguyen Anh Quynh
a176ba4447 x86: properly handle REP, REPNE & REPNZ prefixes 2015-01-13 11:59:00 +08:00
Nguyen Anh Quynh
18dfc1929d Merge branch 'v3' of https://github.com/aquynh/capstone into v3 2015-01-13 10:41:45 +08:00
Nguyen Anh Quynh
0c30daf749 arm64: BL & BLR do not read SP register 2015-01-13 10:41:18 +08:00
Nguyen Anh Quynh
c6cf01c256 arm64: BL & BLR do not read SP register 2015-01-13 10:40:59 +08:00
Nguyen Anh Quynh
993e031795 java & ocaml: update these bindings following the addition of lshift field to arm_op_mem of Arm engine 2015-01-12 16:01:26 +08:00
Nguyen Anh Quynh
6c34c6659b tests: update test_arm.c to add a sample reflecting the addition of lshift field on arm_op_mem 2015-01-12 15:38:06 +08:00
Nguyen Anh Quynh
2951e640a4 Merge branch 'next' of https://github.com/aquynh/capstone into next 2015-01-12 15:28:22 +08:00
Nguyen Anh Quynh
590b1de14b python: update Python binding for ARM after the latest change in the core 2015-01-12 15:28:03 +08:00
Nguyen Anh Quynh
706b808af3 arm: add lshift field to arm_op_mem to provide left-shift value for index register in some memory op. issue reported by @jabba2989 2015-01-12 15:27:29 +08:00
Nguyen Anh Quynh
78d640045c cython: fix incomplete array of bytes returned by CsInsn.bytes. bug reported by @secretsquirrel 2015-01-07 22:08:35 +08:00
Nguyen Anh Quynh
4de9de683d cython: fix incomplete array of bytes returned by CsInsn.bytes. bug reported by @secretsquirrel 2015-01-07 22:07:42 +08:00
Nguyen Anh Quynh
499f0ca7cb suite: add some tools to verify X86 machine code 2015-01-06 13:11:04 +07:00
Nguyen Anh Quynh
0653c4edb1 Merge pull request #245 from awesie/next 
x86: add more valid instructions for LOCK prefix
 2015-01-06 07:31:12 +07:00
Andrew Wesie
5de09479a6 x86: add more valid instructions for LOCK prefix 2015-01-05 18:26:41 -06:00
Nguyen Anh Quynh
beb3248c26 x86: check for invalid instructions with LOCK prefix 2015-01-05 22:18:00 +07:00
Nguyen Anh Quynh
4539ba3088 x86: support MOVSXD64rm with missing REX byte. bug reported by Aurélien Wailly 2015-01-03 23:43:14 +08:00
Nguyen Anh Quynh
599b559455 x86: fix some compilation issues about missing instructions on CAPSTONE_X86_REDUCE setup 2014-12-31 10:42:16 +08:00
Maciej Szawlowski
2c24d88f89 fixed bug that prevented using md.detail = true and md.skipdata = true together 2014-12-31 10:33:05 +08:00
Nguyen Anh Quynh
dc101c25b3 Merge branch 'master' of https://github.com/mszawlow/capstone into next 2014-12-31 10:32:12 +08:00
Maciej Szawlowski
9b0221f229 fixed bug that prevented using md.detail = true and md.skipdata = true together 2014-12-30 22:37:04 +01:00
Nguyen Anh Quynh
3c27827a25 x86: handle 0x82 opcode for CAPSTONE_X86_REDUCE setup 2014-12-30 15:43:19 +08:00
Nguyen Anh Quynh
3410b63a4e x86: handle 0x82 opcode. bug reported by Anton Kochkov 2014-12-30 13:16:44 +08:00
derrek
07526e989b arm: Thumb BL & BLX read ARM_REG_PC instead of ARM_REG_SP. 2014-12-30 10:47:04 +08:00
Nguyen Anh Quynh
828667f3b3 Merge pull request #240 from derrekr/next 
arm: Thumb BL & BLX read ARM_REG_PC instead of ARM_REG_SP.
 2014-12-30 10:45:04 +08:00
derrek
bda2c1c591 arm: Thumb BL & BLX read ARM_REG_PC instead of ARM_REG_SP. 2014-12-29 17:20:19 +01:00
Nguyen Anh Quynh
c51e04fa97 x86: support CR9-CR15 registers 3.0.1-rc1 2014-12-27 23:56:14 +08:00
Nguyen Anh Quynh
08390775b5 x86: support CR9-CR15 registers 2014-12-27 23:55:08 +08:00
Nguyen Anh Quynh
db684b2398 arm: BL & BLX do not read SP, but PC register. issue reported by Der Rek 2014-12-27 16:26:42 +08:00
Nguyen Anh Quynh
0f9ef1559d arm: BL & BLX do not read SP, but PC register. issue reported by Der Rek 2014-12-27 16:16:12 +08:00
Nguyen Anh Quynh
61ab00718a x86: remove dead code & dead SSE_CC constants. issue reported by Coverity 2014-12-27 15:42:13 +08:00
Nguyen Anh Quynh
1038fdb038 x86: add new registers DR8-DR15 2014-12-27 15:33:12 +08:00
Nguyen Anh Quynh
59c72afe7a x86: add 3 new undocumented instructions fdisi8087_nop, feni8087_nop & ffreep 2014-12-26 23:59:35 +08:00
Nguyen Anh Quynh
534b948661 bump version to 4.0 2014-12-26 23:14:53 +08:00
Nguyen Anh Quynh
7ca66a4982 bump package version to 3.0.1 2014-12-26 21:32:40 +08:00
Nguyen Anh Quynh
9f694cc934 x86: handle undocumented immediates for (v)cmpps/pd/ss/sd instructions 2014-12-26 17:54:11 +08:00
Nguyen Anh Quynh
d319c114db x86: more encodings for FXCH & FCOMP. also print LJUMP without * as prefix for Intel syntax. handle BOUND & FARCALL better 2014-12-26 16:49:10 +08:00
Nguyen Anh Quynh
5f8c4239c2 x86: add missing CR8-CR15 registers to arch/X86/X86DisassemblerDecoder.h 2014-12-25 01:12:56 +08:00
Nguyen Anh Quynh
2ac7941227 x86: handle REX properly for segment related instructions by ignoring REX.r entirely 2014-12-24 16:16:51 +08:00
Nguyen Anh Quynh
80959c9a25 code style 2014-12-24 16:03:10 +08:00
Nguyen Anh Quynh
094811415c x86: handle REX properly for x64 MMX related instructions by ignoring REX.b & REX.w entirely 2014-12-24 16:02:44 +08:00
Nguyen Anh Quynh
c9c3fdc3c9 arm64: print ADR with absolute address. bug reported by blackboxer123 2014-12-23 15:30:40 +08:00