* Added new M680X target. Supports M6800/1/2/3/9, HD6301
* M680X: Reformat for coding guide lines. Set alphabetical order in HACK.TXT
* M680X: Prepare for python binding. Move cs_m680x, m680x_insn to m680x_info. Chec
> k cpu type, no default.
* M680X: Add python bindings. Added python tests.
* M680X: Added cpu types to usage message.
* cstool: Avoid segfault for invalid <arch+mode>.
* Make test_m680x.c/test_m680x.py output comparable (diff params: -bu). Keep xprint.py untouched.
* M680X: Update CMake/make for m680x support. Update .gitignore.
* M680X: Reduce compiler warnings.
* M680X: Reduce compiler warnings.
* M680X: Reduce compiler warnings.
* M680X: Make test_m680x.c/test_m680x.py output comparable (diff params: -bu).
* M680X: Add ocaml bindings and tests.
* M680X: Add java bindings and tests.
* M680X: Added tests for all indexed addressing modes. C/Python/Ocaml
* M680X: Naming, use page1 for PAGE1 instructions (without prefix).
* M680X: Naming, use page1 for PAGE1 instructions (without prefix).
* M680X: Used M680X_FIRST_OP_IN_MNEM in tests C/python/java/ocaml.
* M680X: Added access property to cs_m680x_op.
* M680X: Added operand size.
* M680X: Remove compiler warnings.
* M680X: Added READ/WRITE access property per operator.
* M680X: Make reg_inherent_hdlr independent of CPU type.
* M680X: Add HD6309 support + bug fixes
* M680X: Remove errors and warning.
* M680X: Add Bcc/LBcc to group BRAREL (relative branch).
* M680X: Add group JUMP to BVS/BVC/LBVS/LBVC. Remove BRAREL from BRN/LBRN.
* M680X: Remove LBRN from group BRAREL.
* M680X: Refactored cpu_type initialization for better readability.
* M680X: Add two operands for insn having two reg. in mnemonic. e.g. ABX.
* M680X: Remove typo in cstool.c
* M680X: Some format improvements in changed_regs.
* M680X: Remove insn id string list from tests (C/python/java/ocaml).
* M680X: SEXW, set access of reg. D to WRITE.
* M680X: Sort changed_regs in increasing m680x_insn order.
* M680X: Add M68HC11 support + Reduced from two to one INDEXED operand.
* M680X: cstool, also write '(in mnemonic)' for second reg. operand.
* M680X: Add BRN/LBRN to group JUMP and BRAREL.
* M680X: For Bcc/LBcc/BRSET/BRCLR set reg. CC to read access.
* M680X: Correctly print negative immediate values with option CS_OPT_UNSIGNED.
* M680X: Rename some instruction handlers.
* M680X: Add M68HC05 support.
* M680X: Dont print prefix '<' for direct addr. mode.
* M680X: Add M68HC08 support + resorted tables + bug fixes.
* M680X: Add Freescale HCS08 support.
* M680X: Changed group names, avoid spaces.
* M680X: Refactoring, rename addessing mode handlers.
* M680X: indexed addr. mode, changed pre/post inc-/decrement representation.
* M680X: Rename some M6809/HD6309 specific functions.
* M680X: Add CPU12 (68HC12/HCS12) support.
* M680X: Correctly display illegal instruction as FCB .
* M680X: bugfix: BRA/BRN/BSR/LBRA/LBRN/LBSR does not read CC reg.
* M680X: bugfix: Correctly check for sufficient code size for M6809 indexed addressing.
* M680X: Better support for changing insn id within handler for addessing mode.
* M680X: Remove warnings.
* M680X: In set_changed_regs_read_write_counts use own access_mode.
* M680X: Split cpu specific tables into separate *.inc files.
* M680X: Remove warnings.
* M680X: Removed address_mode. Addressing mode is available in operand.type
* M680X: Bugfix: BSET/BCLR/BRSET/BRCLR correct read/modify CC reg.
* M680X: Remove register TMP1. It is first visible in CPU12X.
* M680X: Performance improvement + bug fixes.
* M680X: Performance improvement, make cpu_tables const static.
* M680X: Simplify operand decoding by using two handlers.
* M680X: Replace M680X_OP_INDEX by M680X_OP_CONSTANT + bugfix in java/python/ocaml bindings.
* M680X: Format with astyle.
* M680X: Update documentation.
* M680X: Corrected author for m680x specific files.
* M680X: Make max. number of architectures single source.
This is one of those “how did this ever work?” changes. Problem was that as m68k_op was aliased with the imm value so when changing that to something big it would trash the values in the mem struct which would make things go really bad.
Now m68k_op_mem has been moved out of the union so this will not happen again. Also fixed instruction printing bug related to this (just happend to “work” due to the old union layout)
* fixed hardcoded paths with variables.
cmake pkg-config file fixed hardcoded paths with variables. CMakeLists.txt line 394 needs to be modified
> configure_file("capstone.pc.in" "capstone.pc" @ONLY)
* forgot to add 64bit support variable.
* Add a new group for relative branching instructions
* x86: Add relative branch group to appropiate instructions
* Rename RELATIVE_BRANCH to BRANCH_RELATIVE
* aarch64: Add relative branch group to appropiate instructions
* arm: Add relative branch group to appropiate instructions
* m68k: Add relative branch group to appropiate instructions
* mips: Add relative branch group to appropiate instructions
The correct compiler was not being passed to cstool/Makefile. The expected name
for the capstone lib was also incorrect - there is no "lib" prefix when
compiling with mingw.
* Add FPUFLAGS information.
* Change the structure insn_op: from uint64_t eflags to union{ uint64_t eflags, uint64_t fpuflags; }.
* Adjust the modified structure insn_op.
* Add missing flags.
* Change flags information acorrding to xed files and instruction manual.
* Rename fpuflags to fpu_flags.
* Updating flags information accoring to manual and xed files.
* Changing the name eflags to flags.
* Printing the FPU_FLAGS information when it belongs to group X86_GRP_FPU.
* Defining new flags.
* Updating flags information according to manual and xed files.
* Adding X86_GRP_FPU to all the instructions which have modified fpu_flags.
* Solving the conflict problem when do git commit.
* Rectify the annotation within the structure insn_op.
* Supplement fpu flags information for floating-point instructions which missed fpu flags before.
* Print fpu group information when an instructure belongs to X86_GRP_FPU.
* Add two new groups ARM64_GRP_BASE(base instructions) and ARM64_GRP_FPSIMD(SIMD&FP instructions).
* Revert "Add two new groups ARM64_GRP_BASE(base instructions) and ARM64_GRP_FPSIMD(SIMD&FP instructions)."
This reverts commit 8ab50e80a3.
* X86 clean up.
* Clean up arch/X86/X86MappingInsn.inc.
* Double check.
* Delete files.
* Clean up x86.
* Clean up reduce file
* Fix btr
* fix x86
