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2,129 Commits 13 Branches 41 Tags 106 MiB
e5aa75131b
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630 Commits

Author SHA1 Message Date
Nguyen Anh Quynh
e5aa75131b x86: treat prefix-only sequences of bytes as invalid code. this fixes a NDP reported by @felixgr 2015-06-16 11:57:45 +08:00
Nguyen Anh Quynh
fb18a93f73 ppc: avoid potential memleak issue when alias mnemonic is empty in PPC_printInst() 2015-06-06 19:11:25 +08:00
Nguyen Anh Quynh
5cb356061e ppc: make sure alias mnememonic is not empty in PPC_printInst() 2015-06-06 16:10:07 +08:00
Nguyen Anh Quynh
aa7c6cd6ce xcore: increase op_count in set_mem_access() only on register operand. bug reported by Ben Nagy 2015-06-06 12:30:56 +08:00
Nguyen Anh Quynh
e39f9e1ab9 x86: properly handle AL/AX/EAX operand of OUT instruction in AT&T syntax 2015-06-06 00:32:42 +08:00
Nguyen Anh Quynh
743832a80f x86: some algorithm instructions with immediate of 1 byte should be printed in positive form 2015-06-06 00:04:03 +08:00
Nguyen Anh Quynh
b0a1832d2d xcore: turn off doing_mem after each printing each instruction. this fixes a memory corruption reported by @felixgr 2015-06-05 18:06:22 +08:00
Nguyen Anh Quynh
c0bf7f6e48 x86: revert the old change that check prefix location more strictly 2015-06-04 21:30:15 +08:00
Nikolay Igotti
1bcb7d6cc6 Fix Thumb disassembler memory corruption with IT sequence (issue #385) 2015-06-03 15:38:45 +02:00
Nguyen Anh Quynh
b1d12e50d4 arm: fix an warning on conversion from uint64_t to bool. issue reported by @yegord 2015-05-24 21:33:17 +08:00
Nguyen Anh Quynh
5c48bb22f9 arm: remove ASRS, LSRS, SUBS & MOVS from mapping table insns[]. backported from the 'next' branch, but do not really remove these 'dead' instructions for compatibility reason 2015-05-08 15:08:35 +08:00
Nguyen Anh Quynh
accd198468 arm: BLX should read PC & modify LR registers. bug reported by Zach Riggle 2015-05-08 15:04:09 +08:00
Nguyen Anh Quynh
c52d8cd7d3 x86: make all shifted instructions to support first operand in AT&T syntax 2015-05-08 14:23:08 +08:00
Ole André Vadla Ravnås
2ac028681c Fix handling of cmpxchg16b with lock prefix 
This was discovered when Frida's Stalker encountered the following
x86-64 instruction while tracing code in ntdll: `f0 49 0f c7 0a`.
 2015-04-23 20:44:21 +08:00
learn_more
a129475a26 Fix compiling with nmake 2015-04-14 15:36:10 +02:00
Nguyen Anh Quynh
b2c6fd566c Merge pull request #311 from jpenalbae/sparc-branchfix 
Sparc conditional branches displacement fix
 2015-04-13 22:21:53 +08:00
NighterMan
b01881b432 Improved displacement decoding for sparc banching instructions 2015-04-11 04:55:16 +02:00
reverser
cf6201419a Add support to embed Capstone into OS X kernel extensions. 2015-04-10 23:28:12 +08:00
NighterMan
32a0ab7f50 Sparc conditional branches displacement fix 2015-04-10 04:47:42 +02:00
Nguyen Anh Quynh
52ef895d53 x86: tighter check on return of consumeByte() & lookAtByte(). this fixes the segfault on the sole input of 0xf3 reported by windhl 2015-04-08 12:18:33 +08:00
Nguyen Anh Quynh
1739ecc651 x86: tighter check on return of consumeByte() & lookAtByte(). this fixes the segfault on the sole input of 0xf3 reported by windhl 2015-04-08 12:18:27 +08:00
Nguyen Anh Quynh
4504dcdc48 Merge branch 'master' into v3 2015-04-07 13:21:56 +08:00
Nguyen Anh Quynh
e1bde17b6b x86: fix instruction 66f20f59ff reported by @maijin 2015-04-02 12:44:23 +08:00
Nguyen Anh Quynh
3cd999f631 x86: fix the pause instruction reported by @maijin in issue #298 2015-04-02 12:44:11 +08:00
Cr4sh
9d60607645 inttypes.h fix 2015-03-29 18:29:06 +08:00
Nguyen Anh Quynh
2cdd422d70 x86: fix Immediate operand size when first register operand is embedded in mnemonic (CMP8i8). bug reported by @joelpx 2015-03-14 10:18:12 +08:00
Nguyen Anh Quynh
93d7dfa6ba x86: fix Immediate operand size when first register operand is embedded in mnemonic (CMP8i8). bug reported by @joelpx 2015-03-14 10:17:48 +08:00
Nguyen Anh Quynh
97447d1fda Merge branch 'v3' of https://github.com/aquynh/capstone into v3 2015-03-11 11:16:33 +08:00
Nguyen Anh Quynh
d50dcc5384 x86: F2 can be a part of instruction encoding, but not a prefix 2015-03-11 11:16:04 +08:00
Nguyen Anh Quynh
726ade0c8d arm: more optimization on MCInstrDesc struct to reduce the library size by further 20KB 2015-03-10 17:30:26 +08:00
Nguyen Anh Quynh
e220b503f1 arm: rever the change on OperandInfo* in the last commit 2015-03-10 16:45:15 +08:00
Nguyen Anh Quynh
3d00666e90 optimize MCInstrDesc to reduce its size 2015-03-10 15:40:09 +08:00
Nguyen Anh Quynh
7d5266d64c sparc, systemz, xcore: getInstruction() should return boolean instead of DecodeStatus 2015-03-10 15:22:06 +08:00
Nguyen Anh Quynh
5160e2340d x86: multiple fixes for insns[] - reduced mode (X86Mapping.c) 2015-03-08 06:21:11 +08:00
Nguyen Anh Quynh
c0fa5b744b x86: multiple fixes for insns[] (X86Mapping.c) 2015-03-08 06:09:47 +08:00
Nguyen Anh Quynh
7334a88041 Merge branch 'master' into v3 2015-03-03 11:43:36 +08:00
Félix Cloutier
f7e5bfe315 Silencing Clang warning about losing precision 2015-03-02 22:19:58 -05:00
Félix Cloutier
e255659c3c Silencing uninitialized variable warning about insn_id 2015-03-02 22:12:56 -05:00
Félix Cloutier
c141af9052 Silencing Clang warning bys casting values 
Warnings were: "Implicit conversion loses integer precision: 'size_t' to 'cs_mode'/'cs_opt_value'"
 2015-03-02 22:11:55 -05:00
Nguyen Anh Quynh
fbfa06deb7 mips: sanity check for input code length of Mips64 2015-02-27 17:31:24 +08:00
Nguyen Anh Quynh
ed46b0b27a x86: allow prefixes to be positioned anywhere. this should fix the bug reported by Gabriel Quadros 2015-02-26 07:09:34 +08:00
Nguyen Anh Quynh
b756aed7b2 arm: fix some warnings reported by MSVC 2015-02-25 18:01:55 +08:00
Nguyen Anh Quynh
8c9fd12bc3 arm: fix some warnings reported by MSVC 2015-02-25 18:01:02 +08:00
pzread
5598301217 Correct printAM3PreOrOffsetIndexOp disp value 2015-02-15 22:42:06 +08:00
pzread
996f06c30f Correct printAM3PreOrOffsetIndexOp disp value 2015-02-15 18:22:51 +09:00
pzread
61cbeabb44 Remove incorrect ITBlock.size = 0 2015-02-15 01:40:58 +09:00
Nguyen Anh Quynh
f15d3dd4bd x86: REPNE can go with STOS/MOVS. bug reported by Gabriel Quadros 2015-02-13 11:26:13 +08:00
Nguyen Anh Quynh
c48a16aeca x86: add the missing X86 instructions in X86_REDUCE mode in X86DisassemblerDecoder.c. bug reported by Julian Stecklina 2015-02-12 09:02:25 +08:00
Nguyen Anh Quynh
e10b53f110 x86: fix operand size for 'CALL PTR [REG]'. bug reported by Gabriel Quadros 2015-02-10 18:46:25 +08:00
Nguyen Anh Quynh
9426ad572f arm: add few more post-indexed instructions doing writeback 2015-01-21 20:03:40 +08:00