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630 Commits

Author SHA1 Message Date
Nguyen Anh Quynh
4b6b15fcb1 fix more MSVC warnings 2014-08-26 15:57:04 +08:00
Nguyen Anh Quynh
07c92ec20a fix warnings reported by MSVC 2014-08-26 15:35:11 +08:00
Nguyen Anh Quynh
ed1234a892 xcore: update core 2014-08-26 14:11:09 +08:00
Nguyen Anh Quynh
a7792ae488 systemz: update core. also update Python & Java bindings 2014-08-26 12:14:25 +08:00
Nguyen Anh Quynh
14b684e07d last commit missed a check 2014-08-25 23:45:52 +08:00
Nguyen Anh Quynh
b1e87e3e31 arm, mips, ppc, spac, x86: printAliasInstr() should handle \t (besides space) as separate char between mnemonic & operands 2014-08-25 23:27:33 +08:00
Nguyen Anh Quynh
8027adad6c arm64: refine output of some instructions to make them match available test suites 2014-08-25 23:20:59 +08:00
Nguyen Anh Quynh
62af137a81 arm64: printAliasInstr() should handle \t (besides space) as separate char between mnemonic & operands 2014-08-25 22:30:10 +08:00
Nguyen Anh Quynh
c286b346c6 Merge branch 'arm64' into v3 2014-08-25 17:01:53 +08:00
Nguyen Anh Quynh
0efef5dd48 solve some conflicts when merging -next into -v3 2014-08-25 17:01:45 +08:00
Nguyen Anh Quynh
46a74e53b7 arm64: update core. this added a lot more details to cs_arm64_op struct 2014-08-25 16:47:12 +08:00
Nguyen Anh Quynh
ffb6b23c7d x86: add SMAP group for CLAC/STAC instructions 2014-08-22 14:47:29 +07:00
Nguyen Anh Quynh
663829431e x86: return proper error if cs_option() enables AT&T syntax but AT&T support is opt-out at compile time 2014-08-20 14:02:14 +08:00
Nguyen Anh Quynh
a65e77baee Merge branch 'no_att' of https://github.com/obs1dium/capstone into next 2014-08-20 13:50:29 +08:00
Nguyen Anh Quynh
1ce5dea3e0 ppc: fix an unused variable warning 2014-08-20 11:51:46 +08:00
obs
2725a3fea8 X86GenInstrInfo size reduction 2014-08-19 20:12:39 +02:00
obs
b7e2ff451f x86.operands array wasn't fully cleared 2014-08-17 21:46:30 +02:00
baguette
86e845056d renamed CAPSTONE_NO_ATT to CAPSTONE_X86_ATT_DISABLE, added options to makefile, cmake, compile.txt 2014-08-17 20:59:05 +02:00
baguette
4f412c4483 Selectively disable AT&T syntax in non-diet mode to reduce library size 2014-08-17 19:38:20 +02:00
Nguyen Anh Quynh
a726402513 sparc: update core. this added/removed some instructions & groups. updated Python & Java bindings accordingly 2014-08-15 18:29:17 +08:00
Nguyen Anh Quynh
2124b8a9c9 mips: indentations 2014-08-15 16:37:03 +08:00
Nguyen Anh Quynh
159ddbd99f ppc: add new groups to group_name_maps[] 2014-08-15 16:35:12 +08:00
Nguyen Anh Quynh
64f36d9759 change '2013>' to 2013-2014 2014-08-15 13:53:44 +08:00
Nguyen Anh Quynh
91a64776a8 ppc: fix a mistake on interpreting CR registers by deleting CR8 -> CR31 2014-08-15 13:48:11 +08:00
Nguyen Anh Quynh
dd3deec1e9 ppc: update core. this added new instructions, groups & registers. updated Python & Java bindings accordingly 2014-08-15 13:26:12 +08:00
Nguyen Anh Quynh
0f0eb9851a mips: update core. this added bunch of new instructions & groups. updated Python & Java bindings accordingly 2014-08-14 18:26:39 +08:00
Nguyen Anh Quynh
7c089fd6c6 arm: add new mode CS_MODE_MCLASS for Cortex-M series. updated Python & Java bindings accordingly 2014-08-13 23:08:40 +08:00
Nguyen Anh Quynh
b52f11f636 arm: update core. this added a new instruction UDF. also updated Python+Java bindings accordingly 2014-08-13 22:38:15 +08:00
Nguyen Anh Quynh
0b690387b3 x86: update core with upstream. this added bunch of new instructions & groups. also updated Python & Java bindings after the core change 2014-08-13 13:01:50 +08:00
Nguyen Anh Quynh
4db4d9bdd7 xcore: fix an warning of unused array when DIET mode is enable 2014-08-13 00:29:51 +08:00
Nguyen Anh Quynh
590f23af54 arm: do not need to initialize local variable opcode in DecodeRegListOperand() 2014-07-31 21:23:51 +08:00
Nguyen Anh Quynh
0c235e15ab arm: some simple improvements & cleanups 2014-07-31 21:16:54 +08:00
Nguyen Anh Quynh
26dfbc6677 fix indentation introduced by the latest merge. also move test_arm_regression.c into suite/arm/ and add Makefile for it 2014-07-31 18:24:51 +08:00
Nguyen Anh Quynh
5d8067822b Merge branch 'next' of https://github.com/flyingsymbols/capstone into arm 2014-07-31 15:36:13 +08:00
Nguyen Anh Quynh
48eb7a6614 x86: INTO is invalid in 64bit mode. bug reported by Pancake & Ange Albertini 2014-07-21 23:08:52 +08:00
flyingsymbols
298d413bbc * added a test file to suite for testing invalid and valid instruction sequences 
* fixed and added a test for a thumb-2 invalid sequence that was incorrectly allowed before these changes (pop.w with sp argument included)
* fixed and added a test for a blx from thumb to ARM that had its immediate argument incorrect (misaligned)

* eliminated some warnings by explicitly casting so I could turn on
  treat warnings as errors locally

General notes:
*  probably worth turning on treat all warnings as errors in the msvc project files, had a subtle bug that resulted from a missing declaration causing differences in dll and static compilation modes

( code was working incorrectly in dll form because of missing declaration in arch/ARM/ARMMapping.h for new function ARM_blx_to_arm_mode. Something about the linking was confusing ld when making the dll, and the resulting offsets were wonky (e.g. the added ble test would show up as #0x1fc instead of #0x1fe like it should have )

* the invalid pop was being treated as a soft fail which then gets coerced
  to a success because it is != MCDisassembler_Fail in Thumb_getInstruction
  what are the semantics of a soft fail? Maybe we should be able to set up
  whether or not we want a soft fail to be a real fail in the csh struct?
 2014-07-15 04:33:40 -04:00
Nguyen Anh Quynh
55cd996add sparc: initialize detail->sparc in Sparc_getInstruction. bug reported by Ben Nagy 2014-07-09 13:08:17 +08:00
Nguyen Anh Quynh
e1fc8a83ba sparc: initialize detail->sparc in Sparc_getInstruction. bug reported by Ben Nagy 2014-07-09 13:07:45 +08:00
Nguyen Anh Quynh
4d2eba7f43 systemz: initialize detail->sysz in SystemZ_getInstruction. bug reported by Ben Nagy 2014-07-09 11:27:09 +08:00
Nguyen Anh Quynh
39d6b2f066 systemz: initialize detail->sysz in SystemZ_getInstruction. bug reported by Ben Nagy 2014-07-09 11:26:53 +08:00
Nguyen Anh Quynh
650f96ce43 add new API cs_group_name() to return group name in string, given the group id 2014-07-08 08:59:27 +08:00
Nguyen Anh Quynh
bb8bbaa930 x86: test reg, [mem] -> test [mem], reg. bug reported by Gabriel Quadros 2014-07-04 09:48:58 +08:00
Nguyen Anh Quynh
dbdb61a9cf x86: regs_write[] of RDTSC & RDTSCP depend on @mode 2014-07-02 12:45:02 +08:00
Nguyen Anh Quynh
9f6ed7155a x86: add @rex to cs_x86 struct. updated python & java binding for this change 2014-07-01 10:13:28 +08:00
Nguyen Anh Quynh
32e2c6c9c7 x86: address-size prefix should override RIP relative address in x64 mode. bug reported by @hlide 2014-06-30 07:58:33 +08:00
Nguyen Anh Quynh
ed6b8c5a96 x86: address-size prefix should override RIP relative address in x64 mode. bug reported by @hlide 2014-06-30 07:57:29 +08:00
Nguyen Anh Quynh
656ebc9625 x86: handle RIP relative addressing in 64bit mode properly. bug reported by @hlide 2014-06-30 02:01:42 +08:00
Nguyen Anh Quynh
af6db2afe8 x86: handle RIP relative addressing in 64bit mode properly. bug reported by @hlide 2014-06-30 02:01:04 +08:00
Nguyen Anh Quynh
7ef3700550 x86: SHL reg, 1 has one too many operands. bug reported by Sean Heelan 2014-06-27 21:54:45 +08:00
Nguyen Anh Quynh
1a66fecdbc x86: support avx_sae & avx_rm in cs_x86 struct. this also updates Python & Java bindings following the core's change 2014-06-26 12:09:15 +08:00
Nguyen Anh Quynh
12e6e31389 x86: rename zero_opmask of cs_x86_op to avx_zero_opmask 2014-06-26 11:27:24 +08:00
Nguyen Anh Quynh
92a3d4c079 x86: add AVX's zero_opmask to cs_x86_op struct. updated Python & Java bindings for this change 2014-06-25 23:10:39 +08:00
Nguyen Anh Quynh
f1ec52628e x86: provide size for X86_OP_IMM operand. thank Gabriel Quadros for some suggestions 2014-06-25 22:03:18 +08:00
Nguyen Anh Quynh
e1aba1703f x86: fix all {cc} instructions to have correct instruction ID 2014-06-25 21:06:44 +08:00
Nguyen Anh Quynh
4c5eabc32b x86: support SSE_CC & AVX_CC in cs_x86 struct. this also updates Python & Java bindings 2014-06-24 23:50:41 +08:00
Nguyen Anh Quynh
0d716450fc x86: add avx_bcast to cs_x86_op to support AVX512 instructions. this also updates Python & Java binding 2014-06-24 22:51:56 +08:00
Nguyen Anh Quynh
bb6440c5ef x86: extend cs_x86.opcode to 4 bytes to contain EVEX opcode. this also updates Python binding following this interface change 2014-06-24 21:46:54 +08:00
Nguyen Anh Quynh
15b746fe4f x86: op_addReg() & op_addImm() only work when detail mode is ON 2014-06-24 16:13:37 +08:00
Nguyen Anh Quynh
c74ec28691 x86: LEA for 16bit register should have pointer size of word, not dword. bug reported by Gabriel Quadros 2014-06-24 15:49:26 +08:00
Nguyen Anh Quynh
14ba46bfab x86: add segment to x86_op_mem struct. this fixes a bug in generating detail for instructions with segment override. bug reported by Sean Heelan. 2014-06-24 14:32:01 +08:00
Nguyen Anh Quynh
eb2f3fb85a x86: properly reset prefixPresent for prefix0/1 group 2014-06-20 11:15:58 +08:00
Nguyen Anh Quynh
1e688d4ff9 x86: do not use markup in AT&T syntax 2014-06-18 14:28:55 +08:00
Nguyen Anh Quynh
46291c139f Merge branch 'next' into opsize 2014-06-18 14:21:49 +08:00
Nguyen Anh Quynh
44db3c37fa x86: support CS_OPT_MODE for dynamically changing mode at run-time 2014-06-18 14:18:47 +08:00
Nguyen Anh Quynh
cff03629ac arm64: assign NULL to char pointer, not zero. bug reported by Coverity 2014-06-18 14:04:42 +08:00
Nguyen Anh Quynh
1085073f8f x86: remove disp_size, imm_size, op_size. add size to each operand. thanks Gabriel Quadros for some nice ideas 2014-06-18 12:16:24 +08:00
Nguyen Anh Quynh
73eb5d5486 arm: op_addImm() is called only when detail mode is ON 2014-06-17 18:08:29 +08:00
Nguyen Anh Quynh
cae09bf543 replace offset_of with offsetof from stddef.h 2014-06-17 14:58:39 +08:00
Nguyen Anh Quynh
ebe2443b9b arm: some special instructions need to have numerical operand added manually in printInstruction() 2014-06-17 13:56:01 +08:00
Nguyen Anh Quynh
eccb9da7a8 arm64: zeroout a whole cs_arm64 struct of MCI in *getInstruction(). 2014-06-17 13:34:25 +08:00
Nguyen Anh Quynh
73bbbb3800 arm: add ASRS, LSRS, VCLE, VCLT instructions. update Python & Java bindings at the same time 2014-06-17 13:29:54 +08:00
Nguyen Anh Quynh
8693fcdc99 arm: correct operand setup for REG type in printAddrMode3OffsetOperand() 2014-06-17 13:28:33 +08:00
Nguyen Anh Quynh
2a461ed422 arm: zeroout a whole cs_arm struct in *getInstruction(). this makes sure operand of REG type has shift type = 0 by default 2014-06-17 13:27:38 +08:00
Nguyen Anh Quynh
9cf88119fb x86: InternalInstruction@xAcquireRelease should be initialized to 0 (FALSE) 2014-06-16 18:32:34 +08:00
Nguyen Anh Quynh
495295ecd4 MCInst_Init() is arch-independent 2014-06-16 15:54:32 +08:00
Nguyen Anh Quynh
215e76b223 ppc: use MCInst_insert0() instead of MCInst_insert() to avoid malloc/free 2014-06-16 14:47:43 +08:00
Nguyen Anh Quynh
d06f3d662b xcore: use CreateImm0() & CreateReg0() to create MCOperand* to avoid using malloc/free 2014-06-16 14:35:08 +08:00
Nguyen Anh Quynh
88fca42a5f xcore: use SStream_concat0() instead of SStream_concat() for simple string processing whenever possible 2014-06-16 14:30:19 +08:00
Nguyen Anh Quynh
7062988855 systemz: use CreateImm0() & CreateReg0() to create MCOperand* to avoid using malloc/free 2014-06-16 13:09:15 +08:00
Nguyen Anh Quynh
bddd215099 systemz: use SStream_concat0() instead of SStream_concat() for simple string processing whenever possible 2014-06-16 13:02:41 +08:00
Nguyen Anh Quynh
3d3b6cec01 sparc: use CreateImm0() & CreateReg0() to create MCOperand* to avoid using malloc/free 2014-06-16 12:57:02 +08:00
Nguyen Anh Quynh
9b91de0ae3 sparc: use SStream_concat0() instead of SStream_concat() for simple string processing whenever possible 2014-06-16 12:51:07 +08:00
Nguyen Anh Quynh
7f945d3655 ppc: use CreateImm0() & CreateReg0() to create MCOperand* to avoid using malloc/free 2014-06-16 12:34:02 +08:00
Nguyen Anh Quynh
7f15f67544 ppc: use SStream_concat0() instead of SStream_concat() for simple string processing whenever possible 2014-06-16 12:11:50 +08:00
Nguyen Anh Quynh
f08b83ddba mips: use CreateImm0() & CreateReg0() to create MCOperand* to avoid using malloc/free 2014-06-16 12:04:25 +08:00
Nguyen Anh Quynh
0c764d4a70 mips: use SStream_concat0() instead of SStream_concat() for simple string processing whenever possible 2014-06-16 11:53:08 +08:00
Nguyen Anh Quynh
d489a679f4 arm64: use CreateImm0() & CreateReg0() to create MCOperand* to avoid using malloc/free 2014-06-16 11:46:20 +08:00
Nguyen Anh Quynh
cbb33583b3 arm64: use SStream_concat0() instead of SStream_concat() for simple string processing whenever possible 2014-06-16 11:16:30 +08:00
Nguyen Anh Quynh
9678705d57 arm: convert MCOperand_CreateReg() to MCOperand_CreateReg0() to avoid malloc/free 2014-06-10 13:59:55 +07:00
Nguyen Anh Quynh
748687df46 arm: convert the left-over MCOperand_CreateImm to MCOperand_CreateImm0 2014-06-10 09:18:39 +07:00
Nguyen Anh Quynh
0f648ea3e8 arm: use CreateImm0() & CreateReg0() to create MCOperand* to avoid using malloc/free to improve performance 2014-06-10 01:01:23 +07:00
Nguyen Anh Quynh
8c1104b567 arm: do not use markup 2014-06-10 00:39:06 +07:00
Nguyen Anh Quynh
dd9225b930 arm: use SStream_concat0() for SStream_concat() whereever possible for better performance 2014-06-10 00:37:53 +07:00
Nguyen Anh Quynh
b95647d2c1 systemz & xcore: create details only when detail mode is ON. this fixes some crashes in tests/test 2014-06-09 18:49:37 +07:00
Nguyen Anh Quynh
69582d71ae initialize cs_insn.detail by properly zero-out right members for each arch 2014-06-09 17:50:01 +07:00
Nguyen Anh Quynh
29fd0f6405 fix all the code in other non-X86 archs after the change made by commit 5329a6ffd4 2014-06-09 08:00:18 +07:00
Nguyen Anh Quynh
5329a6ffd4 directly update cs_insn from MCInst interface to avoid multiple memcpy() 2014-06-08 23:35:52 +07:00
Nguyen Anh Quynh
8cae86ccfa x86: copy prefix back after updating it in X86_lockrep() 2014-06-07 23:47:35 +08:00
Nguyen Anh Quynh
22a5a761d8 x86: simplify byteReader_t 2014-06-07 23:41:20 +08:00
Nguyen Anh Quynh
30c065998b optimize memset() of MCInst_Init() 2014-06-07 13:30:59 +08:00
Nguyen Anh Quynh
5474d877b0 x86: optimize struct InternalInstruction for memset(). this improve performance by around 4% 2014-06-07 12:56:44 +08:00
Nguyen Anh Quynh
0ad226e332 x86: fix a conflict when merging -next to -optimize branch 2014-06-06 00:59:15 +08:00
Nguyen Anh Quynh
cf0813809a x86: more simplification on managing MCOperand. this also fixes a bug in handling memory reference instructions 2014-06-06 00:56:46 +08:00
Nguyen Anh Quynh
0e534bf0ff x86: correct the related comment of the last commit 2014-06-05 17:05:16 +07:00
Nguyen Anh Quynh
9417ad6cd5 x86: printDstIdx() should only print segment in non-64bit mode. bug reported by Filipe Cabecinhas (@filcab) 2014-06-05 17:03:52 +07:00
Nguyen Anh Quynh
e70a043a04 x86: more simplification for better performance 2014-06-05 10:52:43 +08:00
Nguyen Anh Quynh
937e48314c x86: avoid malloc/free MCOperand with new API of MCInst: MCInst_addOperand0, MCInst_CreateReg0, MCInst_CreateImm0 2014-06-04 22:51:51 +07:00
Nguyen Anh Quynh
a62b9a07e4 x86: use SStream_concat0() where possible to improve performance - for AT&T and X86_REDUCE 2014-06-04 22:25:48 +07:00
Nguyen Anh Quynh
46b6693d36 x86: save prefixes to avoid expensive copying loop. based on idea of Dang Hoang Vu 2014-06-04 19:04:46 +08:00
Nguyen Anh Quynh
b76233c648 avoid using vsnprintf when possible for SStream_concat() to improve performance. based on the idea of Dang Hoang Vu. 2014-06-04 18:31:02 +08:00
Jay Oster
368c45b4c6 x86 instruction groups: Add SYSEXIT and SYSRET to the X86_GRP_IRET group 2014-06-04 00:08:46 -07:00
Nguyen Anh Quynh
a19d3f0b60 Merge branch 'feature/x86-groups' of https://github.com/parasyte/capstone into test 2014-06-04 13:35:12 +07:00
Jay Oster
6b00344f23 x86 instruction groups: Fix RET/IRET mapping. 2014-06-03 23:31:58 -07:00
Nguyen Anh Quynh
0577bb728c x86: ATT syntax does not print word size pointer like Intel syntax 2014-06-03 13:50:35 +07:00
Jay Oster
6f74ccc97a Add new x86 instruction groups 
- VM: Virtual Machine
- INT: Interrupts
- IRET: Interupt returns
- CALL: Subroutine call
- RET: Subroutine return

Includes a special case for writes to port 0xb2, which triggers an SMI
 2014-06-02 22:21:41 -07:00
Nguyen Anh Quynh
c70442edc6 arm: shift info associates with the right op in LDR instruction. bug reported by Daniel Colascione 2014-06-01 11:35:34 +07:00
Nguyen Anh Quynh
a04ee4feb8 arm: add missing the check for detail mode in the last commit 2014-06-01 10:52:01 +07:00
Nguyen Anh Quynh
b79d915a38 arm: add missing operand info for Thumb instruction vldr. bug reported by Daniel Colascione 2014-06-01 10:48:55 +07:00
Nguyen Anh Quynh
bb71c13098 arm: add missing operand info for Thumb instruction LDR involving label. bug reported by Daniel Colascione 2014-06-01 10:14:31 +07:00
Nguyen Anh Quynh
6eb55cf52e arm: add operand details for 'mov pc, lr'. bug reported by Daniel Colascione 2014-06-01 10:03:14 +07:00
Nguyen Anh Quynh
48b6cb4ce5 arm: CC_AL is the default code condition for instructions without CC. bug reported by Daniel Colascione 2014-06-01 09:45:19 +07:00
Nguyen Anh Quynh
5e2e660be7 fix some warnings reported by Coverity 2014-05-30 17:43:36 +08:00
Nguyen Anh Quynh
2c20a1b5a3 ppc: wrong comparison in printOperand(). bug found by Coverity 2014-05-30 17:00:20 +08:00
Nguyen Anh Quynh
b70e121ce3 x86: FP instructions are only available when X86_REDUCE mode is off 2014-05-28 15:57:51 +08:00
Nguyen Anh Quynh
d0023197eb cmake: support Sparc, SystemZ & XCore 2014-05-28 15:15:00 +08:00
Nguyen Anh Quynh
3a5965eb05 xcore: fix some warnings with Diet mode 2014-05-28 15:14:28 +08:00
Nguyen Anh Quynh
0150f06553 x86: fix a warning on Diet mode 2014-05-28 15:04:15 +08:00
Nguyen Anh Quynh
9148420b0d replace strcasecmp() with strcmp() 2014-05-28 12:57:46 +08:00
Nguyen Anh Quynh
d69f9ded5b x86: delete dead code 2014-05-28 12:39:11 +08:00
Nguyen Anh Quynh
b2e566ac88 xcore: use strcpy() rather than strncpy() 2014-05-28 11:35:19 +08:00
Nguyen Anh Quynh
2a33afe6e8 msvc: make MSVC shutup on strncpy() 2014-05-28 00:24:33 +08:00
Nguyen Anh Quynh
dc1af545c0 msvc: fix warnings 2014-05-28 00:14:22 +08:00
Nguyen Anh Quynh
be2b788dc1 xcore: handle details for some special tricky instructions 2014-05-27 23:34:03 +08:00
Nguyen Anh Quynh
f721e3124d Disassembler -> Disassembly 2014-05-27 10:45:58 +08:00
Nguyen Anh Quynh
8f50ba894c Merge branch 'next' into xcore 2014-05-27 10:39:11 +08:00
Nguyen Anh Quynh
04f2ec6d0f cleanup redundant headers included 2014-05-27 10:39:04 +08:00
Nguyen Anh Quynh
2cf9c524da x86: MOV64rr belongs to GRP_MODE64 group. bug reported by Jason Oster 2014-05-27 07:23:53 +08:00
Nguyen Anh Quynh
553bb488d7 python: support XCore 2014-05-26 23:47:45 +08:00
Nguyen Anh Quynh
c80d840ffc add XCore architecture 2014-05-26 23:02:48 +08:00
Nguyen Anh Quynh
3dc080c2b6 systemz: cleanup SystemZGenDisassemblerTables.inc 2014-05-26 15:54:16 +08:00
Nguyen Anh Quynh
5d6383e335 sparc: SPARC_CC_ICC_N should not have the same value as SPARC_CC_INVALID. bug reported by Jason Oster 2014-05-25 13:48:06 +08:00
Jason Oster
6380446222 Add r0l register to SystemZMapping.c 2014-05-24 21:26:12 -07:00
Nguyen Anh Quynh
4ebd062ee3 x86: cleanup unused code 2014-05-22 12:11:35 +08:00
Nguyen Anh Quynh
fed098f9a7 x86: eliminate irrelevant prefixes in x86.prefix[] - such as f2/f3 prefixed irrelevant instructions 2014-05-22 12:10:21 +08:00
Nguyen Anh Quynh
1e93adf5c3 x86: add CL operand into details for 'SHL *, CL' instruction 2014-05-21 17:10:10 +08:00
Nguyen Anh Quynh
7a65ad7e4b x86: detail operands for 'fstpnce st(0), st(0)' & 'fstpst(7), st(0)' 2014-05-21 16:18:56 +08:00
Nguyen Anh Quynh
b6e3f01bb8 x86: handle REP MOVSD/CMPSD/SCASD/LODSD/STOSD properly (due to confused 128bit media instructions having the same mnemonics) 2014-05-21 15:11:58 +08:00
Nguyen Anh Quynh
3a86d92e7c x86: correct instructions related to REP prefix 2014-05-21 14:12:24 +08:00
Nguyen Anh Quynh
1d6f7ee50e x86: prefix REP/REPNE are only relevant for MOVS/CMPS/SCAS/LDOS/STOS/INS/OUTS instructions 2014-05-21 12:38:10 +08:00
Jason Oster
984ed7e9e8 MIPS: Add HI, LO, and PC registers to MipsMapping.c 
- Using MIPS_REG_HI, MIPS_REG_LO, and MIPS_REG_PC with cs_reg_name() caused out-of-bounds reads
 2014-05-19 22:56:19 -07:00
Nguyen Anh Quynh
6456481508 x86: add immediate operand (1) for SHL/SHR/ROR/ROL/SAR/SAL in detail mode & Intel syntax 2014-05-19 16:46:31 +08:00
Nguyen Anh Quynh
f338657f17 x86: set syntax variable when changing syntax with cs_option() 2014-05-19 16:34:54 +08:00
Nguyen Anh Quynh
1922b2f74b arm64: clean reg_name_maps[] 2014-05-18 10:30:09 +08:00
Nguyen Anh Quynh
c5cad6cab3 avoid using stdbool.h to support compilers without C99 support 2014-05-15 21:40:24 +08:00
Nguyen Anh Quynh
1d2e69b869 msvc: remove headers/ directory & replace it with include/platform.h 2014-05-15 13:56:54 +08:00
Nguyen Anh Quynh
7bab8dc12e x86: AT&T syntax is irrelevant in Diet mode, so setting this syntax should return CS_ERR_DIET error 2014-05-14 23:48:17 +08:00
Nguyen Anh Quynh
f7850266d5 x86: enable AT&T code only when DIET mode is off 2014-05-14 22:03:06 +08:00
Nguyen Anh Quynh
0ffd811d67 merge next branch 2014-05-14 14:33:03 +08:00
Nguyen Anh Quynh
b2a88df20f MSVC added some code picked up by MingW, so cross-win32/74 compile is broken. this fixes the issue 2014-05-14 14:28:40 +08:00
Nguyen Anh Quynh
506890863c x86: assembly syntax is irrelevant in Diet mode. this optimization reduces library size to only 180KB on OSX 2014-05-14 12:26:53 +08:00
Nguyen Anh Quynh
8598a219f3 enable arch code from source with CAPSTONE_HAS_* for MSVC to pick up 2014-05-14 11:26:41 +08:00
Nguyen Anh Quynh
eb2e840887 x86: fix C89 issues for X86GenAsmWriter1_reduce.inc & X86GenAsmWriter_reduce.inc 2014-05-12 21:53:53 +08:00
Nguyen Anh Quynh
cfcace3f43 arm: make checkDecoderPredicate() handle boolean casting for MSVC (redone in more systematic way for autogen code) 2014-05-12 21:38:05 +08:00
Nguyen Anh Quynh
805fed5162 make checkDecoderPredicate() handle boolean casting for MSVC 2014-05-12 21:29:04 +08:00
Nguyen Anh Quynh
ef3e450f1a arm: checkDecoderPredicate() needs to handle Bool data type in the way that MSVC can understand 2014-05-12 18:15:18 +08:00
Nguyen Anh Quynh
043702e9ef more fixes for warnings reported by MSVC 2014-05-12 16:17:00 +08:00
Nguyen Anh Quynh
6893ec535e more warnings fixed reported by MSVC 2014-05-12 15:36:38 +08:00
Nguyen Anh Quynh
638835a1d5 fix some warnings reported by MSVC 2014-05-12 15:15:32 +08:00
Nguyen Anh Quynh
abffe02a46 sparc: recover autogen code in arch/Sparc/SparcGenDisassemblerTables.inc 2014-05-12 13:48:22 +08:00
Nguyen Anh Quynh
bb0744df5d do not initialize some local vars unnecessarily. this problem was introduced when we fixed C89 issues for MSVC 2014-05-12 13:41:49 +08:00
Nguyen Anh Quynh
2d34251889 x86: handle 16bit segment bound for JMP. bug reported by Pancake & Anton Kochkov 2014-05-11 15:33:11 +08:00
Nguyen Anh Quynh
0596e11bd5 arm64: fix a wrong int type of a local var in printLabelOperand. this bug was introduced when we fixed C89 issue for MSVC 2014-05-10 09:17:48 +08:00
Axel 0vercl0k Souchet
35c8467275 still want that to compile on other systems 2014-05-09 20:51:02 +01:00
Axel 0vercl0k Souchet
605faf1db9 moved the hardcoded macros in the vcproj & just disable the warning for the crt 2014-05-09 20:40:00 +01:00
Nguyen Anh Quynh
b5e7db57ee Merge branch 'next' into msvc2 2014-05-09 17:38:31 +08:00
Nguyen Anh Quynh
d27b0155ef arm: add BLX_pred into the list of relative branch instructions 2014-05-09 17:34:54 +08:00
Nguyen Anh Quynh
bc80b3dc24 arm: fix some more Thumb relative branch instructions. bug reported by Giovanni Nanomad Condello 2014-05-09 17:31:41 +08:00
Nguyen Anh Quynh
42706a39e2 indentation with tab 2014-05-09 07:33:35 +08:00
Nguyen Anh Quynh
336bf29230 Merge branch 'next' of https://github.com/0vercl0k/capstone into msvc2 2014-05-09 07:10:47 +08:00
Nguyen Anh Quynh
d43187d4f9 arm: BLXi is another relative branch instruction to be fixed. bug reported by Giovanni Nanomad Condello 2014-05-09 07:02:51 +08:00
Axel 0vercl0k Souchet
779d4c75d9 first changes to get a successfully compiled version of capstone on VS2012 2014-05-08 23:44:49 +01:00
Nguyen Anh Quynh
49a1cb374c arm: fix another relative jump issue. bug reported by Giovanni Nanomad Condello 2014-05-08 23:42:06 +08:00
Nguyen Anh Quynh
958927eb56 clean up after the last removal of SubtargetFeature.h 2014-05-08 22:59:28 +08:00
Nguyen Anh Quynh
79e1dcb5f1 arm: update target branch having relative offset. issue reported by Giovanni Condello 2014-05-07 14:12:50 +08:00
Nguyen Anh Quynh
e68ee701c4 x86: simplify code handling LOCK/REP by remembering this prefix status when decoding it 2014-05-07 13:57:09 +08:00
Nguyen Anh Quynh
16837f8431 x86: MULPD instruction is unavailable in X86_REDUCE mode 2014-05-07 12:34:27 +08:00
Nguyen Anh Quynh
288d6b3c8a x86: properly handle lock/rep prefixes when DIET option is enable 2014-05-07 12:26:55 +08:00
Nguyen Anh Quynh
9bcca47a98 x86: avoid duplicating code when handling prefixes in X86_getInstruction() 2014-05-07 11:45:02 +08:00
Nguyen Anh Quynh
45c77aeadd x86: handle tricky instructions related to MULPD at http://habrahabr.ru/company/intel/blog/200658/ 2014-05-07 11:39:41 +08:00
Nguyen Anh Quynh
5c7f0c3e0d x86: REP & REPNE are mutually exclusive prefixes 2014-05-07 10:06:24 +08:00
Nguyen Anh Quynh
a5ffdc3a80 x86: properly handle LOCK/REP in the core, so remove buch of hacks 2014-05-07 08:25:24 +08:00
Nguyen Anh Quynh
e106f701ef x86: only handle 3DNow instructions when X86_REDUCE mode is disable 2014-05-06 17:09:21 +08:00
Nguyen Anh Quynh
13d8c6f205 x86: support 3DNow instructions 2014-05-06 15:02:21 +08:00
Nguyen Anh Quynh
57e784b865 x86: cleanup unused opcode tables for X86_REDUCE 2014-05-06 12:22:42 +08:00
Giovanni Condello
7c78778cfc Make capstone library compile with arm-none-eabi-gcc 4.8 2014-05-02 20:15:53 +02:00
Nguyen Anh Quynh
ca057fa8f6 x86: identation 2014-04-30 14:26:10 +08:00
Nguyen Anh Quynh
17874d084e x86: handle NOP instruction 0f18* 2014-04-29 11:16:21 +08:00
Nguyen Anh Quynh
2c5e3e5833 x86: allow 0x66 & 0x67 prefixes to be put anywhere in front of an instruction 2014-04-28 15:46:52 +08:00
Nguyen Anh Quynh
2cff6f61fc x86: handle instructions with LOCK/REP/REPNE prefix after other prefixes. bear with this until we have a better approach 2014-04-28 11:19:44 +08:00
Nguyen Anh Quynh
1b4864ac46 x86: fix comments on MOVcr, MOVdr, MOVrc, MOVrd 2014-04-25 13:44:31 +08:00
Nguyen Anh Quynh
e93179b851 x86: BOUND instruction uses dword & qword for boundary array, but not memory reference 2014-04-25 11:18:40 +08:00
Nguyen Anh Quynh
7437a41bfa x86: minor fixes for comments on MOV32cr etc: this is related to 64bit code as well 2014-04-25 10:51:37 +08:00
Nguyen Anh Quynh
fe94c2b270 x86: BOUND opcode is reused by EVEX instruction set, so must be handled properly 2014-04-25 10:47:50 +08:00
Nguyen Anh Quynh
96bda4f8b4 x86: MOV32cr & co. work for x64, not only x86. thank Joxean Koret for the help to verify this. 2014-04-24 23:03:26 +08:00
Nguyen Anh Quynh
0902bf2a25 x86: handle MOV32cr, MOV32dr, MOV32rc, MOV32rd 2014-04-24 22:46:25 +08:00
Nguyen Anh Quynh
2a9c0e0396 x86: fix a bug when sign-extend immediate for Ev. backport from upstream LLVM 2014-04-23 16:19:15 +08:00
Nguyen Anh Quynh
fa697076b1 x86: handle more tricky instructions. 
- support undocumented instructions FSTP & FSTPNCE. see http://blogs.technet.com/b/mmpc/archive/2013/06/24/investigation-of-a-new-undocumented-instruction-trick.aspx
- TEST instructions with opcode 0xF6, 0xF7 (MRM1r)
 2014-04-23 12:41:16 +08:00
Nguyen Anh Quynh
2ce77133f5 x86: support some tricky instructions 
- NOP instructions with encoding 0f {19-1f}. see http://code.google.com/p/corkami/wiki/x86oddities?show=content
- TEST instructions with opcode 0xF6, 0xF7 (MRM1m)
- Fix arithmetic instructions with opcode 0x82: only available in Non64bit mode
 2014-04-22 17:49:54 +08:00
Nguyen Anh Quynh
33e16362d6 x86: support 0x82 opcode for Arithmetic instructions 2014-04-20 11:32:00 +08:00
Nguyen Anh Quynh
6f56ff5663 x86: handle SAL instructions. bug reported by Attila Suszter & Ange Albertini 2014-04-16 17:29:34 +08:00
Nguyen Anh Quynh
a247dc187d arm: print address Imm without prefix 0x for Imm >= -9 2014-04-12 00:19:42 +08:00
Nguyen Anh Quynh
9df79afc77 systemz: cleanup 2014-04-10 22:17:07 +08:00
Nguyen Anh Quynh
2579a3fae9 systemz: add a missing operand for instructions involving PCRel 2014-04-10 18:14:08 +08:00
Nguyen Anh Quynh
81a6df4d00 x86: temporarily revert a part of commit 2be9b8791a due to some broken output 2014-04-01 07:24:33 +08:00
Nguyen Anh Quynh
40f72fde6f arm: do not update target branch with relative offset 2014-03-31 22:07:40 +08:00
Nguyen Anh Quynh
7626808de6 Merge branch 'x86imm' into next 2014-03-29 21:38:31 +08:00
Nguyen Anh Quynh
6d3d8005aa x86: do not print memory offset in negative form. bug reported by Le Dinh Long 2014-03-29 17:26:51 +08:00
Nguyen Anh Quynh
125f504174 x86: print offset value in memory reference instruction properly when offset is negative. bug reported by Le Dinh Long 2014-03-29 12:02:21 +08:00
Nguyen Anh Quynh
2eb37ee02a ppc: disable some redundant functions when Diet option is enable 2014-03-28 10:38:55 +08:00
Nguyen Anh Quynh
d325b1a94b x86: reduce mode support VMX/SVM instructions now 2014-03-27 14:44:38 +08:00
Nguyen Anh Quynh
e51cf36636 x86: do not print negative immediate. request of Le Dinh Long 2014-03-27 12:36:46 +08:00
Nguyen Anh Quynh
59b5489d8e x86: rename X86_COMPACT to X86_REDUCE. suggested by Pancake 2014-03-27 10:54:44 +08:00
Nguyen Anh Quynh
a3c9bd678f sparc: more fix to print negative numbers in more friendly way 2014-03-26 16:22:16 +08:00
Nguyen Anh Quynh
ffff756d21 arm: more fix to print negative numbers in more friendly way 2014-03-26 16:21:31 +08:00
Nguyen Anh Quynh
6211ab8e5e arm64: fix the rest code printing out negative numbers like big decimal positive numbers 2014-03-26 11:53:00 +08:00
Nguyen Anh Quynh
6f4840270a arm64: properly print immediate in friendly format in printSImm7ScaledOperand(). bug reported by Amanieu 2014-03-25 23:41:10 +08:00
Nguyen Anh Quynh
9518148e6f add X86_COMPACT option. also add CS_SUPPORT_X86_COMPACT. made Python support this change 2014-03-25 23:20:41 +08:00
Nguyen Anh Quynh
6db860a246 systemz: indentation 2014-03-25 06:35:51 +08:00
pancake
d889290a02 Remove C++ dependency and fix SystemZ initialization 2014-02-04 08:11:07 +01:00
Nguyen Anh Quynh
7e92884f41 systemz: fix for details 2014-03-24 17:27:32 +08:00
Nguyen Anh Quynh
d04aad77f6 systemz: support Diet option 2014-03-24 17:26:14 +08:00
Nguyen Anh Quynh
f0ff96138e systemz: print immediates in range [-9, 9] without 0x prefix 2014-03-24 13:41:28 +08:00
Nguyen Anh Quynh
da1e833c8c systemz: support accesss register operand 2014-03-23 11:12:07 +08:00
Nguyen Anh Quynh
b3d000a841 fix SystemZ on Op 2014-03-23 09:15:50 +08:00
Nguyen Anh Quynh
48a14ca4ce add SystemZ arch 2014-03-23 08:35:45 +08:00
Nguyen Anh Quynh
88b2833760 sparc: cleanup 2014-03-22 13:41:04 +08:00
Nguyen Anh Quynh
017df604dc arm64, mips, x86: print -9, not -0x9 2014-03-20 15:38:51 +08:00
Nguyen Anh Quynh
beda293c06 arm64: print label & offset in hex format for negative numbers 2014-03-20 15:30:54 +08:00
Nguyen Anh Quynh
fa814fe479 x86: flag short instruction with missing SIB byte as broken one. ported from upstream. bug reported by @longledinh 2014-03-20 14:14:27 +08:00
Nguyen Anh Quynh
f6c7cbc972 core: fix some warnings 2014-03-12 12:50:54 +08:00
Nguyen Anh Quynh
65c7a01d4f sparc: fix warning on unused variable 2014-03-11 10:31:53 +08:00
Nguyen Anh Quynh
2ff665ad4a arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp') 2014-03-11 00:18:50 +08:00
Nguyen Anh Quynh
641be49c2f sparc: fix mnemnonic for some alias instructions 2014-03-10 17:57:04 +08:00
Nguyen Anh Quynh
78153f59bb sparc: add SWAP instruction 2014-03-10 15:29:33 +08:00
Nguyen Anh Quynh
1055a2e22a python: support Sparc 2014-03-10 14:37:08 +08:00
Nguyen Anh Quynh
05e27138ae core: add Sparc arch 2014-03-10 11:58:57 +08:00
Nguyen Anh Quynh
cbaf913d68 arm: fix a bug in getting data from input buffer of Thumb: bail out if not enough data 2014-03-06 21:50:45 +08:00
Nguyen Anh Quynh
1514d5ca0c ppc: cleaning up 2014-03-06 14:04:45 +08:00
Nguyen Anh Quynh
1c68ab9293 cleaning up unused code 2014-03-06 12:41:28 +08:00
Nguyen Anh Quynh
ce2ad202d2 x86: clean up X86ATTInstPrinter.c 2014-03-04 15:00:33 +08:00