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Author SHA1 Message Date
Nguyen Anh Quynh
f1ec52628e x86: provide size for X86_OP_IMM operand. thank Gabriel Quadros for some suggestions 2014-06-25 22:03:18 +08:00
Nguyen Anh Quynh
e1aba1703f x86: fix all {cc} instructions to have correct instruction ID 2014-06-25 21:06:44 +08:00
Nguyen Anh Quynh
4c5eabc32b x86: support SSE_CC & AVX_CC in cs_x86 struct. this also updates Python & Java bindings 2014-06-24 23:50:41 +08:00
Nguyen Anh Quynh
0de6783d49 python: print instruction's basic info from print_detail() of test_detail.py 2014-06-24 23:00:16 +08:00
Nguyen Anh Quynh
0d716450fc x86: add avx_bcast to cs_x86_op to support AVX512 instructions. this also updates Python & Java binding 2014-06-24 22:51:56 +08:00
Nguyen Anh Quynh
eeb06902ed java: update X86 after the last change in the core 2014-06-24 21:48:19 +08:00
Nguyen Anh Quynh
bb6440c5ef x86: extend cs_x86.opcode to 4 bytes to contain EVEX opcode. this also updates Python binding following this interface change 2014-06-24 21:46:54 +08:00
Nguyen Anh Quynh
15b746fe4f x86: op_addReg() & op_addImm() only work when detail mode is ON 2014-06-24 16:13:37 +08:00
Nguyen Anh Quynh
c74ec28691 x86: LEA for 16bit register should have pointer size of word, not dword. bug reported by Gabriel Quadros 2014-06-24 15:49:26 +08:00
Nguyen Anh Quynh
d29aa6235a x86: correct comments on x86_op_mem.scale 2014-06-24 14:52:16 +08:00
Nguyen Anh Quynh
0467842205 java: update X86 binding after the last update in the core 2014-06-24 14:35:47 +08:00
Nguyen Anh Quynh
14ba46bfab x86: add segment to x86_op_mem struct. this fixes a bug in generating detail for instructions with segment override. bug reported by Sean Heelan. 2014-06-24 14:32:01 +08:00
Nguyen Anh Quynh
d948dd42b8 tests/test_x86: prefix[] size is now 4, not 5 2014-06-20 13:55:24 +08:00
Nguyen Anh Quynh
f3a9659cd5 python & java: update x86 following the last update in core 2014-06-20 13:46:53 +08:00
Nguyen Anh Quynh
fb15221666 x86: cs_x86.prefix[] should have size 4, not 5 2014-06-20 13:46:19 +08:00
Nguyen Anh Quynh
eb2f3fb85a x86: properly reset prefixPresent for prefix0/1 group 2014-06-20 11:15:58 +08:00
Nguyen Anh Quynh
dab17fd0b1 set @insn to NULL on error in cs_disasm_ex() 2014-06-19 11:15:18 +08:00
Nguyen Anh Quynh
11bb56f04d Merge branch 'opsize' of https://github.com/aquynh/capstone into opsize 2014-06-18 21:52:53 +08:00
Nguyen Anh Quynh
369ecf66f6 Merge branch 'next' into opsize 2014-06-18 21:52:10 +08:00
Nguyen Anh Quynh
6c182aedcf fix a memleaking issue in cs_disasm_ex() where memory was not freed when input code is illegit 2014-06-18 21:50:25 +08:00
Nguyen Anh Quynh
09132bf5d6 Merge branch 'next' into opsize 2014-06-18 15:39:58 +08:00
Nguyen Anh Quynh
cb6fc59da1 remove redundant return in MCInst_Init() 2014-06-18 15:39:00 +08:00
Nguyen Anh Quynh
1e688d4ff9 x86: do not use markup in AT&T syntax 2014-06-18 14:28:55 +08:00
Nguyen Anh Quynh
46291c139f Merge branch 'next' into opsize 2014-06-18 14:21:49 +08:00
Nguyen Anh Quynh
83800cdc31 python & java: add comments on operand's size 2014-06-18 14:21:36 +08:00
Nguyen Anh Quynh
44db3c37fa x86: support CS_OPT_MODE for dynamically changing mode at run-time 2014-06-18 14:18:47 +08:00
Nguyen Anh Quynh
cff03629ac arm64: assign NULL to char pointer, not zero. bug reported by Coverity 2014-06-18 14:04:42 +08:00
Nguyen Anh Quynh
e68ce0ecc8 java: update after the last change in x86 core 2014-06-18 12:33:39 +08:00
Nguyen Anh Quynh
e792451cce python: update after the last change in x86 core 2014-06-18 12:27:54 +08:00
Nguyen Anh Quynh
1085073f8f x86: remove disp_size, imm_size, op_size. add size to each operand. thanks Gabriel Quadros for some nice ideas 2014-06-18 12:16:24 +08:00
Nguyen Anh Quynh
7ae389ede8 suite: support XCore in fuzz.py 2014-06-17 18:17:59 +08:00
Nguyen Anh Quynh
6a5cc570cc suite: support XCore in benchmark.py 2014-06-17 18:17:26 +08:00
Nguyen Anh Quynh
73eb5d5486 arm: op_addImm() is called only when detail mode is ON 2014-06-17 18:08:29 +08:00
Nguyen Anh Quynh
b287301ef4 bump number of operands supported by MCInst to 48. this fixes a segfault in ARM 2014-06-17 17:19:11 +08:00
Nguyen Anh Quynh
476d5ad7a5 msvc: disable warning on strcpy() 2014-06-17 15:09:59 +08:00
Nguyen Anh Quynh
cae09bf543 replace offset_of with offsetof from stddef.h 2014-06-17 14:58:39 +08:00
Nguyen Anh Quynh
4fe59955d6 python: test_detail.py print groups with space delimiter 2014-06-17 13:59:08 +08:00
Nguyen Anh Quynh
ebe2443b9b arm: some special instructions need to have numerical operand added manually in printInstruction() 2014-06-17 13:56:01 +08:00
Nguyen Anh Quynh
eccb9da7a8 arm64: zeroout a whole cs_arm64 struct of MCI in *getInstruction(). 2014-06-17 13:34:25 +08:00
Nguyen Anh Quynh
aaddb25453 no need to zeroout insn_cache in make_id2insn() 2014-06-17 13:32:37 +08:00
Nguyen Anh Quynh
73bbbb3800 arm: add ASRS, LSRS, VCLE, VCLT instructions. update Python & Java bindings at the same time 2014-06-17 13:29:54 +08:00
Nguyen Anh Quynh
8693fcdc99 arm: correct operand setup for REG type in printAddrMode3OffsetOperand() 2014-06-17 13:28:33 +08:00
Nguyen Anh Quynh
2a461ed422 arm: zeroout a whole cs_arm struct in *getInstruction(). this makes sure operand of REG type has shift type = 0 by default 2014-06-17 13:27:38 +08:00
Nguyen Anh Quynh
9672cd259a update README 2014-06-16 22:06:44 +08:00
Nguyen Anh Quynh
6217f36d12 update README 2014-06-16 18:38:32 +08:00
Nguyen Anh Quynh
64091f77e0 resize total memory allocated for @insns to just the right size for cs_disasm_ex() 2014-06-16 18:37:11 +08:00
Nguyen Anh Quynh
9cf88119fb x86: InternalInstruction@xAcquireRelease should be initialized to 0 (FALSE) 2014-06-16 18:32:34 +08:00
Nguyen Anh Quynh
fec5539f3a use calloc() to zerout insn_cache in make_id2insn. this makes sure uninitialized data zero 2014-06-16 17:31:43 +08:00
Nguyen Anh Quynh
495295ecd4 MCInst_Init() is arch-independent 2014-06-16 15:54:32 +08:00
Nguyen Anh Quynh
370b7d7d4e remove unused MCInst/MCOperand functions 2014-06-16 14:57:07 +08:00