mirror of
https://github.com/capstone-engine/capstone.git
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ef89b18a88
* Update sysop inc file
* Fix missing braces warning
* Handle new system operands
* Fix build errors by renaming.
* Fix segfault
* Fix segfault
* Add custom MCOperand valiadtors
* Add AArch64 case for getFeatureBits
* Fix infinite loop
* Fix braces warning.
* Implement loopuo by name for sys operands
* Fix incorrect translation which remove else if statements.
* Fix several segfaults
* Rename GetRegFromClass patch
* Fix segfaults and asserts
* Fix segfault
* Move MRI setting to Mapping
* Remove unused code
* Add add_op_X functinos for AArch64.
* Add fill detail functins
* Handle RegWithShiftExtend operands
* Handle TypedVectorList operands.
* Handle ComplexRoatation operands
* Handle MemExtend operands
* Handle ImmRangeScale operands
* Handle ExactFPImm operands
* Handle GPRSeqPairsClass operands
* Handle Imm8OptLsl operands
* Handle ImmScale operands
* Handle LogicalImm operands
* Handle Matrix operands
* Handle SME Matrix tiles and vectors.
* Handle normal operands.
* Fix segfault.
* Handle PostInc operands.
* Reorder VecLayout enum to have no duplicate enum value.
* Handle PredicateAsCounter operands
* Handle ZPRasFPR operands
* Handle VectorIndex operands
* Handle UImm12Offset operands.
* Move reg suffix to enum val to single function.
* Handle SVERegOp operands
* Handle SVELogicalImm operands
* Handle SImm operand
* Handle PrefetchOp operands
* Handle Imm and ImmHex operands
* Handle GPR64as32 and GPR64x8 operands
* Add missing break
* Handle FPImm operand
* Handle ExtendedRegister opreand
* Handle CondCode operands
* Handle BTIHintOp operands
* Handle BarrierOption operands
* Handle BarrierXSOption
* Add not implemeted case again
* Handle ArithExtend operands
* Handle AdrpLabel and AlignedLabel operands
* Handle AMNoIndex operands
* Handle AddSubImm operands
* Handle MSRSystemRegisters and MRSSystemRegister operands
* Handle PSBHntOp and RPRFMOperand operands
* Remove unused variables
* Handle InverseCondCode operands
* Handle ImplicityTypedVectorList operands
* Handle ShiftedRegister operands
* Handle Shifter operands
* Handle SIMDType10Operand operands
* Handle SVCROp operands
* Handle SVEPattern operands
* Handle SVEVecLenSpecifier operands
* Handle SysCROperands
* Handle SysXzrPair operands
* Handle PState operands
* Handle VRegOperands
* Primt SME oeprands.
* Fix cs_operand.h include
* Rename arm64 -> aarch64 in python bindings.
* Add Python bindings for SH
* Fix ARM Python bindings (#2127)
* Restructure auto-sync update scripts.
* Move Helper functions to Updater dir
* Move requirements.txt
* Add basic ASUpdater.py
* Run black.
* Add inc file generater to updater
* Add option to select certain inc files fore generation.
* Enable clean build and implement patcher for inc files.
* Format config
* Patch main header files after inc generation.
* Implement clang-format function (unused yet, because it takes forever.)
* Copy generated inc files to arch dir
* Invert clean option (noramlly we need to clean the build dir.)
* Clearify arg doc
* Rename SystemRegister file for AArch64
* Centralize handling of path variables.
* Check if SystemOperands had to be generated before renaming on of its files.
* Replace class parameters by calling get_path
* Remove updater config which only contained paths.
* Add refactor option.
* Remove more path handling in the Configurator.
* Add translation step to updater.
* Fix includes after CppTranslator was moved into the Updater
* Remove updater config
* Fix several issue in the Configurator
* Fix file operations
* Remove addition argument from translator.
* Add Differ step to updater.
* Add path variable for arch_config
* Add diff step.
* Fix typo
* Introduce .clang-format path variable.
* Remove duplicate functions
* Add option to select update steps to execute.
* Check in write functions for write flag.
* Rename PatchMainHeader -> HeaderPatcher
* Move .gitignore
* Add README to vendor dir.
* Add all system operands to cstool output
* Update cstest with aarch64 changes
* Remove wb flag of aarch64 detail struct
* Set updates_flag after decoding
* Set writeback after decoding.
* Rename ARM64 -> AArch64
* Update printer and op mapping
* Exit normally
* Add AArch64 alias
* Fix some tmeplate function calls
* Fix flag check after rebase.
* Fix build by commentig unnused code.
* Add memory operand flag
* Handle memory operands printed via generic printOperand function.
* Handle UImm memory offsets
* Introduce MEM_REG and MEM_IMM op types
* Handle scaled memory immediates
* Check for op_count before checking for mem op at -1 index.
* Update memory operand flags.
* Pass imm/reg memory ops in set_imm/reg to set_mem.
* Add missing set_sme_operand call and fix assert.
* Remove CS_OP_MEM flag before entering switch.
* Preidcates are registers.
* Add shift info always to the previous operand
* Check for generic system regs
* Handle NumLanes = 0 LaneKind = q case
* Replace printImm call with normal print logic. Otherwise ops get added twice to detail.
* Handle FP operands in printOperand.
* Add access information to float operands.
* Rewrite SME matrix handling.
* Set correct SME layouts and allow for immediate range sme offsets.
* Handle cases of unknown system alias by setting their raw values
* Update cstool and header file with new SME offset handling
* Handle SME Tile lists.
* Fix build error in cstest
* Update MC tests for AArch64
* Handle TLBI operands and fix printing bug.
* Fix: Print signed value as signed.
* Add more system alias to detail.
* Remove duplicate hex prefix
* Set correct values for the register info
* Replace tabs with white spaces
* Move string append logic to own function.
* Set DecodeComplete = true before decoding (as originally in the LLVM code).
* Change type of feature argument, since only LLVM features are passed, not CS groups.
* Imitate lower_bound for the index table binary search.
* Remove trailing comments from test files.
* Print shift amount in decimal
* Save detail of shift alias instructions.
* Add extension details fot ext instruction alias
* Print LSB and width in decimal
* Fix LLVM bug. The feature check for V8_2a doesn't check if all features are enabled.
* Fix lower_bounds check.
For m == 0 we wrap around 0 of cause.
* Fix feature check. Add check for FeatureAll since it includes XS
* Operate on temporary MCInst when trying decoding.
* Add lower_bound behavior to IndexTypeStr binsearch.
* Fix MC tests which were incorrect because of missing FeatureAll check
* Add Alias handling for AArch64
* Update system operands with SYSIMM types and add additional sysop category.
* Add macros for meta programming (ARM64 <-> AArch64 selection).
* Fix union/struct confusion and add raw_value member to uninions.
* Allow to set Syntax and mode options for AArch64
* Fix build warning by using correct type
* Print shift value in decimal
* Add missing call to add_cs_detail.
* Update name map files with normalized names.
* Remove unused function
* Add check if detail should be filled.
* Fill detail for real instructions if only real detail is requested.
* Add always the extension.
* Make dir creation log message debug level
* Implement ADR immediate operand printer.
See: c3484b1fdc
* Check for flag registers beeing written and update flag.
* Move multiple CondCode helpers to aarch64.h because they are so freaking useful.
+ Print CC if it is EQ
* Fix incorrectly initialized CC and VectorLayout.
* Add LSL shift type for extensions.
* Fix case when shift amount is 0
* Fix post-index memory instructions.
* Pass raw immediate through getShiftValue to extract actual shift amount
* Setup AArch64 detail ops.
* Add flag for operands part of a list.
* Set vector indices for all relevant registers.
* Add missing call to add_cs_detail for postIncOperands
* Add ugly yet reliable way to determine post-index addressing mode
* Add support for old Capstone register alias.
* Remove leading space before some alias mnemonics.
* add AARCH64 to `cmake.sh`
* add HAS_AARCH64 to `cs.c`
* should probably just reference `cs_operand.h` in `aarch64.h`
* hint compiler at `AArch64_SYSREG` enum type for casting purposes
* update `Makefile` for AARCH64
leaves `CAPSTONE_HAS_ARM64` supported
* `testFeatureBits` platform function check
`testFeatureBits` should check if the platform function is visible first
* update tests to use AARCH64 convention
* hack: avoid enum casts for `MCInst` Values
Apple compiler really hates typecasting a enum, even if bounded from a unsigned. Lets set the raw_value directly
is a hack and needs proper review
* Check for present detail before accessing it.
* Add CS only groups
* Use general map ins_op type
* Fix build warning about str size computation.
* Disable warning about unitialized value for GCC 11.
Imm is initialized and the warning does not appear
in later versions.
* Use correct include guard for PPC
* Add missing requirements
* Update SystemOperand enums.
* Fix overlapping comparison warning
* Fix reachable assert where OpNum is not of type IMM
* Handle 0.0 operand for fcmp
* Fix incorrect variable passed.
* Fix for MacOS which doesn't know the warning and throws another one.
* Make getExtendEncoding static to fix build warning on MSVC.
* Fix build error: 'missing binary operator before token' by checking __GNUC__
* Add string search to add vector layout info.
* Add missing mem disponents of several ldr and str instructions.
* Add 0 immediates to several instructions.
* Rename v regs to q and d variant.
The cs_regname API can not pass the variant name of the register requested.
So we simply emit the default variant name.
* Fix incorrect enum value.
* Fix tests for system operands.
* Fix syntax issues in tests.
* Rename Arm64 -> AArch64 Python bindings.
* Fix Python bindings C structs.
* Fix generation of constants (ARMCC skipped because it starts with ARM)
* Update const files
* Remove -Wmaybe-uninitialized warning since it fails fuzz build
* Add missing comma
* Fix case
* Fix AArch64 Python bindings:
- Do not generate constants automatically (dscript is way too buggy).
- Update printing of details.
* Rename ARM64 -> AArch64 in test_corpus.py
* Rename test_arm64 -> test_aarch64
* Rename ARM-64 -> AArch64
* Fix diff CI test by disassembling AArch64 at former ARM64 place
* Fix several wrong types and remove unnecessary memebers from Python binding
* Fix: Same printing format of detail for cstool, test_ and test_*.py
* Fix: pass correct op index for mov alias with op[1] == reg wzr.
* Set prfm op manuall in case of unnown sysop. set_imm would add it to an memory operand wihtout base.
* Fix: If barrier ops are not set an assert is reached.
We fix it here by simply getting the immediate as the printing code does.
---------
Co-authored-by: Peace-Maker <peace-maker@wcfan.de>
Co-authored-by: Dayton <5340801+watbulb@users.noreply.github.com>
130 lines
3.6 KiB
Python
Executable File
130 lines
3.6 KiB
Python
Executable File
#!/usr/bin/python
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# Simple benchmark for Capstone by disassembling random code. By Nguyen Anh Quynh, 2014
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# Syntax:
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# ./suite/benchmark.py --> Benchmark all archs
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# ./suite/benchmark.py x86 --> Benchmark all X86 (all 16bit, 32bit, 64bit)
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# ./suite/benchmark.py x86-32 --> Benchmark X86-32 arch only
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# ./suite/benchmark.py arm --> Benchmark all ARM (arm, thumb)
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# ./suite/benchmark.py aarch64 --> Benchmark ARM-64
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# ./suite/benchmark.py mips --> Benchmark all Mips (32bit, 64bit)
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# ./suite/benchmark.py ppc --> Benchmark PPC
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from capstone import *
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from time import time
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from random import randint
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import sys
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# file providing code to disassemble
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FILE = '/usr/bin/python'
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all_tests = (
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(CS_ARCH_X86, CS_MODE_16, "X86-16 (Intel syntax)", 0),
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(CS_ARCH_X86, CS_MODE_32, "X86-32 (ATT syntax)", CS_OPT_SYNTAX_ATT),
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(CS_ARCH_X86, CS_MODE_32, "X86-32 (Intel syntax)", 0),
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(CS_ARCH_X86, CS_MODE_64, "X86-64 (Intel syntax)", 0),
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(CS_ARCH_ARM, CS_MODE_ARM, "ARM", 0),
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(CS_ARCH_ARM, CS_MODE_THUMB, "THUMB (ARM)", 0),
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(CS_ARCH_MIPS, CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN, "MIPS-32 (Big-endian)", 0),
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(CS_ARCH_MIPS, CS_MODE_MIPS64 + CS_MODE_LITTLE_ENDIAN, "MIPS-64-EL (Little-endian)", 0),
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(CS_ARCH_AARCH64, CS_MODE_ARM, "ARM-64 (AArch64)", 0),
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(CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, "PPC", 0),
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(CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, "PPC, print register with number only", CS_OPT_SYNTAX_NOREGNAME),
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(CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, "Sparc", 0),
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(CS_ARCH_SYSZ, 0, "SystemZ", 0),
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(CS_ARCH_XCORE, 0, "XCore", 0),
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(CS_ARCH_M68K, 0, "M68K", 0),
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(CS_ARCH_RISCV, 0, "RISCV", 0),
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)
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# for debugging
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def to_hex(s):
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return " ".join("0x" + "{0:x}".format(ord(c)).zfill(2) for c in s) # <-- Python 3 is OK
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def get_code(f, size):
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code = f.read(size)
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if len(code) != size: # reached end-of-file?
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# then reset file position to begin-of-file
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f.seek(0)
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code = f.read(size)
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return code
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def cs(md, code):
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insns = md.disasm(code, 0)
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# uncomment below line to speed up this function 200 times!
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# return
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for i in insns:
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if i.address == 0x100000:
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print i
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def cs_lite(md, code):
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insns = md.disasm_lite(code, 0)
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for (addr, size, mnem, ops) in insns:
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if addr == 0x100000:
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print i
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cfile = open(FILE)
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for (arch, mode, comment, syntax) in all_tests:
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try:
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request = sys.argv[1]
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if not request in comment.lower():
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continue
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except:
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pass
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print("Platform: %s" %comment)
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try:
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md = Cs(arch, mode)
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#md.detail = True
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if syntax != 0:
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md.syntax = syntax
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# warm up few times
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cfile.seek(0)
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for i in xrange(3):
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code = get_code(cfile, 128)
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#print to_hex(code)
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#print
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cs(md, code)
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# start real benchmark
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c_t = 0
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for i in xrange(50000):
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code = get_code(cfile, 128)
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#print to_hex(code)
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#print
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t1 = time()
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cs(md, code)
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c_t += time() - t1
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print "Benchmark - full obj:", c_t, "seconds"
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print
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cfile.seek(0)
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c_t = 0
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for i in xrange(50000):
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code = get_code(cfile, 128)
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#print to_hex(code)
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#print
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t1 = time()
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cs_lite(md, code)
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c_t += time() - t1
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print "Benchmark - lite:", c_t, "seconds"
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print
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except CsError as e:
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print("ERROR: %s" %e)
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