capstone/suite/fuzz/platform.c
Rot127 ef89b18a88 Architecture updater (auto-sync) - Updating AArch64 (#2026)
* Update sysop inc file

* Fix missing  braces warning

* Handle new system operands

* Fix build errors by renaming.

* Fix segfault

* Fix segfault

* Add custom MCOperand valiadtors

* Add AArch64 case for getFeatureBits

* Fix infinite loop

* Fix braces warning.

* Implement loopuo by name for sys operands

* Fix incorrect translation which remove else if statements.

* Fix several segfaults

* Rename GetRegFromClass patch

* Fix segfaults and asserts

* Fix segfault

* Move MRI setting to Mapping

* Remove unused code

* Add add_op_X functinos for AArch64.

* Add fill detail functins

* Handle RegWithShiftExtend operands

* Handle TypedVectorList operands.

* Handle ComplexRoatation operands

* Handle MemExtend operands

* Handle ImmRangeScale operands

* Handle ExactFPImm operands

* Handle GPRSeqPairsClass operands

* Handle Imm8OptLsl operands

* Handle ImmScale operands

* Handle LogicalImm operands

* Handle Matrix operands

* Handle SME Matrix tiles and vectors.

* Handle normal operands.

* Fix segfault.

* Handle PostInc operands.

* Reorder VecLayout enum to have no duplicate enum value.

* Handle PredicateAsCounter operands

* Handle ZPRasFPR operands

* Handle VectorIndex operands

* Handle UImm12Offset operands.

* Move reg suffix to enum val to single function.

* Handle SVERegOp operands

* Handle SVELogicalImm operands

* Handle SImm operand

* Handle PrefetchOp operands

* Handle Imm and ImmHex operands

* Handle GPR64as32 and GPR64x8 operands

* Add missing break

* Handle FPImm operand

* Handle ExtendedRegister opreand

* Handle CondCode operands

* Handle BTIHintOp operands

* Handle BarrierOption operands

* Handle BarrierXSOption

* Add not implemeted case again

* Handle ArithExtend operands

* Handle AdrpLabel and AlignedLabel operands

* Handle AMNoIndex operands

* Handle AddSubImm operands

* Handle MSRSystemRegisters and MRSSystemRegister operands

* Handle PSBHntOp and RPRFMOperand operands

* Remove unused variables

* Handle InverseCondCode operands

* Handle ImplicityTypedVectorList operands

* Handle ShiftedRegister operands

* Handle Shifter operands

* Handle SIMDType10Operand operands

* Handle SVCROp operands

* Handle SVEPattern operands

* Handle SVEVecLenSpecifier operands

* Handle SysCROperands

* Handle SysXzrPair operands

* Handle PState operands

* Handle VRegOperands

* Primt SME oeprands.

* Fix cs_operand.h include

* Rename arm64 -> aarch64 in python bindings.

* Add Python bindings for SH

* Fix ARM Python bindings (#2127)

* Restructure auto-sync update scripts.

* Move Helper functions to Updater dir

* Move requirements.txt

* Add basic ASUpdater.py

* Run black.

* Add inc file generater to updater

* Add option to select certain inc files fore generation.

* Enable clean build and implement patcher for inc files.

* Format config

* Patch main header files after inc generation.

* Implement clang-format function (unused yet, because it takes forever.)

* Copy generated inc files to arch dir

* Invert clean option (noramlly we need to clean the build dir.)

* Clearify arg doc

* Rename SystemRegister file for AArch64

* Centralize handling of path variables.

* Check if SystemOperands had to be generated before renaming on of its files.

* Replace class parameters by calling get_path

* Remove updater config which only contained paths.

* Add refactor option.

* Remove more path handling in the Configurator.

* Add translation step to updater.

* Fix includes after CppTranslator was moved into the Updater

* Remove updater config

* Fix several issue in the Configurator

* Fix file operations

* Remove addition argument from translator.

* Add Differ step to updater.

* Add path variable for arch_config

* Add diff step.

* Fix typo

* Introduce .clang-format path variable.

* Remove duplicate functions

* Add option to select update steps to execute.

* Check in write functions for write flag.

* Rename PatchMainHeader -> HeaderPatcher

* Move .gitignore

* Add README to vendor dir.

* Add all system operands to cstool output

* Update cstest with aarch64 changes

* Remove wb flag of aarch64 detail struct

* Set updates_flag after decoding

* Set writeback after decoding.

* Rename ARM64 -> AArch64

* Update printer and op mapping

* Exit normally

* Add AArch64 alias

* Fix some tmeplate function calls

* Fix flag check after rebase.

* Fix build by commentig unnused code.

* Add memory operand flag

* Handle memory operands printed via generic printOperand function.

* Handle UImm memory offsets

* Introduce MEM_REG and MEM_IMM op types

* Handle scaled memory immediates

* Check for op_count before checking for mem op at -1 index.

* Update memory operand flags.

* Pass imm/reg memory ops in set_imm/reg to set_mem.

* Add missing set_sme_operand call and fix assert.

* Remove CS_OP_MEM flag before entering switch.

* Preidcates are registers.

* Add shift info always to the previous operand

* Check for generic system regs

* Handle NumLanes = 0 LaneKind = q case

* Replace printImm call with normal print logic. Otherwise ops get added twice to detail.

* Handle FP operands in printOperand.

* Add access information to float operands.

* Rewrite SME matrix handling.

* Set correct SME layouts and allow for immediate range sme offsets.

* Handle cases of unknown system alias by setting their raw values

* Update cstool and header file with new SME offset handling

* Handle SME Tile lists.

* Fix build error in cstest

* Update MC tests for AArch64

* Handle TLBI operands and fix printing bug.

* Fix: Print signed value as signed.

* Add more system alias to detail.

* Remove duplicate hex prefix

* Set correct values for the register info

* Replace tabs with white spaces

* Move string append logic to own function.

* Set DecodeComplete = true before decoding (as originally in the LLVM code).

* Change type of feature argument, since only LLVM features are passed, not CS groups.

* Imitate lower_bound for the index table binary search.

* Remove trailing comments from test files.

* Print shift amount in decimal

* Save detail of shift alias instructions.

* Add extension details fot ext instruction alias

* Print LSB and width in decimal

* Fix LLVM bug. The feature check for V8_2a doesn't check if all features are enabled.

* Fix lower_bounds check.
For m == 0 we wrap around 0 of cause.

* Fix feature check. Add check for FeatureAll since it includes XS

* Operate on temporary MCInst when trying decoding.

* Add lower_bound behavior to IndexTypeStr binsearch.

* Fix MC tests which were incorrect because of missing FeatureAll check

* Add Alias handling for AArch64

* Update system operands with SYSIMM types and add additional sysop category.

* Add macros for meta programming (ARM64 <-> AArch64 selection).

* Fix union/struct confusion and add raw_value member to uninions.

* Allow to set Syntax and mode options for AArch64

* Fix build warning by using correct type

* Print shift value in decimal

* Add missing call to add_cs_detail.

* Update name map files with normalized names.

* Remove unused function

* Add check if detail should be filled.

* Fill detail for real instructions if only real detail is requested.

* Add always the extension.

* Make dir creation log message debug level

* Implement ADR immediate operand printer.

See: c3484b1fdc

* Check for flag registers beeing written and update flag.

* Move multiple CondCode helpers to aarch64.h because they are so freaking useful.

+ Print CC if it is EQ

* Fix incorrectly initialized CC and VectorLayout.

* Add LSL shift type for extensions.

* Fix case when shift amount is 0

* Fix post-index memory instructions.

* Pass raw immediate through getShiftValue to extract actual shift amount

* Setup AArch64 detail ops.

* Add flag for operands part of a list.

* Set vector indices for all relevant registers.

* Add missing call to add_cs_detail for postIncOperands

* Add ugly yet reliable way to determine post-index addressing mode

* Add support for old Capstone register alias.

* Remove leading space before some alias mnemonics.

* add AARCH64 to `cmake.sh`

* add HAS_AARCH64 to `cs.c`

* should probably just reference `cs_operand.h` in `aarch64.h`

* hint compiler at `AArch64_SYSREG` enum type for casting purposes

* update `Makefile` for AARCH64

leaves `CAPSTONE_HAS_ARM64` supported

* `testFeatureBits` platform function check

`testFeatureBits` should check if the platform function is visible first

* update tests to use AARCH64 convention

* hack: avoid enum casts for `MCInst` Values

Apple compiler really hates typecasting a enum, even if bounded from a unsigned. Lets set the raw_value directly

is a hack and needs proper review

* Check for present detail before accessing it.

* Add CS only groups

* Use general map ins_op type

* Fix build warning about str size computation.

* Disable warning about unitialized value for GCC 11.

Imm is initialized and the warning does not appear
in later versions.

* Use correct include guard for PPC

* Add missing requirements

* Update SystemOperand enums.

* Fix overlapping comparison warning

* Fix reachable assert where OpNum is not of type IMM

* Handle 0.0 operand for fcmp

* Fix incorrect variable passed.

* Fix for MacOS which doesn't know the warning and throws another one.

* Make getExtendEncoding static to fix build warning on MSVC.

* Fix build error: 'missing binary operator before token' by checking __GNUC__

* Add string search to add vector layout info.

* Add missing mem disponents of several ldr and str instructions.

* Add 0 immediates to several instructions.

* Rename v regs to q and d variant.

The cs_regname API can not pass the variant name of the register requested.
So we simply emit the default variant name.

* Fix incorrect enum value.

* Fix tests for system operands.

* Fix syntax issues in tests.

* Rename Arm64 -> AArch64 Python bindings.

* Fix Python bindings C structs.

* Fix generation of constants (ARMCC skipped because it starts with ARM)

* Update const files

* Remove -Wmaybe-uninitialized warning since it fails fuzz build

* Add missing comma

* Fix case

* Fix AArch64 Python bindings:

- Do not generate constants automatically (dscript is way too buggy).
- Update printing of details.

* Rename ARM64 -> AArch64 in test_corpus.py

* Rename test_arm64 -> test_aarch64

* Rename ARM-64 -> AArch64

* Fix diff CI test by disassembling AArch64 at former ARM64 place

* Fix several wrong types and remove unnecessary memebers from Python binding

* Fix: Same printing format of detail for cstool, test_ and test_*.py

* Fix: pass correct op index for mov alias with op[1] == reg wzr.

* Set prfm op manuall in case of unnown sysop. set_imm would add it to an memory operand wihtout base.

* Fix: If barrier ops are not set an assert is reached.

We fix it here by simply getting the immediate as the printing code does.

---------

Co-authored-by: Peace-Maker <peace-maker@wcfan.de>
Co-authored-by: Dayton <5340801+watbulb@users.noreply.github.com>
2023-11-15 12:12:14 +08:00

412 lines
6.5 KiB
C

#include "platform.h"
struct platform platforms[] = {
{
// item 0
CS_ARCH_X86,
CS_MODE_32,
"X86 32 (Intel syntax)",
"x32"
},
{
// item 1
CS_ARCH_X86,
CS_MODE_64,
"X86 64 (Intel syntax)",
"x64"
},
{
// item 2
CS_ARCH_ARM,
CS_MODE_ARM,
"ARM",
"arm"
},
{
// item 3
CS_ARCH_ARM,
CS_MODE_THUMB,
"THUMB",
"thumb"
},
{
// item 4
CS_ARCH_ARM,
(cs_mode) (CS_MODE_ARM + CS_MODE_V8),
"Arm-V8",
"armv8"
},
{
// item 5
CS_ARCH_ARM,
(cs_mode) (CS_MODE_THUMB + CS_MODE_V8),
"THUMB+V8",
"thumbv8"
},
{
// item 6
CS_ARCH_ARM,
(cs_mode) (CS_MODE_THUMB + CS_MODE_MCLASS),
"Thumb-MClass",
"cortexm"
},
{
// item 7
CS_ARCH_AARCH64,
(cs_mode) 0,
"AARCH64",
"aarch64"
},
{
// item 8
CS_ARCH_MIPS,
(cs_mode) (CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN),
"MIPS-32 (Big-endian)",
"mipsbe"
},
{
// item 9
CS_ARCH_MIPS,
(cs_mode) (CS_MODE_MIPS32 + CS_MODE_MICRO),
"MIPS-32 (micro)",
"mipsmicro"
},
{
//item 10
CS_ARCH_MIPS,
CS_MODE_MIPS64,
"MIPS-64-EL (Little-endian)",
"mips64"
},
{
//item 11
CS_ARCH_MIPS,
CS_MODE_MIPS32,
"MIPS-32-EL (Little-endian)",
"mips"
},
{
//item 12
CS_ARCH_MIPS,
(cs_mode) (CS_MODE_MIPS64 + CS_MODE_BIG_ENDIAN),
"MIPS-64 (Big-endian)",
"mips64be"
},
{
//item 13
CS_ARCH_MIPS,
(cs_mode) (CS_MODE_MIPS32 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN),
"MIPS-32 | Micro (Big-endian)",
"mipsbemicro"
},
{
//item 14
CS_ARCH_PPC,
CS_MODE_64 | CS_MODE_BIG_ENDIAN,
"PPC-64",
"ppc64be"
},
{
//item 15
CS_ARCH_SPARC,
CS_MODE_BIG_ENDIAN,
"Sparc",
"sparc"
},
{
//item 16
CS_ARCH_SPARC,
(cs_mode) (CS_MODE_BIG_ENDIAN + CS_MODE_V9),
"SparcV9",
"sparcv9"
},
{
//item 17
CS_ARCH_SYSZ,
(cs_mode) 0,
"SystemZ",
"systemz"
},
{
//item 18
CS_ARCH_XCORE,
(cs_mode) 0,
"XCore",
"xcore"
},
{
//item 19
CS_ARCH_MIPS,
(cs_mode) (CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN),
"MIPS-32R6 (Big-endian)",
"mipsbe32r6"
},
{
//item 20
CS_ARCH_MIPS,
(cs_mode) (CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN),
"MIPS-32R6 (Micro+Big-endian)",
"mipsbe32r6micro"
},
{
//item 21
CS_ARCH_MIPS,
CS_MODE_MIPS32R6,
"MIPS-32R6 (Little-endian)",
"mips32r6"
},
{
//item 22
CS_ARCH_MIPS,
(cs_mode) (CS_MODE_MIPS32R6 + CS_MODE_MICRO),
"MIPS-32R6 (Micro+Little-endian)",
"mips32r6micro"
},
{
//item 23
CS_ARCH_M68K,
(cs_mode) 0,
"M68K",
"m68k"
},
{
//item 24
CS_ARCH_M680X,
(cs_mode) CS_MODE_M680X_6809,
"M680X_M6809",
"m6809"
},
{
//item 25
CS_ARCH_EVM,
(cs_mode) 0,
"EVM",
"evm"
},
{
//item 26
CS_ARCH_MOS65XX,
(cs_mode) 0,
"MOS65XX",
"mos65xx"
},
{
//item 27
CS_ARCH_TMS320C64X,
CS_MODE_BIG_ENDIAN,
"tms320c64x",
"tms320c64x"
},
{
//item 28
CS_ARCH_WASM,
(cs_mode) 0,
"WASM",
"wasm"
},
{
//item 29
CS_ARCH_BPF,
CS_MODE_LITTLE_ENDIAN | CS_MODE_BPF_CLASSIC,
"cBPF",
"bpf"
},
{
//item 30
CS_ARCH_BPF,
CS_MODE_LITTLE_ENDIAN | CS_MODE_BPF_EXTENDED,
"eBPF",
"ebpf"
},
{
//item 31
CS_ARCH_BPF,
CS_MODE_BIG_ENDIAN | CS_MODE_BPF_CLASSIC,
"cBPF",
"bpfbe"
},
{
//item 32
CS_ARCH_BPF,
CS_MODE_BIG_ENDIAN | CS_MODE_BPF_EXTENDED,
"eBPF",
"ebpfbe"
},
{
// item 33
CS_ARCH_X86,
CS_MODE_16,
"X86 16 (Intel syntax)",
"x16"
},
{
// item 34
CS_ARCH_M68K,
CS_MODE_M68K_040,
"M68K mode 40",
"m68k40"
},
{
//item 35
CS_ARCH_M680X,
(cs_mode) CS_MODE_M680X_6800,
"M680X_M6800",
"m6800"
},
{
//item 36
CS_ARCH_M680X,
(cs_mode) CS_MODE_M680X_6801,
"M680X_M6801",
"m6801"
},
{
//item 37
CS_ARCH_M680X,
(cs_mode) CS_MODE_M680X_6805,
"M680X_M6805",
"m6805"
},
{
//item 38
CS_ARCH_M680X,
(cs_mode) CS_MODE_M680X_6808,
"M680X_M6808",
"m6808"
},
{
//item 39
CS_ARCH_M680X,
(cs_mode) CS_MODE_M680X_6811,
"M680X_M6811",
"m6811"
},
{
//item 40
CS_ARCH_M680X,
(cs_mode) CS_MODE_M680X_CPU12,
"M680X_cpu12",
"cpu12"
},
{
//item 41
CS_ARCH_M680X,
(cs_mode) CS_MODE_M680X_6301,
"M680X_M6808",
"hd6301"
},
{
//item 42
CS_ARCH_M680X,
(cs_mode) CS_MODE_M680X_6309,
"M680X_M6808",
"hd6309"
},
{
//item 43
CS_ARCH_M680X,
(cs_mode) CS_MODE_M680X_HCS08,
"M680X_M6808",
"hcs08"
},
{
//item 44
CS_ARCH_RISCV,
CS_MODE_RISCV32,
"RISCV",
"riscv32"
},
{
//item 45
CS_ARCH_RISCV,
CS_MODE_RISCV64,
"RISCV",
"riscv64"
},
{
//item 46
CS_ARCH_PPC,
CS_MODE_64 | CS_MODE_BIG_ENDIAN | CS_MODE_QPX,
"ppc+qpx",
"ppc64beqpx"
},
{
//item 46
CS_ARCH_PPC,
CS_MODE_32 | CS_MODE_BIG_ENDIAN | CS_MODE_PS,
"ppc+ps",
"ppc32beps"
},
{
CS_ARCH_TRICORE,
CS_MODE_32 | CS_MODE_BIG_ENDIAN | CS_MODE_TRICORE_110,
"TRICORE",
"tc110"
},
{
CS_ARCH_TRICORE,
CS_MODE_32 | CS_MODE_BIG_ENDIAN | CS_MODE_TRICORE_120,
"TRICORE",
"tc120"
},
{
CS_ARCH_TRICORE,
CS_MODE_32 | CS_MODE_BIG_ENDIAN | CS_MODE_TRICORE_130,
"TRICORE",
"tc130"
},
{
CS_ARCH_TRICORE,
CS_MODE_32 | CS_MODE_BIG_ENDIAN | CS_MODE_TRICORE_131,
"TRICORE",
"tc131"
},
{
CS_ARCH_TRICORE,
CS_MODE_32 | CS_MODE_BIG_ENDIAN | CS_MODE_TRICORE_160,
"TRICORE",
"tc160"
},
{
CS_ARCH_TRICORE,
CS_MODE_32 | CS_MODE_BIG_ENDIAN | CS_MODE_TRICORE_161,
"TRICORE",
"tc161"
},
{
CS_ARCH_TRICORE,
CS_MODE_32 | CS_MODE_BIG_ENDIAN | CS_MODE_TRICORE_162,
"TRICORE",
"tc162"
},
// dummy entry to mark the end of this array.
// DO NOT DELETE THIS
{
0,
0,
NULL,
NULL,
},
};
// get length of platforms[]
unsigned int platform_len(void) {
unsigned int c;
for (c = 0; platforms[c].cstoolname; c++);
return c;
}
// get platform entry encoded n (first byte for input data of OSS fuzz)
unsigned int get_platform_entry(uint8_t n) {
return n % platform_len();
}
// get cstoolname from encoded n (first byte for input data of OSS fuzz)
const char *get_platform_cstoolname(uint8_t n) {
return platforms[get_platform_entry(n)].cstoolname;
}