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936dca0e2d
* Constify registerinfo.py output Remove two conditionals separating identical bits of code. Add "const" markup to MCRegisterDesc and MCRegisterClass. Signed-off-by: Richard Henderson <rth@twiddle.net> * Constify instrinfo-arch.py output In this case, do not actively strip const. Signed-off-by: Richard Henderson <rth@twiddle.net> * Constify the AArch64 backend Signed-off-by: Richard Henderson <rth@twiddle.net> * Constify the EVM backend Signed-off-by: Richard Henderson <rth@twiddle.net> * Constify M680X backend Signed-off-by: Richard Henderson <rth@twiddle.net> * Constify M68K backend Signed-off-by: Richard Henderson <rth@twiddle.net> * Constify the Mips backend The Mips backend has not been regenerated from LLVM recently, and there are more fixups required than I'd like. Just apply the fixes to the tables by hand for now. Signed-off-by: Richard Henderson <rth@twiddle.net> * Constify the Sparc backend Signed-off-by: Richard Henderson <rth@twiddle.net> * Constify the TMS320C64x backend Signed-off-by: Richard Henderson <rth@twiddle.net> * Constify the X86 backend Signed-off-by: Richard Henderson <rth@twiddle.net> * Constify the XCore backend Signed-off-by: Richard Henderson <rth@twiddle.net> * Constify systemregister.py output Signed-off-by: Richard Henderson <rth@twiddle.net> * Constify the ARM backend Signed-off-by: Richard Henderson <rth@twiddle.net> * Constify the PowerPC backend Signed-off-by: Richard Henderson <rth@twiddle.net> * Constify the MOS65XX backend Signed-off-by: Richard Henderson <rth@twiddle.net> * Constify the SystemZ backend The mapping of system register to indexes is easy to generate read-only. Since we know the indexes are between 0 and 31, use uint8_t instead of unsigned. Signed-off-by: Richard Henderson <rth@twiddle.net> * Constify the WASM backend Signed-off-by: Richard Henderson <rth@twiddle.net> * Constify cs.c Signed-off-by: Richard Henderson <rth@twiddle.net> * Constify the BPF backend Signed-off-by: Richard Henderson <rth@twiddle.net>
95 lines
3.0 KiB
C
95 lines
3.0 KiB
C
/* Capstone Disassembly Engine */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
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#ifndef CS_X86_MAP_H
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#define CS_X86_MAP_H
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#include "capstone/capstone.h"
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#include "../../cs_priv.h"
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// map instruction to its characteristics
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typedef struct insn_map_x86 {
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unsigned short id;
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unsigned short mapid;
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unsigned char is64bit;
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#ifndef CAPSTONE_DIET
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uint16_t regs_use[12]; // list of implicit registers used by this instruction
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uint16_t regs_mod[20]; // list of implicit registers modified by this instruction
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unsigned char groups[8]; // list of group this instruction belong to
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bool branch; // branch instruction?
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bool indirect_branch; // indirect branch instruction?
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#endif
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} insn_map_x86;
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extern const insn_map_x86 insns[];
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// map sib_base to x86_reg
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x86_reg x86_map_sib_base(int r);
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// map sib_index to x86_reg
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x86_reg x86_map_sib_index(int r);
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// map seg_override to x86_reg
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x86_reg x86_map_segment(int r);
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// return name of regiser in friendly string
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const char *X86_reg_name(csh handle, unsigned int reg);
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// given internal insn id, return public instruction info
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void X86_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
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// return insn name, given insn id
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const char *X86_insn_name(csh handle, unsigned int id);
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// return group name, given group id
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const char *X86_group_name(csh handle, unsigned int id);
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// return register of given instruction id
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// return 0 if not found
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// this is to handle instructions embedding accumulate registers into AsmStrs[]
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x86_reg X86_insn_reg_intel(unsigned int id, enum cs_ac_type *access);
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x86_reg X86_insn_reg_att(unsigned int id, enum cs_ac_type *access);
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bool X86_insn_reg_intel2(unsigned int id, x86_reg *reg1, enum cs_ac_type *access1, x86_reg *reg2, enum cs_ac_type *access2);
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bool X86_insn_reg_att2(unsigned int id, x86_reg *reg1, enum cs_ac_type *access1, x86_reg *reg2, enum cs_ac_type *access2);
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extern const uint64_t arch_masks[9];
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// handle LOCK/REP/REPNE prefixes
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// return True if we patch mnemonic, like in MULPD case
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bool X86_lockrep(MCInst *MI, SStream *O);
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// map registers to sizes
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extern const uint8_t regsize_map_32[];
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extern const uint8_t regsize_map_64[];
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void op_addReg(MCInst *MI, int reg);
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void op_addImm(MCInst *MI, int v);
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void op_addAvxBroadcast(MCInst *MI, x86_avx_bcast v);
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void op_addXopCC(MCInst *MI, int v);
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void op_addSseCC(MCInst *MI, int v);
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void op_addAvxCC(MCInst *MI, int v);
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void op_addAvxZeroOpmask(MCInst *MI);
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void op_addAvxSae(MCInst *MI);
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void op_addAvxRoundingMode(MCInst *MI, int v);
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// given internal insn id, return operand access info
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const uint8_t *X86_get_op_access(cs_struct *h, unsigned int id, uint64_t *eflags);
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void X86_reg_access(const cs_insn *insn,
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cs_regs regs_read, uint8_t *regs_read_count,
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cs_regs regs_write, uint8_t *regs_write_count);
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// given the instruction id, return the size of its immediate operand (or 0)
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uint8_t X86_immediate_size(unsigned int id, uint8_t *enc_size);
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unsigned short X86_register_map(unsigned short id);
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unsigned int find_insn(unsigned int id);
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#endif
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