capstone/arch/X86/X86Mapping.h

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/* Capstone Disassembly Engine */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
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#ifndef CS_X86_MAP_H
#define CS_X86_MAP_H
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#include "capstone/capstone.h"
#include "../../cs_priv.h"
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// map instruction to its characteristics
typedef struct insn_map_x86 {
unsigned short id;
unsigned short mapid;
unsigned char is64bit;
#ifndef CAPSTONE_DIET
uint16_t regs_use[12]; // list of implicit registers used by this instruction
uint16_t regs_mod[20]; // list of implicit registers modified by this instruction
unsigned char groups[8]; // list of group this instruction belong to
bool branch; // branch instruction?
bool indirect_branch; // indirect branch instruction?
#endif
} insn_map_x86;
extern const insn_map_x86 insns[];
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// map sib_base to x86_reg
x86_reg x86_map_sib_base(int r);
// map sib_index to x86_reg
x86_reg x86_map_sib_index(int r);
// map seg_override to x86_reg
x86_reg x86_map_segment(int r);
// return name of regiser in friendly string
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const char *X86_reg_name(csh handle, unsigned int reg);
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// given internal insn id, return public instruction info
void X86_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
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// return insn name, given insn id
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const char *X86_insn_name(csh handle, unsigned int id);
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// return group name, given group id
const char *X86_group_name(csh handle, unsigned int id);
// return register of given instruction id
// return 0 if not found
// this is to handle instructions embedding accumulate registers into AsmStrs[]
x86_reg X86_insn_reg_intel(unsigned int id, enum cs_ac_type *access);
x86_reg X86_insn_reg_att(unsigned int id, enum cs_ac_type *access);
bool X86_insn_reg_intel2(unsigned int id, x86_reg *reg1, enum cs_ac_type *access1, x86_reg *reg2, enum cs_ac_type *access2);
bool X86_insn_reg_att2(unsigned int id, x86_reg *reg1, enum cs_ac_type *access1, x86_reg *reg2, enum cs_ac_type *access2);
Constify backend data (#1040) * Constify string literals Use -Wwrite-strings to force string literals to be of type "const char[]", then fix up all warning fallout. * Constify common infrastructure Step one in allowing backend data to be readonly. Minimal changes to backends for now; just set all pointers in common structs that aren't modified to const. * Constify AArch64 backend Section size changes within libcapstone.so are -.rodata 602587 -.data.rel.ro 228416 -.data 1003746 +.rodata 769051 +.data.rel.ro 241120 +.data 824578 * Constify ARM backend Section size changes within libcapstone.so are -.rodata 769051 -.data.rel.ro 241120 -.data 824578 +.rodata 959835 +.data.rel.ro 245120 +.data 629506 * Constify Mips backend Section size changes within libcapstone.so are -.rodata 959835 -.data.rel.ro 245120 -.data 629506 +.rodata 1069851 +.data.rel.ro 256416 +.data 508194 * Constify PowerPC backend Section size changes within libcapstone.so are -.rodata 1069851 -.data.rel.ro 256416 -.data 508194 +.rodata 1142715 +.data.rel.ro 272224 +.data 419490 * Constify Sparc backend Section size changes within libcapstone.so are -.rodata 1142715 -.data.rel.ro 272224 -.data 419490 +.rodata 1175227 +.data.rel.ro 277536 +.data 381666 * Constify SystemZ backend Section size changes within libcapstone.so are -.rodata 1175227 -.data.rel.ro 277536 -.data 381666 +.rodata 1221883 +.data.rel.ro 278016 +.data 334498 * Constify X86 backend Section size changes within libcapstone.so are -.rodata 1221883 -.data.rel.ro 278016 -.data 334498 +.rodata 1533531 +.data.rel.ro 281184 +.data 19714 * Constify XCore backend Section size changes within libcapstone.so are -.rodata 1533531 -.data.rel.ro 281184 -.data 19714 +.rodata 1553026 +.data.rel.ro 281280 +.data 40
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extern const uint64_t arch_masks[9];
// handle LOCK/REP/REPNE prefixes
// return True if we patch mnemonic, like in MULPD case
bool X86_lockrep(MCInst *MI, SStream *O);
// map registers to sizes
Constify backend data (#1040) * Constify string literals Use -Wwrite-strings to force string literals to be of type "const char[]", then fix up all warning fallout. * Constify common infrastructure Step one in allowing backend data to be readonly. Minimal changes to backends for now; just set all pointers in common structs that aren't modified to const. * Constify AArch64 backend Section size changes within libcapstone.so are -.rodata 602587 -.data.rel.ro 228416 -.data 1003746 +.rodata 769051 +.data.rel.ro 241120 +.data 824578 * Constify ARM backend Section size changes within libcapstone.so are -.rodata 769051 -.data.rel.ro 241120 -.data 824578 +.rodata 959835 +.data.rel.ro 245120 +.data 629506 * Constify Mips backend Section size changes within libcapstone.so are -.rodata 959835 -.data.rel.ro 245120 -.data 629506 +.rodata 1069851 +.data.rel.ro 256416 +.data 508194 * Constify PowerPC backend Section size changes within libcapstone.so are -.rodata 1069851 -.data.rel.ro 256416 -.data 508194 +.rodata 1142715 +.data.rel.ro 272224 +.data 419490 * Constify Sparc backend Section size changes within libcapstone.so are -.rodata 1142715 -.data.rel.ro 272224 -.data 419490 +.rodata 1175227 +.data.rel.ro 277536 +.data 381666 * Constify SystemZ backend Section size changes within libcapstone.so are -.rodata 1175227 -.data.rel.ro 277536 -.data 381666 +.rodata 1221883 +.data.rel.ro 278016 +.data 334498 * Constify X86 backend Section size changes within libcapstone.so are -.rodata 1221883 -.data.rel.ro 278016 -.data 334498 +.rodata 1533531 +.data.rel.ro 281184 +.data 19714 * Constify XCore backend Section size changes within libcapstone.so are -.rodata 1533531 -.data.rel.ro 281184 -.data 19714 +.rodata 1553026 +.data.rel.ro 281280 +.data 40
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extern const uint8_t regsize_map_32[];
extern const uint8_t regsize_map_64[];
void op_addReg(MCInst *MI, int reg);
void op_addImm(MCInst *MI, int v);
void op_addAvxBroadcast(MCInst *MI, x86_avx_bcast v);
void op_addXopCC(MCInst *MI, int v);
void op_addSseCC(MCInst *MI, int v);
void op_addAvxCC(MCInst *MI, int v);
void op_addAvxZeroOpmask(MCInst *MI);
void op_addAvxSae(MCInst *MI);
void op_addAvxRoundingMode(MCInst *MI, int v);
// given internal insn id, return operand access info
Constify backends (#1549) * Constify registerinfo.py output Remove two conditionals separating identical bits of code. Add "const" markup to MCRegisterDesc and MCRegisterClass. Signed-off-by: Richard Henderson <rth@twiddle.net> * Constify instrinfo-arch.py output In this case, do not actively strip const. Signed-off-by: Richard Henderson <rth@twiddle.net> * Constify the AArch64 backend Signed-off-by: Richard Henderson <rth@twiddle.net> * Constify the EVM backend Signed-off-by: Richard Henderson <rth@twiddle.net> * Constify M680X backend Signed-off-by: Richard Henderson <rth@twiddle.net> * Constify M68K backend Signed-off-by: Richard Henderson <rth@twiddle.net> * Constify the Mips backend The Mips backend has not been regenerated from LLVM recently, and there are more fixups required than I'd like. Just apply the fixes to the tables by hand for now. Signed-off-by: Richard Henderson <rth@twiddle.net> * Constify the Sparc backend Signed-off-by: Richard Henderson <rth@twiddle.net> * Constify the TMS320C64x backend Signed-off-by: Richard Henderson <rth@twiddle.net> * Constify the X86 backend Signed-off-by: Richard Henderson <rth@twiddle.net> * Constify the XCore backend Signed-off-by: Richard Henderson <rth@twiddle.net> * Constify systemregister.py output Signed-off-by: Richard Henderson <rth@twiddle.net> * Constify the ARM backend Signed-off-by: Richard Henderson <rth@twiddle.net> * Constify the PowerPC backend Signed-off-by: Richard Henderson <rth@twiddle.net> * Constify the MOS65XX backend Signed-off-by: Richard Henderson <rth@twiddle.net> * Constify the SystemZ backend The mapping of system register to indexes is easy to generate read-only. Since we know the indexes are between 0 and 31, use uint8_t instead of unsigned. Signed-off-by: Richard Henderson <rth@twiddle.net> * Constify the WASM backend Signed-off-by: Richard Henderson <rth@twiddle.net> * Constify cs.c Signed-off-by: Richard Henderson <rth@twiddle.net> * Constify the BPF backend Signed-off-by: Richard Henderson <rth@twiddle.net>
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const uint8_t *X86_get_op_access(cs_struct *h, unsigned int id, uint64_t *eflags);
void X86_reg_access(const cs_insn *insn,
cs_regs regs_read, uint8_t *regs_read_count,
cs_regs regs_write, uint8_t *regs_write_count);
// given the instruction id, return the size of its immediate operand (or 0)
uint8_t X86_immediate_size(unsigned int id, uint8_t *enc_size);
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unsigned short X86_register_map(unsigned short id);
unsigned int find_insn(unsigned int id);
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#endif