capstone/suite/MC
2023-09-05 12:24:59 +08:00
..
AArch64 Updated AArch64 tests to match corrections to instruction aliases. 2022-09-30 16:46:49 +01:00
ARM Fix running cstest in CI (#2126) 2023-08-06 18:28:52 +08:00
BPF Merge pull request #1886 from terorie/ebpf-callx 2022-06-09 21:37:40 +08:00
Mips fix MC 2019-02-26 15:41:04 +08:00
PowerPC Architecture updater (auto-sync) - Updating PPC (#2013) 2023-09-05 12:24:59 +08:00
RISCV RISCV support ISRV32/ISRV64 (#1401) 2019-03-09 08:41:12 +08:00
Sparc fix MC 2019-02-26 15:41:04 +08:00
SystemZ fix MC 2019-02-26 15:41:04 +08:00
TriCore Fixing TriCore disasm instructions (#2088) 2023-07-26 14:47:05 +08:00
X86 x86: fix testcase of MOVSD 2020-05-07 21:51:54 +08:00
README Architecture updater (auto-sync) - Updating ARM (#1949) 2023-07-19 17:56:27 +08:00
Update.py Architecture updater (auto-sync) - Updating ARM (#1949) 2023-07-19 17:56:27 +08:00

## Input files for testing Capstone engine.

Input files used to test instructions of architectures and modes.

The test cases are taken from `llvm/test/MC`. Note that the LLVM tests
are for **encoding** of instructions (`asm_string -> bytes`).

We test the decoding (`bytes -> asm_string`).
A few tests might decode to a different asm string than
used to encode the instruction (because the behavior
of instructions can be equivalent).

Fix the obvious broken tests first and test the rest
against `llvm-objdump`.

### Update test files

Run the update script with the paths to LLVM's `MC` test directories

```
cd capstone/suite/MC
./Update.py -a <ARCH> -d llvm-project/llvm/test/MC
./Update.py -a <ARCH> -d llvm-project/llvm/test/MC/Disassembler
```

You can update more fine grained. Check the help to get the possible options.

### Test file formatting

**Format of input files:**
```
# ARCH, MODE, OPTION
hexcode = assembly
```

**Example**
```
# CS_ARCH_ARM, CS_MODE_ARM+CS_MODE_V8, None
0xa0,0x0b,0x71,0xee = vadd.f64 d16, d17, d16
...
```

**Format of issue file:**

```
!# ARCH, MODE, OPTION
hexcode = assembly | regs_read | regs_read_count | regs_write | regs_write_count | groups | groups_count
```

**Example**
```
!# CS_ARCH_ARM64, CS_MODE_ARM, CS_OPT_DETAIL
0xc0,0x1e,0x0c,0x4e == mov v0.s[1], w22 ; operands[0].vas: 0xb ; operands[0].vector_index: 1
...
```