Magic-Mirror/capstone
1
0
Fork 0
mirror of https://github.com/capstone-engine/capstone.git synced 2025-03-07 05:47:32 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity
capstone/arch/RISCV/RISCVGenInsnNameMaps.inc
z b8fcf27b22 RISCV support ISRV32/ISRV64 (#1401) 
* Added RISCV dir to contain the RISCV architecture engine code. Adding the TableGen files generated from llvm-tblgen. Add Disassembler.h

* Started working on RISCVDisassembler.c - RISCV_init(), RISCVDisassembler_getInstruction, and RISCV_getInstruction

* Added all functions to RISCVDisassembler.c and needed modifications to RISCVGenDisassemblerTables.inc. Add and modified RISCVGenSubtargetInfo.inc. Start creation of RISCVInstPrinter.h

* Finished RISCVGenAsmWriter.inc. Finished RISCVGenRegisterInfo.inc. Minor fixes to RISCVDisassembler.c. Working on RISCVInstPrinter

* Finished RISCVInstPrinter, RISCVMapping, RISCVBaseInfo, RISCVGenInstrInfo.inc, RISCVModule.c. Working on riscv.h

* Backport it from: 0db412ce3b

* All RISCV files added. Compiled correctly and initial test for ADD, ADDI, AND works properly.

* Add refactored cs.c for RISCV

* Testing all I instructions in test_riscv.c

* Modify the orignal backport for RISCVGenRegisterInfo.inc, capstone.h and test_iter to work w/ the current code strcuture

* Fix issue with RISCVGenRegisterInfo.inc - RISCVRegDesc[] (Excess elements in struct initializer). Added RISCV tests to test_iter.c

* fixed bug related to incorrect initialization of memory after malloc

* fix compile bug

* Fix compile errors.

* move riscv.h to include/capstone

* fix indentation issues

* fix coding style issues

* Fix indentation issues

* fix coding style

* Move variable declaration to the top of the block

* Fix coding indentation

* Move some stuff into RISCVMappingInsn.inc

* Fix code sytle

* remove cs_mode support for RISCV

* update asmwriter-inc to LLVM upstream

* update the .inc files to riscv upstream

* update riscv disassembler function for suport 16bit instructions

* update printer & tablegen inc files which have fixed arguments mismatch

* update headers and mapping source

* add riscv architecture specific test code

* fix all RISCV tons of compiler errors

* pass final tests

* add riscv tablegen patchs

* merge with upstream/next

* fix cstool missing riscv file

* fix root Makefile

* add new TableGen patchs for riscv

* fix cmakefile.txt of missing one riscv file

* fix declaration conflict

* fix incompatible declaration type

* change riscvc from arch to mode

* fix test_riscv warnning

* fix code style and add riscv part of test_basic

* add RISCV64 mode

* add suite for riscv

* crack fuzz test

* fix getfeaturebits test add riscvc

* fix test missing const qualifier warnning

* fix testcase type mismatch

* fix return value missing

* change getfeaturebits test

* add test cs files

* using a winder type contain the decode string

* fix a copy typo

* remove useless mode for riscv

* change cs file blank type

* add repo for update_riscv & fix cstool missing riscv mode

* fix typo

* add riscv for cstool useage

* add TableGen patch for riscv asmwriter

* clean ctags file

* remove black comment line

* fix fuzz related something

* fix missing RISCV string of fuzz

* update readme, etc..

* add riscv *.s.cs file

* add riscv *.s.cs file & clear ctags

* clear useless array declarations at capstone_test

* update to 5e4069f

* update readme change name more formal

* change position of riscv after bpf and modify copyright more uniform

* clear useless ctags file

* change blank with tab in riscv.h

* add riscv python bindings

* add riscv in __init__.py

* fix riscv define value for python binding

* fix test_riscv.py typo

* add missing riscvc in __init__.py of python bindings

* fix alias-insn printer bug, remove useless newline

* change inst print delimter from tab to bankspace for travis

* add riscv tablegen patch

* fix inst output more consistency

* add TableGen patch which fix inst output formal

* crack the effective address output for detail and change register print function

* fix not detail crash bug

* change item declaration position at cs_riscv

* update riscv.py

* change function name more meaningfull

* update python binding makefile

* fix register enum sequence according to riscvgenreginfo.inc

* test function name

* add enum s0/fp in riscv.h & update riscv_const.py

* add register name enum
2019-03-09 08:41:12 +08:00

276 lines
9.4 KiB
C
Raw Blame History

// This is auto-gen data for Capstone engine (www.capstone-engine.org)
// By Nguyen Anh Quynh <aquynh@gmail.com>
{ RISCV_INS_ADD, "add" },
{ RISCV_INS_ADDI, "addi" },
{ RISCV_INS_ADDIW, "addiw" },
{ RISCV_INS_ADDW, "addw" },
{ RISCV_INS_AMOADD_D, "amoadd.d" },
{ RISCV_INS_AMOADD_D_AQ, "amoadd.d.aq" },
{ RISCV_INS_AMOADD_D_AQ_RL, "amoadd.d.aqrl" },
{ RISCV_INS_AMOADD_D_RL, "amoadd.d.rl" },
{ RISCV_INS_AMOADD_W, "amoadd.w" },
{ RISCV_INS_AMOADD_W_AQ, "amoadd.w.aq" },
{ RISCV_INS_AMOADD_W_AQ_RL, "amoadd.w.aqrl" },
{ RISCV_INS_AMOADD_W_RL, "amoadd.w.rl" },
{ RISCV_INS_AMOAND_D, "amoand.d" },
{ RISCV_INS_AMOAND_D_AQ, "amoand.d.aq" },
{ RISCV_INS_AMOAND_D_AQ_RL, "amoand.d.aqrl" },
{ RISCV_INS_AMOAND_D_RL, "amoand.d.rl" },
{ RISCV_INS_AMOAND_W, "amoand.w" },
{ RISCV_INS_AMOAND_W_AQ, "amoand.w.aq" },
{ RISCV_INS_AMOAND_W_AQ_RL, "amoand.w.aqrl" },
{ RISCV_INS_AMOAND_W_RL, "amoand.w.rl" },
{ RISCV_INS_AMOMAXU_D, "amomaxu.d" },
{ RISCV_INS_AMOMAXU_D_AQ, "amomaxu.d.aq" },
{ RISCV_INS_AMOMAXU_D_AQ_RL, "amomaxu.d.aqrl" },
{ RISCV_INS_AMOMAXU_D_RL, "amomaxu.d.rl" },
{ RISCV_INS_AMOMAXU_W, "amomaxu.w" },
{ RISCV_INS_AMOMAXU_W_AQ, "amomaxu.w.aq" },
{ RISCV_INS_AMOMAXU_W_AQ_RL, "amomaxu.w.aqrl" },
{ RISCV_INS_AMOMAXU_W_RL, "amomaxu.w.rl" },
{ RISCV_INS_AMOMAX_D, "amomax.d" },
{ RISCV_INS_AMOMAX_D_AQ, "amomax.d.aq" },
{ RISCV_INS_AMOMAX_D_AQ_RL, "amomax.d.aqrl" },
{ RISCV_INS_AMOMAX_D_RL, "amomax.d.rl" },
{ RISCV_INS_AMOMAX_W, "amomax.w" },
{ RISCV_INS_AMOMAX_W_AQ, "amomax.w.aq" },
{ RISCV_INS_AMOMAX_W_AQ_RL, "amomax.w.aqrl" },
{ RISCV_INS_AMOMAX_W_RL, "amomax.w.rl" },
{ RISCV_INS_AMOMINU_D, "amominu.d" },
{ RISCV_INS_AMOMINU_D_AQ, "amominu.d.aq" },
{ RISCV_INS_AMOMINU_D_AQ_RL, "amominu.d.aqrl" },
{ RISCV_INS_AMOMINU_D_RL, "amominu.d.rl" },
{ RISCV_INS_AMOMINU_W, "amominu.w" },
{ RISCV_INS_AMOMINU_W_AQ, "amominu.w.aq" },
{ RISCV_INS_AMOMINU_W_AQ_RL, "amominu.w.aqrl" },
{ RISCV_INS_AMOMINU_W_RL, "amominu.w.rl" },
{ RISCV_INS_AMOMIN_D, "amomin.d" },
{ RISCV_INS_AMOMIN_D_AQ, "amomin.d.aq" },
{ RISCV_INS_AMOMIN_D_AQ_RL, "amomin.d.aqrl" },
{ RISCV_INS_AMOMIN_D_RL, "amomin.d.rl" },
{ RISCV_INS_AMOMIN_W, "amomin.w" },
{ RISCV_INS_AMOMIN_W_AQ, "amomin.w.aq" },
{ RISCV_INS_AMOMIN_W_AQ_RL, "amomin.w.aqrl" },
{ RISCV_INS_AMOMIN_W_RL, "amomin.w.rl" },
{ RISCV_INS_AMOOR_D, "amoor.d" },
{ RISCV_INS_AMOOR_D_AQ, "amoor.d.aq" },
{ RISCV_INS_AMOOR_D_AQ_RL, "amoor.d.aqrl" },
{ RISCV_INS_AMOOR_D_RL, "amoor.d.rl" },
{ RISCV_INS_AMOOR_W, "amoor.w" },
{ RISCV_INS_AMOOR_W_AQ, "amoor.w.aq" },
{ RISCV_INS_AMOOR_W_AQ_RL, "amoor.w.aqrl" },
{ RISCV_INS_AMOOR_W_RL, "amoor.w.rl" },
{ RISCV_INS_AMOSWAP_D, "amoswap.d" },
{ RISCV_INS_AMOSWAP_D_AQ, "amoswap.d.aq" },
{ RISCV_INS_AMOSWAP_D_AQ_RL, "amoswap.d.aqrl" },
{ RISCV_INS_AMOSWAP_D_RL, "amoswap.d.rl" },
{ RISCV_INS_AMOSWAP_W, "amoswap.w" },
{ RISCV_INS_AMOSWAP_W_AQ, "amoswap.w.aq" },
{ RISCV_INS_AMOSWAP_W_AQ_RL, "amoswap.w.aqrl" },
{ RISCV_INS_AMOSWAP_W_RL, "amoswap.w.rl" },
{ RISCV_INS_AMOXOR_D, "amoxor.d" },
{ RISCV_INS_AMOXOR_D_AQ, "amoxor.d.aq" },
{ RISCV_INS_AMOXOR_D_AQ_RL, "amoxor.d.aqrl" },
{ RISCV_INS_AMOXOR_D_RL, "amoxor.d.rl" },
{ RISCV_INS_AMOXOR_W, "amoxor.w" },
{ RISCV_INS_AMOXOR_W_AQ, "amoxor.w.aq" },
{ RISCV_INS_AMOXOR_W_AQ_RL, "amoxor.w.aqrl" },
{ RISCV_INS_AMOXOR_W_RL, "amoxor.w.rl" },
{ RISCV_INS_AND, "and" },
{ RISCV_INS_ANDI, "andi" },
{ RISCV_INS_AUIPC, "auipc" },
{ RISCV_INS_BEQ, "beq" },
{ RISCV_INS_BGE, "bge" },
{ RISCV_INS_BGEU, "bgeu" },
{ RISCV_INS_BLT, "blt" },
{ RISCV_INS_BLTU, "bltu" },
{ RISCV_INS_BNE, "bne" },
{ RISCV_INS_CSRRC, "csrrc" },
{ RISCV_INS_CSRRCI, "csrrci" },
{ RISCV_INS_CSRRS, "csrrs" },
{ RISCV_INS_CSRRSI, "csrrsi" },
{ RISCV_INS_CSRRW, "csrrw" },
{ RISCV_INS_CSRRWI, "csrrwi" },
{ RISCV_INS_C_ADD, "c.add" },
{ RISCV_INS_C_ADDI, "c.addi" },
{ RISCV_INS_C_ADDI16SP, "c.addi16sp" },
{ RISCV_INS_C_ADDI4SPN, "c.addi4spn" },
{ RISCV_INS_C_ADDIW, "c.addiw" },
{ RISCV_INS_C_ADDW, "c.addw" },
{ RISCV_INS_C_AND, "c.and" },
{ RISCV_INS_C_ANDI, "c.andi" },
{ RISCV_INS_C_BEQZ, "c.beqz" },
{ RISCV_INS_C_BNEZ, "c.bnez" },
{ RISCV_INS_C_EBREAK, "c.ebreak" },
{ RISCV_INS_C_FLD, "c.fld" },
{ RISCV_INS_C_FLDSP, "c.fldsp" },
{ RISCV_INS_C_FLW, "c.flw" },
{ RISCV_INS_C_FLWSP, "c.flwsp" },
{ RISCV_INS_C_FSD, "c.fsd" },
{ RISCV_INS_C_FSDSP, "c.fsdsp" },
{ RISCV_INS_C_FSW, "c.fsw" },
{ RISCV_INS_C_FSWSP, "c.fswsp" },
{ RISCV_INS_C_J, "c.j" },
{ RISCV_INS_C_JAL, "c.jal" },
{ RISCV_INS_C_JALR, "c.jalr" },
{ RISCV_INS_C_JR, "c.jr" },
{ RISCV_INS_C_LD, "c.ld" },
{ RISCV_INS_C_LDSP, "c.ldsp" },
{ RISCV_INS_C_LI, "c.li" },
{ RISCV_INS_C_LUI, "c.lui" },
{ RISCV_INS_C_LW, "c.lw" },
{ RISCV_INS_C_LWSP, "c.lwsp" },
{ RISCV_INS_C_MV, "c.mv" },
{ RISCV_INS_C_NOP, "c.nop" },
{ RISCV_INS_C_OR, "c.or" },
{ RISCV_INS_C_SD, "c.sd" },
{ RISCV_INS_C_SDSP, "c.sdsp" },
{ RISCV_INS_C_SLLI, "c.slli" },
{ RISCV_INS_C_SRAI, "c.srai" },
{ RISCV_INS_C_SRLI, "c.srli" },
{ RISCV_INS_C_SUB, "c.sub" },
{ RISCV_INS_C_SUBW, "c.subw" },
{ RISCV_INS_C_SW, "c.sw" },
{ RISCV_INS_C_SWSP, "c.swsp" },
{ RISCV_INS_C_UNIMP, "c.unimp" },
{ RISCV_INS_C_XOR, "c.xor" },
{ RISCV_INS_DIV, "div" },
{ RISCV_INS_DIVU, "divu" },
{ RISCV_INS_DIVUW, "divuw" },
{ RISCV_INS_DIVW, "divw" },
{ RISCV_INS_EBREAK, "ebreak" },
{ RISCV_INS_ECALL, "ecall" },
{ RISCV_INS_FADD_D, "fadd.d" },
{ RISCV_INS_FADD_S, "fadd.s" },
{ RISCV_INS_FCLASS_D, "fclass.d" },
{ RISCV_INS_FCLASS_S, "fclass.s" },
{ RISCV_INS_FCVT_D_L, "fcvt.d.l" },
{ RISCV_INS_FCVT_D_LU, "fcvt.d.lu" },
{ RISCV_INS_FCVT_D_S, "fcvt.d.s" },
{ RISCV_INS_FCVT_D_W, "fcvt.d.w" },
{ RISCV_INS_FCVT_D_WU, "fcvt.d.wu" },
{ RISCV_INS_FCVT_LU_D, "fcvt.lu.d" },
{ RISCV_INS_FCVT_LU_S, "fcvt.lu.s" },
{ RISCV_INS_FCVT_L_D, "fcvt.l.d" },
{ RISCV_INS_FCVT_L_S, "fcvt.l.s" },
{ RISCV_INS_FCVT_S_D, "fcvt.s.d" },
{ RISCV_INS_FCVT_S_L, "fcvt.s.l" },
{ RISCV_INS_FCVT_S_LU, "fcvt.s.lu" },
{ RISCV_INS_FCVT_S_W, "fcvt.s.w" },
{ RISCV_INS_FCVT_S_WU, "fcvt.s.wu" },
{ RISCV_INS_FCVT_WU_D, "fcvt.wu.d" },
{ RISCV_INS_FCVT_WU_S, "fcvt.wu.s" },
{ RISCV_INS_FCVT_W_D, "fcvt.w.d" },
{ RISCV_INS_FCVT_W_S, "fcvt.w.s" },
{ RISCV_INS_FDIV_D, "fdiv.d" },
{ RISCV_INS_FDIV_S, "fdiv.s" },
{ RISCV_INS_FENCE, "fence" },
{ RISCV_INS_FENCE_I, "fence.i" },
{ RISCV_INS_FENCE_TSO, "fence.tso" },
{ RISCV_INS_FEQ_D, "feq.d" },
{ RISCV_INS_FEQ_S, "feq.s" },
{ RISCV_INS_FLD, "fld" },
{ RISCV_INS_FLE_D, "fle.d" },
{ RISCV_INS_FLE_S, "fle.s" },
{ RISCV_INS_FLT_D, "flt.d" },
{ RISCV_INS_FLT_S, "flt.s" },
{ RISCV_INS_FLW, "flw" },
{ RISCV_INS_FMADD_D, "fmadd.d" },
{ RISCV_INS_FMADD_S, "fmadd.s" },
{ RISCV_INS_FMAX_D, "fmax.d" },
{ RISCV_INS_FMAX_S, "fmax.s" },
{ RISCV_INS_FMIN_D, "fmin.d" },
{ RISCV_INS_FMIN_S, "fmin.s" },
{ RISCV_INS_FMSUB_D, "fmsub.d" },
{ RISCV_INS_FMSUB_S, "fmsub.s" },
{ RISCV_INS_FMUL_D, "fmul.d" },
{ RISCV_INS_FMUL_S, "fmul.s" },
{ RISCV_INS_FMV_D_X, "fmv.d.x" },
{ RISCV_INS_FMV_W_X, "fmv.w.x" },
{ RISCV_INS_FMV_X_D, "fmv.x.d" },
{ RISCV_INS_FMV_X_W, "fmv.x.w" },
{ RISCV_INS_FNMADD_D, "fnmadd.d" },
{ RISCV_INS_FNMADD_S, "fnmadd.s" },
{ RISCV_INS_FNMSUB_D, "fnmsub.d" },
{ RISCV_INS_FNMSUB_S, "fnmsub.s" },
{ RISCV_INS_FSD, "fsd" },
{ RISCV_INS_FSGNJN_D, "fsgnjn.d" },
{ RISCV_INS_FSGNJN_S, "fsgnjn.s" },
{ RISCV_INS_FSGNJX_D, "fsgnjx.d" },
{ RISCV_INS_FSGNJX_S, "fsgnjx.s" },
{ RISCV_INS_FSGNJ_D, "fsgnj.d" },
{ RISCV_INS_FSGNJ_S, "fsgnj.s" },
{ RISCV_INS_FSQRT_D, "fsqrt.d" },
{ RISCV_INS_FSQRT_S, "fsqrt.s" },
{ RISCV_INS_FSUB_D, "fsub.d" },
{ RISCV_INS_FSUB_S, "fsub.s" },
{ RISCV_INS_FSW, "fsw" },
{ RISCV_INS_JAL, "jal" },
{ RISCV_INS_JALR, "jalr" },
{ RISCV_INS_LB, "lb" },
{ RISCV_INS_LBU, "lbu" },
{ RISCV_INS_LD, "ld" },
{ RISCV_INS_LH, "lh" },
{ RISCV_INS_LHU, "lhu" },
{ RISCV_INS_LR_D, "lr.d" },
{ RISCV_INS_LR_D_AQ, "lr.d.aq" },
{ RISCV_INS_LR_D_AQ_RL, "lr.d.aqrl" },
{ RISCV_INS_LR_D_RL, "lr.d.rl" },
{ RISCV_INS_LR_W, "lr.w" },
{ RISCV_INS_LR_W_AQ, "lr.w.aq" },
{ RISCV_INS_LR_W_AQ_RL, "lr.w.aqrl" },
{ RISCV_INS_LR_W_RL, "lr.w.rl" },
{ RISCV_INS_LUI, "lui" },
{ RISCV_INS_LW, "lw" },
{ RISCV_INS_LWU, "lwu" },
{ RISCV_INS_MRET, "mret" },
{ RISCV_INS_MUL, "mul" },
{ RISCV_INS_MULH, "mulh" },
{ RISCV_INS_MULHSU, "mulhsu" },
{ RISCV_INS_MULHU, "mulhu" },
{ RISCV_INS_MULW, "mulw" },
{ RISCV_INS_OR, "or" },
{ RISCV_INS_ORI, "ori" },
{ RISCV_INS_REM, "rem" },
{ RISCV_INS_REMU, "remu" },
{ RISCV_INS_REMUW, "remuw" },
{ RISCV_INS_REMW, "remw" },
{ RISCV_INS_SB, "sb" },
{ RISCV_INS_SC_D, "sc.d" },
{ RISCV_INS_SC_D_AQ, "sc.d.aq" },
{ RISCV_INS_SC_D_AQ_RL, "sc.d.aqrl" },
{ RISCV_INS_SC_D_RL, "sc.d.rl" },
{ RISCV_INS_SC_W, "sc.w" },
{ RISCV_INS_SC_W_AQ, "sc.w.aq" },
{ RISCV_INS_SC_W_AQ_RL, "sc.w.aqrl" },
{ RISCV_INS_SC_W_RL, "sc.w.rl" },
{ RISCV_INS_SD, "sd" },
{ RISCV_INS_SFENCE_VMA, "sfence.vma" },
{ RISCV_INS_SH, "sh" },
{ RISCV_INS_SLL, "sll" },
{ RISCV_INS_SLLI, "slli" },
{ RISCV_INS_SLLIW, "slliw" },
{ RISCV_INS_SLLW, "sllw" },
{ RISCV_INS_SLT, "slt" },
{ RISCV_INS_SLTI, "slti" },
{ RISCV_INS_SLTIU, "sltiu" },
{ RISCV_INS_SLTU, "sltu" },
{ RISCV_INS_SRA, "sra" },
{ RISCV_INS_SRAI, "srai" },
{ RISCV_INS_SRAIW, "sraiw" },
{ RISCV_INS_SRAW, "sraw" },
{ RISCV_INS_SRET, "sret" },
{ RISCV_INS_SRL, "srl" },
{ RISCV_INS_SRLI, "srli" },
{ RISCV_INS_SRLIW, "srliw" },
{ RISCV_INS_SRLW, "srlw" },
{ RISCV_INS_SUB, "sub" },
{ RISCV_INS_SUBW, "subw" },
{ RISCV_INS_SW, "sw" },
{ RISCV_INS_UNIMP, "unimp" },
{ RISCV_INS_URET, "uret" },
{ RISCV_INS_WFI, "wfi" },
{ RISCV_INS_XOR, "xor" },
{ RISCV_INS_XORI, "xori" },
Reference in New Issue View Git Blame Copy Permalink