capstone/suite/test_group_name.py
Rot127 ef89b18a88 Architecture updater (auto-sync) - Updating AArch64 (#2026)
* Update sysop inc file

* Fix missing  braces warning

* Handle new system operands

* Fix build errors by renaming.

* Fix segfault

* Fix segfault

* Add custom MCOperand valiadtors

* Add AArch64 case for getFeatureBits

* Fix infinite loop

* Fix braces warning.

* Implement loopuo by name for sys operands

* Fix incorrect translation which remove else if statements.

* Fix several segfaults

* Rename GetRegFromClass patch

* Fix segfaults and asserts

* Fix segfault

* Move MRI setting to Mapping

* Remove unused code

* Add add_op_X functinos for AArch64.

* Add fill detail functins

* Handle RegWithShiftExtend operands

* Handle TypedVectorList operands.

* Handle ComplexRoatation operands

* Handle MemExtend operands

* Handle ImmRangeScale operands

* Handle ExactFPImm operands

* Handle GPRSeqPairsClass operands

* Handle Imm8OptLsl operands

* Handle ImmScale operands

* Handle LogicalImm operands

* Handle Matrix operands

* Handle SME Matrix tiles and vectors.

* Handle normal operands.

* Fix segfault.

* Handle PostInc operands.

* Reorder VecLayout enum to have no duplicate enum value.

* Handle PredicateAsCounter operands

* Handle ZPRasFPR operands

* Handle VectorIndex operands

* Handle UImm12Offset operands.

* Move reg suffix to enum val to single function.

* Handle SVERegOp operands

* Handle SVELogicalImm operands

* Handle SImm operand

* Handle PrefetchOp operands

* Handle Imm and ImmHex operands

* Handle GPR64as32 and GPR64x8 operands

* Add missing break

* Handle FPImm operand

* Handle ExtendedRegister opreand

* Handle CondCode operands

* Handle BTIHintOp operands

* Handle BarrierOption operands

* Handle BarrierXSOption

* Add not implemeted case again

* Handle ArithExtend operands

* Handle AdrpLabel and AlignedLabel operands

* Handle AMNoIndex operands

* Handle AddSubImm operands

* Handle MSRSystemRegisters and MRSSystemRegister operands

* Handle PSBHntOp and RPRFMOperand operands

* Remove unused variables

* Handle InverseCondCode operands

* Handle ImplicityTypedVectorList operands

* Handle ShiftedRegister operands

* Handle Shifter operands

* Handle SIMDType10Operand operands

* Handle SVCROp operands

* Handle SVEPattern operands

* Handle SVEVecLenSpecifier operands

* Handle SysCROperands

* Handle SysXzrPair operands

* Handle PState operands

* Handle VRegOperands

* Primt SME oeprands.

* Fix cs_operand.h include

* Rename arm64 -> aarch64 in python bindings.

* Add Python bindings for SH

* Fix ARM Python bindings (#2127)

* Restructure auto-sync update scripts.

* Move Helper functions to Updater dir

* Move requirements.txt

* Add basic ASUpdater.py

* Run black.

* Add inc file generater to updater

* Add option to select certain inc files fore generation.

* Enable clean build and implement patcher for inc files.

* Format config

* Patch main header files after inc generation.

* Implement clang-format function (unused yet, because it takes forever.)

* Copy generated inc files to arch dir

* Invert clean option (noramlly we need to clean the build dir.)

* Clearify arg doc

* Rename SystemRegister file for AArch64

* Centralize handling of path variables.

* Check if SystemOperands had to be generated before renaming on of its files.

* Replace class parameters by calling get_path

* Remove updater config which only contained paths.

* Add refactor option.

* Remove more path handling in the Configurator.

* Add translation step to updater.

* Fix includes after CppTranslator was moved into the Updater

* Remove updater config

* Fix several issue in the Configurator

* Fix file operations

* Remove addition argument from translator.

* Add Differ step to updater.

* Add path variable for arch_config

* Add diff step.

* Fix typo

* Introduce .clang-format path variable.

* Remove duplicate functions

* Add option to select update steps to execute.

* Check in write functions for write flag.

* Rename PatchMainHeader -> HeaderPatcher

* Move .gitignore

* Add README to vendor dir.

* Add all system operands to cstool output

* Update cstest with aarch64 changes

* Remove wb flag of aarch64 detail struct

* Set updates_flag after decoding

* Set writeback after decoding.

* Rename ARM64 -> AArch64

* Update printer and op mapping

* Exit normally

* Add AArch64 alias

* Fix some tmeplate function calls

* Fix flag check after rebase.

* Fix build by commentig unnused code.

* Add memory operand flag

* Handle memory operands printed via generic printOperand function.

* Handle UImm memory offsets

* Introduce MEM_REG and MEM_IMM op types

* Handle scaled memory immediates

* Check for op_count before checking for mem op at -1 index.

* Update memory operand flags.

* Pass imm/reg memory ops in set_imm/reg to set_mem.

* Add missing set_sme_operand call and fix assert.

* Remove CS_OP_MEM flag before entering switch.

* Preidcates are registers.

* Add shift info always to the previous operand

* Check for generic system regs

* Handle NumLanes = 0 LaneKind = q case

* Replace printImm call with normal print logic. Otherwise ops get added twice to detail.

* Handle FP operands in printOperand.

* Add access information to float operands.

* Rewrite SME matrix handling.

* Set correct SME layouts and allow for immediate range sme offsets.

* Handle cases of unknown system alias by setting their raw values

* Update cstool and header file with new SME offset handling

* Handle SME Tile lists.

* Fix build error in cstest

* Update MC tests for AArch64

* Handle TLBI operands and fix printing bug.

* Fix: Print signed value as signed.

* Add more system alias to detail.

* Remove duplicate hex prefix

* Set correct values for the register info

* Replace tabs with white spaces

* Move string append logic to own function.

* Set DecodeComplete = true before decoding (as originally in the LLVM code).

* Change type of feature argument, since only LLVM features are passed, not CS groups.

* Imitate lower_bound for the index table binary search.

* Remove trailing comments from test files.

* Print shift amount in decimal

* Save detail of shift alias instructions.

* Add extension details fot ext instruction alias

* Print LSB and width in decimal

* Fix LLVM bug. The feature check for V8_2a doesn't check if all features are enabled.

* Fix lower_bounds check.
For m == 0 we wrap around 0 of cause.

* Fix feature check. Add check for FeatureAll since it includes XS

* Operate on temporary MCInst when trying decoding.

* Add lower_bound behavior to IndexTypeStr binsearch.

* Fix MC tests which were incorrect because of missing FeatureAll check

* Add Alias handling for AArch64

* Update system operands with SYSIMM types and add additional sysop category.

* Add macros for meta programming (ARM64 <-> AArch64 selection).

* Fix union/struct confusion and add raw_value member to uninions.

* Allow to set Syntax and mode options for AArch64

* Fix build warning by using correct type

* Print shift value in decimal

* Add missing call to add_cs_detail.

* Update name map files with normalized names.

* Remove unused function

* Add check if detail should be filled.

* Fill detail for real instructions if only real detail is requested.

* Add always the extension.

* Make dir creation log message debug level

* Implement ADR immediate operand printer.

See: c3484b1fdc

* Check for flag registers beeing written and update flag.

* Move multiple CondCode helpers to aarch64.h because they are so freaking useful.

+ Print CC if it is EQ

* Fix incorrectly initialized CC and VectorLayout.

* Add LSL shift type for extensions.

* Fix case when shift amount is 0

* Fix post-index memory instructions.

* Pass raw immediate through getShiftValue to extract actual shift amount

* Setup AArch64 detail ops.

* Add flag for operands part of a list.

* Set vector indices for all relevant registers.

* Add missing call to add_cs_detail for postIncOperands

* Add ugly yet reliable way to determine post-index addressing mode

* Add support for old Capstone register alias.

* Remove leading space before some alias mnemonics.

* add AARCH64 to `cmake.sh`

* add HAS_AARCH64 to `cs.c`

* should probably just reference `cs_operand.h` in `aarch64.h`

* hint compiler at `AArch64_SYSREG` enum type for casting purposes

* update `Makefile` for AARCH64

leaves `CAPSTONE_HAS_ARM64` supported

* `testFeatureBits` platform function check

`testFeatureBits` should check if the platform function is visible first

* update tests to use AARCH64 convention

* hack: avoid enum casts for `MCInst` Values

Apple compiler really hates typecasting a enum, even if bounded from a unsigned. Lets set the raw_value directly

is a hack and needs proper review

* Check for present detail before accessing it.

* Add CS only groups

* Use general map ins_op type

* Fix build warning about str size computation.

* Disable warning about unitialized value for GCC 11.

Imm is initialized and the warning does not appear
in later versions.

* Use correct include guard for PPC

* Add missing requirements

* Update SystemOperand enums.

* Fix overlapping comparison warning

* Fix reachable assert where OpNum is not of type IMM

* Handle 0.0 operand for fcmp

* Fix incorrect variable passed.

* Fix for MacOS which doesn't know the warning and throws another one.

* Make getExtendEncoding static to fix build warning on MSVC.

* Fix build error: 'missing binary operator before token' by checking __GNUC__

* Add string search to add vector layout info.

* Add missing mem disponents of several ldr and str instructions.

* Add 0 immediates to several instructions.

* Rename v regs to q and d variant.

The cs_regname API can not pass the variant name of the register requested.
So we simply emit the default variant name.

* Fix incorrect enum value.

* Fix tests for system operands.

* Fix syntax issues in tests.

* Rename Arm64 -> AArch64 Python bindings.

* Fix Python bindings C structs.

* Fix generation of constants (ARMCC skipped because it starts with ARM)

* Update const files

* Remove -Wmaybe-uninitialized warning since it fails fuzz build

* Add missing comma

* Fix case

* Fix AArch64 Python bindings:

- Do not generate constants automatically (dscript is way too buggy).
- Update printing of details.

* Rename ARM64 -> AArch64 in test_corpus.py

* Rename test_arm64 -> test_aarch64

* Rename ARM-64 -> AArch64

* Fix diff CI test by disassembling AArch64 at former ARM64 place

* Fix several wrong types and remove unnecessary memebers from Python binding

* Fix: Same printing format of detail for cstool, test_ and test_*.py

* Fix: pass correct op index for mov alias with op[1] == reg wzr.

* Set prfm op manuall in case of unnown sysop. set_imm would add it to an memory operand wihtout base.

* Fix: If barrier ops are not set an assert is reached.

We fix it here by simply getting the immediate as the printing code does.

---------

Co-authored-by: Peace-Maker <peace-maker@wcfan.de>
Co-authored-by: Dayton <5340801+watbulb@users.noreply.github.com>
2023-11-15 12:12:14 +08:00

284 lines
7.7 KiB
Python
Executable File

#!/usr/bin/python
from capstone import *
from capstone.arm import *
from capstone.arm64 import *
from capstone.mips import *
from capstone.ppc import *
from capstone.sparc import *
from capstone.systemz import *
from capstone.x86 import *
from capstone.xcore import *
from capstone.riscv import *
import sys
class GroupTest:
def __init__(self, name, arch, mode, data):
self.name = name
self.arch = arch
self.mode = mode
self.data = data
def run(self):
print('Testing %s' %self.name)
cap = Cs(self.arch, self.mode)
for group_id in xrange(0,255):
name = self.data.get(group_id)
res = cap.group_name(group_id)
if res != name:
print("ERROR: id = %u expected '%s', but got '%s'" %(group_id, name, res))
print("")
arm_dict = {
ARM_GRP_JUMP: "jump",
ARM_GRP_CALL: "call",
ARM_GRP_INT: "int",
ARM_GRP_PRIVILEGE: "privilege",
ARM_GRP_CRYPTO: "crypto",
ARM_GRP_DATABARRIER: "databarrier",
ARM_GRP_DIVIDE: "divide",
ARM_GRP_FPARMV8: "fparmv8",
ARM_GRP_MULTPRO: "multpro",
ARM_GRP_NEON: "neon",
ARM_GRP_T2EXTRACTPACK: "T2EXTRACTPACK",
ARM_GRP_THUMB2DSP: "THUMB2DSP",
ARM_GRP_TRUSTZONE: "TRUSTZONE",
ARM_GRP_V4T: "v4t",
ARM_GRP_V5T: "v5t",
ARM_GRP_V5TE: "v5te",
ARM_GRP_V6: "v6",
ARM_GRP_V6T2: "v6t2",
ARM_GRP_V7: "v7",
ARM_GRP_V8: "v8",
ARM_GRP_VFP2: "vfp2",
ARM_GRP_VFP3: "vfp3",
ARM_GRP_VFP4: "vfp4",
ARM_GRP_ARM: "arm",
ARM_GRP_MCLASS: "mclass",
ARM_GRP_NOTMCLASS: "notmclass",
ARM_GRP_THUMB: "thumb",
ARM_GRP_THUMB1ONLY: "thumb1only",
ARM_GRP_THUMB2: "thumb2",
ARM_GRP_PREV8: "prev8",
ARM_GRP_FPVMLX: "fpvmlx",
ARM_GRP_MULOPS: "mulops",
ARM_GRP_CRC: "crc",
ARM_GRP_DPVFP: "dpvfp",
ARM_GRP_V6M: "v6m",
ARM_GRP_VIRTUALIZATION: "virtualization",
}
arm64_dict = {
AARCH64_GRP_JUMP: "jump",
AARCH64_GRP_CALL: "call",
AARCH64_GRP_RET: "return",
AARCH64_GRP_INT: "int",
AARCH64_GRP_PRIVILEGE: "privilege",
AARCH64_GRP_CRYPTO: "crypto",
AARCH64_GRP_FPARMV8: "fparmv8",
AARCH64_GRP_NEON: "neon",
AARCH64_GRP_CRC: "crc"
}
mips_dict = {
MIPS_GRP_JUMP: "jump",
MIPS_GRP_CALL: "call",
MIPS_GRP_RET: "ret",
MIPS_GRP_INT: "int",
MIPS_GRP_IRET: "iret",
MIPS_GRP_PRIVILEGE: "privilege",
MIPS_GRP_BITCOUNT: "bitcount",
MIPS_GRP_DSP: "dsp",
MIPS_GRP_DSPR2: "dspr2",
MIPS_GRP_FPIDX: "fpidx",
MIPS_GRP_MSA: "msa",
MIPS_GRP_MIPS32R2: "mips32r2",
MIPS_GRP_MIPS64: "mips64",
MIPS_GRP_MIPS64R2: "mips64r2",
MIPS_GRP_SEINREG: "seinreg",
MIPS_GRP_STDENC: "stdenc",
MIPS_GRP_SWAP: "swap",
MIPS_GRP_MICROMIPS: "micromips",
MIPS_GRP_MIPS16MODE: "mips16mode",
MIPS_GRP_FP64BIT: "fp64bit",
MIPS_GRP_NONANSFPMATH: "nonansfpmath",
MIPS_GRP_NOTFP64BIT: "notfp64bit",
MIPS_GRP_NOTINMICROMIPS: "notinmicromips",
MIPS_GRP_NOTNACL: "notnacl",
MIPS_GRP_NOTMIPS32R6: "notmips32r6",
MIPS_GRP_NOTMIPS64R6: "notmips64r6",
MIPS_GRP_CNMIPS: "cnmips",
MIPS_GRP_MIPS32: "mips32",
MIPS_GRP_MIPS32R6: "mips32r6",
MIPS_GRP_MIPS64R6: "mips64r6",
MIPS_GRP_MIPS2: "mips2",
MIPS_GRP_MIPS3: "mips3",
MIPS_GRP_MIPS3_32: "mips3_32",
MIPS_GRP_MIPS3_32R2: "mips3_32r2",
MIPS_GRP_MIPS4_32: "mips4_32",
MIPS_GRP_MIPS4_32R2: "mips4_32r2",
MIPS_GRP_MIPS5_32R2: "mips5_32r2",
MIPS_GRP_GP32BIT: "gp32bit",
MIPS_GRP_GP64BIT: "gp64bit",
}
ppc_dict = {
PPC_GRP_JUMP: "jump",
PPC_GRP_ALTIVEC: "altivec",
PPC_GRP_MODE32: "mode32",
PPC_GRP_MODE64: "mode64",
PPC_GRP_BOOKE: "booke",
PPC_GRP_NOTBOOKE: "notbooke",
PPC_GRP_SPE: "spe",
PPC_GRP_VSX: "vsx",
PPC_GRP_E500: "e500",
PPC_GRP_PPC4XX: "ppc4xx",
PPC_GRP_PPC6XX: "ppc6xx",
PPC_GRP_ICBT: "icbt",
PPC_GRP_P8ALTIVEC: "p8altivec",
PPC_GRP_P8VECTOR: "p8vector",
PPC_GRP_QPX: "qpx",
PPC_GRP_PS: "ps",
}
sparc_dict = {
SPARC_GRP_JUMP: "jump",
SPARC_GRP_HARDQUAD: "hardquad",
SPARC_GRP_V9: "v9",
SPARC_GRP_VIS: "vis",
SPARC_GRP_VIS2: "vis2",
SPARC_GRP_VIS3: "vis3",
SPARC_GRP_32BIT: "32bit",
SPARC_GRP_64BIT: "64bit",
}
sysz_dict = {
SYSZ_GRP_JUMP: "jump",
SYSZ_GRP_DISTINCTOPS: "distinctops",
SYSZ_GRP_FPEXTENSION: "fpextension",
SYSZ_GRP_HIGHWORD: "highword",
SYSZ_GRP_INTERLOCKEDACCESS1: "interlockedaccess1",
SYSZ_GRP_LOADSTOREONCOND: "loadstoreoncond",
}
x86_dict = {
X86_GRP_JUMP: "jump",
X86_GRP_CALL: "call",
X86_GRP_RET: "ret",
X86_GRP_INT: "int",
X86_GRP_IRET: "iret",
X86_GRP_PRIVILEGE: "privilege",
X86_GRP_VM: "vm",
X86_GRP_3DNOW: "3dnow",
X86_GRP_AES: "aes",
X86_GRP_ADX: "adx",
X86_GRP_AVX: "avx",
X86_GRP_AVX2: "avx2",
X86_GRP_AVX512: "avx512",
X86_GRP_BMI: "bmi",
X86_GRP_BMI2: "bmi2",
X86_GRP_CMOV: "cmov",
X86_GRP_F16C: "fc16",
X86_GRP_FMA: "fma",
X86_GRP_FMA4: "fma4",
X86_GRP_FSGSBASE: "fsgsbase",
X86_GRP_HLE: "hle",
X86_GRP_MMX: "mmx",
X86_GRP_MODE32: "mode32",
X86_GRP_MODE64: "mode64",
X86_GRP_RTM: "rtm",
X86_GRP_SHA: "sha",
X86_GRP_SSE1: "sse1",
X86_GRP_SSE2: "sse2",
X86_GRP_SSE3: "sse3",
X86_GRP_SSE41: "sse41",
X86_GRP_SSE42: "sse42",
X86_GRP_SSE4A: "sse4a",
X86_GRP_SSSE3: "ssse3",
X86_GRP_PCLMUL: "pclmul",
X86_GRP_XOP: "xop",
X86_GRP_CDI: "cdi",
X86_GRP_ERI: "eri",
X86_GRP_TBM: "tbm",
X86_GRP_16BITMODE: "16bitmode",
X86_GRP_NOT64BITMODE: "not64bitmode",
X86_GRP_SGX: "sgx",
X86_GRP_DQI: "dqi",
X86_GRP_BWI: "bwi",
X86_GRP_PFI: "pfi",
X86_GRP_VLX: "vlx",
X86_GRP_SMAP: "smap",
X86_GRP_NOVLX: "novlx",
}
xcore_dict = {
XCORE_GRP_JUMP: "jump",
}
riscv32_dict = {
RISCV_GRP_JUMP : "jump",
RISCV_GRP_CALL : "call",
RISCV_GRP_RET : "ret",
RISCV_GRP_INT : "int",
RISCV_GRP_IRET : "iret",
RISCV_GRP_PRIVILEGE : "privileged",
RISCV_GRP_BRANCH_RELATIVE: "branch_relative",
RISCV_GRP_ISRV32 : "isrv32",
RISCV_GRP_HASSTDEXTA : "hasstdexta",
RISCV_GRP_HASSTDEXTC : "hasstdextc",
RISCV_GRP_HASSTDEXTD : "hasstdextd",
RISCV_GRP_HASSTDEXTF : "hasstdextf",
RISCV_GRP_HASSTDEXTM : "hasstdextm",
}
riscv64_dict = {
RISCV_GRP_JUMP : "jump",
RISCV_GRP_CALL : "call",
RISCV_GRP_RET : "ret",
RISCV_GRP_INT : "int",
RISCV_GRP_IRET : "iret",
RISCV_GRP_PRIVILEGE : "privileged",
RISCV_GRP_BRANCH_RELATIVE: "branch_relative",
RISCV_GRP_ISRV64 : "isrv64",
RISCV_GRP_HASSTDEXTA : "hasstdexta",
RISCV_GRP_HASSTDEXTC : "hasstdextc",
RISCV_GRP_HASSTDEXTD : "hasstdextd",
RISCV_GRP_HASSTDEXTF : "hasstdextf",
RISCV_GRP_HASSTDEXTM : "hasstdextm",
}
tests = [
GroupTest('arm', CS_ARCH_ARM, CS_MODE_THUMB, arm_dict),
GroupTest('arm64', CS_ARCH_AARCH64, CS_MODE_ARM, arm64_dict),
GroupTest('mips', CS_ARCH_MIPS, CS_MODE_MIPS32 | CS_MODE_BIG_ENDIAN, mips_dict),
GroupTest('ppc', CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, ppc_dict),
GroupTest('sparc', CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, sparc_dict),
GroupTest('sysz', CS_ARCH_SYSZ, CS_MODE_BIG_ENDIAN, sysz_dict),
GroupTest('x86', CS_ARCH_X86, CS_MODE_32, x86_dict),
GroupTest('xcore', CS_ARCH_XCORE, CS_MODE_BIG_ENDIAN, xcore_dict),
GroupTest('m68k', CS_ARCH_M68K, CS_MODE_BIG_ENDIAN, xcore_dict),
GroupTest('riscv32', CS_ARCH_RISCV, CS_MODE_RISCV32, riscv32_dict),
GroupTest('riscv64', CS_ARCH_RISCV, CS_MODE_RISCV64, riscv64_dict),
]
if __name__ == '__main__':
args = sys.argv[1:]
all = len(args) == 0 or 'all' in args
for t in tests:
if all or t.name in args:
t.run()
else:
print('Skipping %s' %t.name)