mirror of
https://github.com/capstone-engine/capstone.git
synced 2024-10-07 02:43:23 +00:00
ef89b18a88
* Update sysop inc file
* Fix missing braces warning
* Handle new system operands
* Fix build errors by renaming.
* Fix segfault
* Fix segfault
* Add custom MCOperand valiadtors
* Add AArch64 case for getFeatureBits
* Fix infinite loop
* Fix braces warning.
* Implement loopuo by name for sys operands
* Fix incorrect translation which remove else if statements.
* Fix several segfaults
* Rename GetRegFromClass patch
* Fix segfaults and asserts
* Fix segfault
* Move MRI setting to Mapping
* Remove unused code
* Add add_op_X functinos for AArch64.
* Add fill detail functins
* Handle RegWithShiftExtend operands
* Handle TypedVectorList operands.
* Handle ComplexRoatation operands
* Handle MemExtend operands
* Handle ImmRangeScale operands
* Handle ExactFPImm operands
* Handle GPRSeqPairsClass operands
* Handle Imm8OptLsl operands
* Handle ImmScale operands
* Handle LogicalImm operands
* Handle Matrix operands
* Handle SME Matrix tiles and vectors.
* Handle normal operands.
* Fix segfault.
* Handle PostInc operands.
* Reorder VecLayout enum to have no duplicate enum value.
* Handle PredicateAsCounter operands
* Handle ZPRasFPR operands
* Handle VectorIndex operands
* Handle UImm12Offset operands.
* Move reg suffix to enum val to single function.
* Handle SVERegOp operands
* Handle SVELogicalImm operands
* Handle SImm operand
* Handle PrefetchOp operands
* Handle Imm and ImmHex operands
* Handle GPR64as32 and GPR64x8 operands
* Add missing break
* Handle FPImm operand
* Handle ExtendedRegister opreand
* Handle CondCode operands
* Handle BTIHintOp operands
* Handle BarrierOption operands
* Handle BarrierXSOption
* Add not implemeted case again
* Handle ArithExtend operands
* Handle AdrpLabel and AlignedLabel operands
* Handle AMNoIndex operands
* Handle AddSubImm operands
* Handle MSRSystemRegisters and MRSSystemRegister operands
* Handle PSBHntOp and RPRFMOperand operands
* Remove unused variables
* Handle InverseCondCode operands
* Handle ImplicityTypedVectorList operands
* Handle ShiftedRegister operands
* Handle Shifter operands
* Handle SIMDType10Operand operands
* Handle SVCROp operands
* Handle SVEPattern operands
* Handle SVEVecLenSpecifier operands
* Handle SysCROperands
* Handle SysXzrPair operands
* Handle PState operands
* Handle VRegOperands
* Primt SME oeprands.
* Fix cs_operand.h include
* Rename arm64 -> aarch64 in python bindings.
* Add Python bindings for SH
* Fix ARM Python bindings (#2127)
* Restructure auto-sync update scripts.
* Move Helper functions to Updater dir
* Move requirements.txt
* Add basic ASUpdater.py
* Run black.
* Add inc file generater to updater
* Add option to select certain inc files fore generation.
* Enable clean build and implement patcher for inc files.
* Format config
* Patch main header files after inc generation.
* Implement clang-format function (unused yet, because it takes forever.)
* Copy generated inc files to arch dir
* Invert clean option (noramlly we need to clean the build dir.)
* Clearify arg doc
* Rename SystemRegister file for AArch64
* Centralize handling of path variables.
* Check if SystemOperands had to be generated before renaming on of its files.
* Replace class parameters by calling get_path
* Remove updater config which only contained paths.
* Add refactor option.
* Remove more path handling in the Configurator.
* Add translation step to updater.
* Fix includes after CppTranslator was moved into the Updater
* Remove updater config
* Fix several issue in the Configurator
* Fix file operations
* Remove addition argument from translator.
* Add Differ step to updater.
* Add path variable for arch_config
* Add diff step.
* Fix typo
* Introduce .clang-format path variable.
* Remove duplicate functions
* Add option to select update steps to execute.
* Check in write functions for write flag.
* Rename PatchMainHeader -> HeaderPatcher
* Move .gitignore
* Add README to vendor dir.
* Add all system operands to cstool output
* Update cstest with aarch64 changes
* Remove wb flag of aarch64 detail struct
* Set updates_flag after decoding
* Set writeback after decoding.
* Rename ARM64 -> AArch64
* Update printer and op mapping
* Exit normally
* Add AArch64 alias
* Fix some tmeplate function calls
* Fix flag check after rebase.
* Fix build by commentig unnused code.
* Add memory operand flag
* Handle memory operands printed via generic printOperand function.
* Handle UImm memory offsets
* Introduce MEM_REG and MEM_IMM op types
* Handle scaled memory immediates
* Check for op_count before checking for mem op at -1 index.
* Update memory operand flags.
* Pass imm/reg memory ops in set_imm/reg to set_mem.
* Add missing set_sme_operand call and fix assert.
* Remove CS_OP_MEM flag before entering switch.
* Preidcates are registers.
* Add shift info always to the previous operand
* Check for generic system regs
* Handle NumLanes = 0 LaneKind = q case
* Replace printImm call with normal print logic. Otherwise ops get added twice to detail.
* Handle FP operands in printOperand.
* Add access information to float operands.
* Rewrite SME matrix handling.
* Set correct SME layouts and allow for immediate range sme offsets.
* Handle cases of unknown system alias by setting their raw values
* Update cstool and header file with new SME offset handling
* Handle SME Tile lists.
* Fix build error in cstest
* Update MC tests for AArch64
* Handle TLBI operands and fix printing bug.
* Fix: Print signed value as signed.
* Add more system alias to detail.
* Remove duplicate hex prefix
* Set correct values for the register info
* Replace tabs with white spaces
* Move string append logic to own function.
* Set DecodeComplete = true before decoding (as originally in the LLVM code).
* Change type of feature argument, since only LLVM features are passed, not CS groups.
* Imitate lower_bound for the index table binary search.
* Remove trailing comments from test files.
* Print shift amount in decimal
* Save detail of shift alias instructions.
* Add extension details fot ext instruction alias
* Print LSB and width in decimal
* Fix LLVM bug. The feature check for V8_2a doesn't check if all features are enabled.
* Fix lower_bounds check.
For m == 0 we wrap around 0 of cause.
* Fix feature check. Add check for FeatureAll since it includes XS
* Operate on temporary MCInst when trying decoding.
* Add lower_bound behavior to IndexTypeStr binsearch.
* Fix MC tests which were incorrect because of missing FeatureAll check
* Add Alias handling for AArch64
* Update system operands with SYSIMM types and add additional sysop category.
* Add macros for meta programming (ARM64 <-> AArch64 selection).
* Fix union/struct confusion and add raw_value member to uninions.
* Allow to set Syntax and mode options for AArch64
* Fix build warning by using correct type
* Print shift value in decimal
* Add missing call to add_cs_detail.
* Update name map files with normalized names.
* Remove unused function
* Add check if detail should be filled.
* Fill detail for real instructions if only real detail is requested.
* Add always the extension.
* Make dir creation log message debug level
* Implement ADR immediate operand printer.
See: c3484b1fdc
* Check for flag registers beeing written and update flag.
* Move multiple CondCode helpers to aarch64.h because they are so freaking useful.
+ Print CC if it is EQ
* Fix incorrectly initialized CC and VectorLayout.
* Add LSL shift type for extensions.
* Fix case when shift amount is 0
* Fix post-index memory instructions.
* Pass raw immediate through getShiftValue to extract actual shift amount
* Setup AArch64 detail ops.
* Add flag for operands part of a list.
* Set vector indices for all relevant registers.
* Add missing call to add_cs_detail for postIncOperands
* Add ugly yet reliable way to determine post-index addressing mode
* Add support for old Capstone register alias.
* Remove leading space before some alias mnemonics.
* add AARCH64 to `cmake.sh`
* add HAS_AARCH64 to `cs.c`
* should probably just reference `cs_operand.h` in `aarch64.h`
* hint compiler at `AArch64_SYSREG` enum type for casting purposes
* update `Makefile` for AARCH64
leaves `CAPSTONE_HAS_ARM64` supported
* `testFeatureBits` platform function check
`testFeatureBits` should check if the platform function is visible first
* update tests to use AARCH64 convention
* hack: avoid enum casts for `MCInst` Values
Apple compiler really hates typecasting a enum, even if bounded from a unsigned. Lets set the raw_value directly
is a hack and needs proper review
* Check for present detail before accessing it.
* Add CS only groups
* Use general map ins_op type
* Fix build warning about str size computation.
* Disable warning about unitialized value for GCC 11.
Imm is initialized and the warning does not appear
in later versions.
* Use correct include guard for PPC
* Add missing requirements
* Update SystemOperand enums.
* Fix overlapping comparison warning
* Fix reachable assert where OpNum is not of type IMM
* Handle 0.0 operand for fcmp
* Fix incorrect variable passed.
* Fix for MacOS which doesn't know the warning and throws another one.
* Make getExtendEncoding static to fix build warning on MSVC.
* Fix build error: 'missing binary operator before token' by checking __GNUC__
* Add string search to add vector layout info.
* Add missing mem disponents of several ldr and str instructions.
* Add 0 immediates to several instructions.
* Rename v regs to q and d variant.
The cs_regname API can not pass the variant name of the register requested.
So we simply emit the default variant name.
* Fix incorrect enum value.
* Fix tests for system operands.
* Fix syntax issues in tests.
* Rename Arm64 -> AArch64 Python bindings.
* Fix Python bindings C structs.
* Fix generation of constants (ARMCC skipped because it starts with ARM)
* Update const files
* Remove -Wmaybe-uninitialized warning since it fails fuzz build
* Add missing comma
* Fix case
* Fix AArch64 Python bindings:
- Do not generate constants automatically (dscript is way too buggy).
- Update printing of details.
* Rename ARM64 -> AArch64 in test_corpus.py
* Rename test_arm64 -> test_aarch64
* Rename ARM-64 -> AArch64
* Fix diff CI test by disassembling AArch64 at former ARM64 place
* Fix several wrong types and remove unnecessary memebers from Python binding
* Fix: Same printing format of detail for cstool, test_ and test_*.py
* Fix: pass correct op index for mov alias with op[1] == reg wzr.
* Set prfm op manuall in case of unnown sysop. set_imm would add it to an memory operand wihtout base.
* Fix: If barrier ops are not set an assert is reached.
We fix it here by simply getting the immediate as the printing code does.
---------
Co-authored-by: Peace-Maker <peace-maker@wcfan.de>
Co-authored-by: Dayton <5340801+watbulb@users.noreply.github.com>
284 lines
7.7 KiB
Python
Executable File
284 lines
7.7 KiB
Python
Executable File
#!/usr/bin/python
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from capstone import *
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from capstone.arm import *
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from capstone.arm64 import *
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from capstone.mips import *
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from capstone.ppc import *
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from capstone.sparc import *
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from capstone.systemz import *
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from capstone.x86 import *
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from capstone.xcore import *
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from capstone.riscv import *
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import sys
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class GroupTest:
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def __init__(self, name, arch, mode, data):
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self.name = name
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self.arch = arch
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self.mode = mode
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self.data = data
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def run(self):
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print('Testing %s' %self.name)
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cap = Cs(self.arch, self.mode)
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for group_id in xrange(0,255):
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name = self.data.get(group_id)
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res = cap.group_name(group_id)
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if res != name:
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print("ERROR: id = %u expected '%s', but got '%s'" %(group_id, name, res))
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print("")
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arm_dict = {
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ARM_GRP_JUMP: "jump",
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ARM_GRP_CALL: "call",
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ARM_GRP_INT: "int",
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ARM_GRP_PRIVILEGE: "privilege",
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ARM_GRP_CRYPTO: "crypto",
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ARM_GRP_DATABARRIER: "databarrier",
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ARM_GRP_DIVIDE: "divide",
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ARM_GRP_FPARMV8: "fparmv8",
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ARM_GRP_MULTPRO: "multpro",
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ARM_GRP_NEON: "neon",
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ARM_GRP_T2EXTRACTPACK: "T2EXTRACTPACK",
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ARM_GRP_THUMB2DSP: "THUMB2DSP",
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ARM_GRP_TRUSTZONE: "TRUSTZONE",
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ARM_GRP_V4T: "v4t",
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ARM_GRP_V5T: "v5t",
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ARM_GRP_V5TE: "v5te",
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ARM_GRP_V6: "v6",
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ARM_GRP_V6T2: "v6t2",
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ARM_GRP_V7: "v7",
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ARM_GRP_V8: "v8",
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ARM_GRP_VFP2: "vfp2",
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ARM_GRP_VFP3: "vfp3",
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ARM_GRP_VFP4: "vfp4",
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ARM_GRP_ARM: "arm",
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ARM_GRP_MCLASS: "mclass",
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ARM_GRP_NOTMCLASS: "notmclass",
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ARM_GRP_THUMB: "thumb",
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ARM_GRP_THUMB1ONLY: "thumb1only",
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ARM_GRP_THUMB2: "thumb2",
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ARM_GRP_PREV8: "prev8",
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ARM_GRP_FPVMLX: "fpvmlx",
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ARM_GRP_MULOPS: "mulops",
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ARM_GRP_CRC: "crc",
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ARM_GRP_DPVFP: "dpvfp",
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ARM_GRP_V6M: "v6m",
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ARM_GRP_VIRTUALIZATION: "virtualization",
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}
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arm64_dict = {
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AARCH64_GRP_JUMP: "jump",
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AARCH64_GRP_CALL: "call",
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AARCH64_GRP_RET: "return",
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AARCH64_GRP_INT: "int",
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AARCH64_GRP_PRIVILEGE: "privilege",
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AARCH64_GRP_CRYPTO: "crypto",
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AARCH64_GRP_FPARMV8: "fparmv8",
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AARCH64_GRP_NEON: "neon",
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AARCH64_GRP_CRC: "crc"
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}
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mips_dict = {
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MIPS_GRP_JUMP: "jump",
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MIPS_GRP_CALL: "call",
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MIPS_GRP_RET: "ret",
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MIPS_GRP_INT: "int",
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MIPS_GRP_IRET: "iret",
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MIPS_GRP_PRIVILEGE: "privilege",
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MIPS_GRP_BITCOUNT: "bitcount",
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MIPS_GRP_DSP: "dsp",
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MIPS_GRP_DSPR2: "dspr2",
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MIPS_GRP_FPIDX: "fpidx",
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MIPS_GRP_MSA: "msa",
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MIPS_GRP_MIPS32R2: "mips32r2",
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MIPS_GRP_MIPS64: "mips64",
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MIPS_GRP_MIPS64R2: "mips64r2",
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MIPS_GRP_SEINREG: "seinreg",
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MIPS_GRP_STDENC: "stdenc",
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MIPS_GRP_SWAP: "swap",
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MIPS_GRP_MICROMIPS: "micromips",
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MIPS_GRP_MIPS16MODE: "mips16mode",
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MIPS_GRP_FP64BIT: "fp64bit",
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MIPS_GRP_NONANSFPMATH: "nonansfpmath",
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MIPS_GRP_NOTFP64BIT: "notfp64bit",
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MIPS_GRP_NOTINMICROMIPS: "notinmicromips",
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MIPS_GRP_NOTNACL: "notnacl",
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MIPS_GRP_NOTMIPS32R6: "notmips32r6",
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MIPS_GRP_NOTMIPS64R6: "notmips64r6",
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MIPS_GRP_CNMIPS: "cnmips",
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MIPS_GRP_MIPS32: "mips32",
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MIPS_GRP_MIPS32R6: "mips32r6",
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MIPS_GRP_MIPS64R6: "mips64r6",
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MIPS_GRP_MIPS2: "mips2",
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MIPS_GRP_MIPS3: "mips3",
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MIPS_GRP_MIPS3_32: "mips3_32",
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MIPS_GRP_MIPS3_32R2: "mips3_32r2",
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MIPS_GRP_MIPS4_32: "mips4_32",
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MIPS_GRP_MIPS4_32R2: "mips4_32r2",
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MIPS_GRP_MIPS5_32R2: "mips5_32r2",
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MIPS_GRP_GP32BIT: "gp32bit",
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MIPS_GRP_GP64BIT: "gp64bit",
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}
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ppc_dict = {
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PPC_GRP_JUMP: "jump",
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PPC_GRP_ALTIVEC: "altivec",
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PPC_GRP_MODE32: "mode32",
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PPC_GRP_MODE64: "mode64",
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PPC_GRP_BOOKE: "booke",
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PPC_GRP_NOTBOOKE: "notbooke",
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PPC_GRP_SPE: "spe",
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PPC_GRP_VSX: "vsx",
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PPC_GRP_E500: "e500",
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PPC_GRP_PPC4XX: "ppc4xx",
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PPC_GRP_PPC6XX: "ppc6xx",
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PPC_GRP_ICBT: "icbt",
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PPC_GRP_P8ALTIVEC: "p8altivec",
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PPC_GRP_P8VECTOR: "p8vector",
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PPC_GRP_QPX: "qpx",
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PPC_GRP_PS: "ps",
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}
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sparc_dict = {
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SPARC_GRP_JUMP: "jump",
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SPARC_GRP_HARDQUAD: "hardquad",
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SPARC_GRP_V9: "v9",
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SPARC_GRP_VIS: "vis",
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SPARC_GRP_VIS2: "vis2",
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SPARC_GRP_VIS3: "vis3",
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SPARC_GRP_32BIT: "32bit",
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SPARC_GRP_64BIT: "64bit",
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}
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sysz_dict = {
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SYSZ_GRP_JUMP: "jump",
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SYSZ_GRP_DISTINCTOPS: "distinctops",
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SYSZ_GRP_FPEXTENSION: "fpextension",
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SYSZ_GRP_HIGHWORD: "highword",
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SYSZ_GRP_INTERLOCKEDACCESS1: "interlockedaccess1",
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SYSZ_GRP_LOADSTOREONCOND: "loadstoreoncond",
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}
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x86_dict = {
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X86_GRP_JUMP: "jump",
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X86_GRP_CALL: "call",
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X86_GRP_RET: "ret",
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X86_GRP_INT: "int",
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X86_GRP_IRET: "iret",
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X86_GRP_PRIVILEGE: "privilege",
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X86_GRP_VM: "vm",
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X86_GRP_3DNOW: "3dnow",
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X86_GRP_AES: "aes",
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X86_GRP_ADX: "adx",
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X86_GRP_AVX: "avx",
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X86_GRP_AVX2: "avx2",
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X86_GRP_AVX512: "avx512",
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X86_GRP_BMI: "bmi",
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X86_GRP_BMI2: "bmi2",
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X86_GRP_CMOV: "cmov",
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X86_GRP_F16C: "fc16",
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X86_GRP_FMA: "fma",
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X86_GRP_FMA4: "fma4",
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X86_GRP_FSGSBASE: "fsgsbase",
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X86_GRP_HLE: "hle",
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X86_GRP_MMX: "mmx",
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X86_GRP_MODE32: "mode32",
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X86_GRP_MODE64: "mode64",
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X86_GRP_RTM: "rtm",
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X86_GRP_SHA: "sha",
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X86_GRP_SSE1: "sse1",
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X86_GRP_SSE2: "sse2",
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X86_GRP_SSE3: "sse3",
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X86_GRP_SSE41: "sse41",
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X86_GRP_SSE42: "sse42",
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X86_GRP_SSE4A: "sse4a",
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X86_GRP_SSSE3: "ssse3",
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X86_GRP_PCLMUL: "pclmul",
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X86_GRP_XOP: "xop",
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X86_GRP_CDI: "cdi",
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X86_GRP_ERI: "eri",
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X86_GRP_TBM: "tbm",
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X86_GRP_16BITMODE: "16bitmode",
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X86_GRP_NOT64BITMODE: "not64bitmode",
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X86_GRP_SGX: "sgx",
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X86_GRP_DQI: "dqi",
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X86_GRP_BWI: "bwi",
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X86_GRP_PFI: "pfi",
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X86_GRP_VLX: "vlx",
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X86_GRP_SMAP: "smap",
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X86_GRP_NOVLX: "novlx",
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}
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xcore_dict = {
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XCORE_GRP_JUMP: "jump",
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}
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riscv32_dict = {
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RISCV_GRP_JUMP : "jump",
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RISCV_GRP_CALL : "call",
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RISCV_GRP_RET : "ret",
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RISCV_GRP_INT : "int",
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RISCV_GRP_IRET : "iret",
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RISCV_GRP_PRIVILEGE : "privileged",
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RISCV_GRP_BRANCH_RELATIVE: "branch_relative",
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RISCV_GRP_ISRV32 : "isrv32",
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RISCV_GRP_HASSTDEXTA : "hasstdexta",
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RISCV_GRP_HASSTDEXTC : "hasstdextc",
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RISCV_GRP_HASSTDEXTD : "hasstdextd",
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RISCV_GRP_HASSTDEXTF : "hasstdextf",
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RISCV_GRP_HASSTDEXTM : "hasstdextm",
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}
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riscv64_dict = {
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RISCV_GRP_JUMP : "jump",
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RISCV_GRP_CALL : "call",
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RISCV_GRP_RET : "ret",
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RISCV_GRP_INT : "int",
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RISCV_GRP_IRET : "iret",
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RISCV_GRP_PRIVILEGE : "privileged",
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RISCV_GRP_BRANCH_RELATIVE: "branch_relative",
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RISCV_GRP_ISRV64 : "isrv64",
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RISCV_GRP_HASSTDEXTA : "hasstdexta",
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RISCV_GRP_HASSTDEXTC : "hasstdextc",
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RISCV_GRP_HASSTDEXTD : "hasstdextd",
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RISCV_GRP_HASSTDEXTF : "hasstdextf",
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RISCV_GRP_HASSTDEXTM : "hasstdextm",
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}
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tests = [
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GroupTest('arm', CS_ARCH_ARM, CS_MODE_THUMB, arm_dict),
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GroupTest('arm64', CS_ARCH_AARCH64, CS_MODE_ARM, arm64_dict),
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GroupTest('mips', CS_ARCH_MIPS, CS_MODE_MIPS32 | CS_MODE_BIG_ENDIAN, mips_dict),
|
|
GroupTest('ppc', CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, ppc_dict),
|
|
GroupTest('sparc', CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, sparc_dict),
|
|
GroupTest('sysz', CS_ARCH_SYSZ, CS_MODE_BIG_ENDIAN, sysz_dict),
|
|
GroupTest('x86', CS_ARCH_X86, CS_MODE_32, x86_dict),
|
|
GroupTest('xcore', CS_ARCH_XCORE, CS_MODE_BIG_ENDIAN, xcore_dict),
|
|
GroupTest('m68k', CS_ARCH_M68K, CS_MODE_BIG_ENDIAN, xcore_dict),
|
|
GroupTest('riscv32', CS_ARCH_RISCV, CS_MODE_RISCV32, riscv32_dict),
|
|
GroupTest('riscv64', CS_ARCH_RISCV, CS_MODE_RISCV64, riscv64_dict),
|
|
]
|
|
|
|
if __name__ == '__main__':
|
|
args = sys.argv[1:]
|
|
all = len(args) == 0 or 'all' in args
|
|
for t in tests:
|
|
if all or t.name in args:
|
|
t.run()
|
|
else:
|
|
print('Skipping %s' %t.name)
|
|
|