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Bug 1510749 - The AArch64 ISR explicitly allows CSINC to accept ZR. r=nbp

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--HG--
extra : rebase_source : 66b7a76d979bd2aa8c8b228cba39db9310287944
This commit is contained in:
Sean Stangl 2018-11-30 11:21:00 +02:00
parent c3e45765b6
commit 02b6e39ab1
1 changed files with 6 additions and 2 deletions
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8
js/src/jit/arm64/vixl/MacroAssembler-vixl.h
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@ -656,8 +656,12 @@ class MacroAssembler : public js::jit::Assembler {
const Register& rm,
Condition cond) {
VIXL_ASSERT(!rd.IsZero());
VIXL_ASSERT(!rn.IsZero());
VIXL_ASSERT(!rm.IsZero());
// The VIXL source code contains these assertions, but the AArch64 ISR
// explicitly permits the use of zero registers. CSET itself is defined
// in terms of CSINC with WZR/XZR.
//
// VIXL_ASSERT(!rn.IsZero());
// VIXL_ASSERT(!rm.IsZero());
VIXL_ASSERT((cond != al) && (cond != nv));
SingleEmissionCheckScope guard(this);
csinc(rd, rn, rm, cond);