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[X86] Regenerate CSE test with codegen instead of just the instruction count
llvm-svn: 295819
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@ -1,7 +1,42 @@
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; REQUIRES: asserts
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; RUN: llc < %s -march=x86 -mattr=+sse2 -mtriple=i386-apple-darwin -stats 2>&1 | grep asm-printer | grep 13
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+sse2 | FileCheck %s --check-prefix=X32
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+sse2 | FileCheck %s --check-prefix=X64
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define i32 @t(i8* %ref_frame_ptr, i32 %ref_frame_stride, i32 %idxX, i32 %idxY) nounwind {
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; X32-LABEL: t:
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; X32: ## BB#0: ## %entry
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X32-NEXT: imull {{[0-9]+}}(%esp), %ecx
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; X32-NEXT: addl {{[0-9]+}}(%esp), %ecx
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; X32-NEXT: movzwl 4(%eax,%ecx), %edx
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; X32-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; X32-NEXT: movd %edx, %xmm1
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; X32-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
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; X32-NEXT: pxor %xmm1, %xmm1
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; X32-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,1,1,2,4,5,6,7]
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; X32-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; X32-NEXT: movd %xmm0, %eax
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; X32-NEXT: retl
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;
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; X64-LABEL: t:
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; X64: ## BB#0: ## %entry
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; X64-NEXT: ## kill: %EDX<def> %EDX<kill> %RDX<def>
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; X64-NEXT: ## kill: %ESI<def> %ESI<kill> %RSI<def>
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; X64-NEXT: imull %ecx, %esi
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; X64-NEXT: leal (%rsi,%rdx), %eax
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; X64-NEXT: cltq
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; X64-NEXT: leal 4(%rsi,%rdx), %ecx
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; X64-NEXT: movslq %ecx, %rcx
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; X64-NEXT: movzwl (%rdi,%rcx), %ecx
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; X64-NEXT: shlq $32, %rcx
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; X64-NEXT: movl (%rdi,%rax), %eax
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; X64-NEXT: orq %rcx, %rax
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; X64-NEXT: movd %rax, %xmm0
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; X64-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero
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; X64-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,1,1,2,4,5,6,7]
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; X64-NEXT: movd %xmm0, %eax
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; X64-NEXT: retq
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entry:
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%tmp7 = mul i32 %idxY, %ref_frame_stride ; <i32> [#uses=2]
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%tmp9 = add i32 %tmp7, %idxX ; <i32> [#uses=1]
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