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Add Alpha and LoongArch to the CI tests.
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parent
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@ -1,7 +1,7 @@
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#!/bin/sh
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# Compare the generated tables of our refactored TableGen to the original ones.
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archs="AArch64 ARM PPC"
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archs="AArch64 ARM PPC LoongArch"
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file_names="GenAsmWriter GenDisassemblerTables GenInstrInfo GenRegisterInfo GenSubtargetInfo GenSystemOperands"
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release="18"
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repo_root=$(git rev-parse --show-toplevel)
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@ -3,7 +3,7 @@
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# Compare the generated tables of our refactored TableGen to the original ones.
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# We skip Alpha because it is no longer supported by upstream LLVM
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archs="AArch64 ARM PPC"
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archs="AArch64 ARM PPC LoongArch Alpha"
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file_names="GenAsmWriter GenDisassemblerTables GenInstrInfo GenRegisterInfo GenSubtargetInfo GenSystemOperands"
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release="18"
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repo_root=$(git rev-parse --show-toplevel)
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@ -48,7 +48,7 @@ gen_all()
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elif [ $file_name = "GenSubtargetInfo" ]; then
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$repo_root/build/bin/llvm-tblgen --gen-subtarget "$table_type" -o "$out_file" -I "$arch_include" -I "$repo_root/llvm/include" "$arch_include/$arch.td"
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elif [ $file_name = "GenSystemOperands" ]; then
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if [ $arch != "PPC" ] ; then
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if [ $arch != "PPC" ] && [ $arch != "LoongArch" ] ; then
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$repo_root/build/bin/llvm-tblgen --gen-searchable-tables "$table_type" -o "$out_file" -I "$arch_include" -I "$repo_root/llvm/include" "$arch_include/$arch.td"
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fi
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else
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@ -1,6 +1,6 @@
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#!/bin/sh
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archs="AArch64 ARM PPC"
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archs="AArch64 ARM PPC LoongArch Alpha"
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file_names="GenAsmWriter GenDisassemblerTables GenInstrInfo GenRegisterInfo GenSubtargetInfo GenSystemOperands"
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release="18"
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repo_root=$(git rev-parse --show-toplevel)
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@ -45,7 +45,7 @@ gen_all()
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elif [ $file_name = "GenSubtargetInfo" ]; then
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$repo_root/build/bin/llvm-tblgen --gen-subtarget "$table_type" -o "$out_file" -I "$arch_include" -I "$repo_root/llvm/include" "$arch_include/$arch.td"
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elif [ $file_name = "GenSystemOperands" ]; then
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if [ $arch != "PPC" ] ; then
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if [ $arch != "PPC" ] && [ $arch != "LoongArch" ] ; then
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$repo_root/build/bin/llvm-tblgen --gen-searchable-tables "$table_type" -o "$out_file" -I "$arch_include" -I "$repo_root/llvm/include" "$arch_include/$arch.td"
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fi
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else
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@ -48,9 +48,6 @@ include "AlphaSchedule.td"
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include "AlphaInstrInfo.td"
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def AlphaInstrInfo : InstrInfo {
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let noNamedPositionallyEncodedOperands = 1;
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let useDeprecatedPositionallyEncodedOperands = 1;
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let decodePositionallyEncodedOperands = 1;
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}
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//===----------------------------------------------------------------------===//
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