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Add Alpha and LoongArch to the CI tests.

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Rot127 2024-06-04 03:29:20 -05:00 committed by Rot127
parent 3c619b615d
commit 5943ec6923
4 changed files with 5 additions and 8 deletions
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2
compare_tblgen_output.sh
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@ -1,7 +1,7 @@
#!/bin/sh #!/bin/sh
# Compare the generated tables of our refactored TableGen to the original ones. # Compare the generated tables of our refactored TableGen to the original ones.
archs="AArch64 ARM PPC" archs="AArch64 ARM PPC LoongArch"
file_names="GenAsmWriter GenDisassemblerTables GenInstrInfo GenRegisterInfo GenSubtargetInfo GenSystemOperands" file_names="GenAsmWriter GenDisassemblerTables GenInstrInfo GenRegisterInfo GenSubtargetInfo GenSystemOperands"
release="18" release="18"
repo_root=$(git rev-parse --show-toplevel) repo_root=$(git rev-parse --show-toplevel)

4
gen_cs_tables.sh
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@ -3,7 +3,7 @@
# Compare the generated tables of our refactored TableGen to the original ones. # Compare the generated tables of our refactored TableGen to the original ones.
# We skip Alpha because it is no longer supported by upstream LLVM # We skip Alpha because it is no longer supported by upstream LLVM
archs="AArch64 ARM PPC" archs="AArch64 ARM PPC LoongArch Alpha"
file_names="GenAsmWriter GenDisassemblerTables GenInstrInfo GenRegisterInfo GenSubtargetInfo GenSystemOperands" file_names="GenAsmWriter GenDisassemblerTables GenInstrInfo GenRegisterInfo GenSubtargetInfo GenSystemOperands"
release="18" release="18"
repo_root=$(git rev-parse --show-toplevel) repo_root=$(git rev-parse --show-toplevel)
@ -48,7 +48,7 @@ gen_all()
elif [ $file_name = "GenSubtargetInfo" ]; then elif [ $file_name = "GenSubtargetInfo" ]; then
$repo_root/build/bin/llvm-tblgen --gen-subtarget "$table_type" -o "$out_file" -I "$arch_include" -I "$repo_root/llvm/include" "$arch_include/$arch.td" $repo_root/build/bin/llvm-tblgen --gen-subtarget "$table_type" -o "$out_file" -I "$arch_include" -I "$repo_root/llvm/include" "$arch_include/$arch.td"
elif [ $file_name = "GenSystemOperands" ]; then elif [ $file_name = "GenSystemOperands" ]; then
if [ $arch != "PPC" ] ; then if [ $arch != "PPC" ] && [ $arch != "LoongArch" ] ; then
$repo_root/build/bin/llvm-tblgen --gen-searchable-tables "$table_type" -o "$out_file" -I "$arch_include" -I "$repo_root/llvm/include" "$arch_include/$arch.td" $repo_root/build/bin/llvm-tblgen --gen-searchable-tables "$table_type" -o "$out_file" -I "$arch_include" -I "$repo_root/llvm/include" "$arch_include/$arch.td"
fi fi
else else

4
gen_llvm_tables.sh
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@ -1,6 +1,6 @@
#!/bin/sh #!/bin/sh
archs="AArch64 ARM PPC" archs="AArch64 ARM PPC LoongArch Alpha"
file_names="GenAsmWriter GenDisassemblerTables GenInstrInfo GenRegisterInfo GenSubtargetInfo GenSystemOperands" file_names="GenAsmWriter GenDisassemblerTables GenInstrInfo GenRegisterInfo GenSubtargetInfo GenSystemOperands"
release="18" release="18"
repo_root=$(git rev-parse --show-toplevel) repo_root=$(git rev-parse --show-toplevel)
@ -45,7 +45,7 @@ gen_all()
elif [ $file_name = "GenSubtargetInfo" ]; then elif [ $file_name = "GenSubtargetInfo" ]; then
$repo_root/build/bin/llvm-tblgen --gen-subtarget "$table_type" -o "$out_file" -I "$arch_include" -I "$repo_root/llvm/include" "$arch_include/$arch.td" $repo_root/build/bin/llvm-tblgen --gen-subtarget "$table_type" -o "$out_file" -I "$arch_include" -I "$repo_root/llvm/include" "$arch_include/$arch.td"
elif [ $file_name = "GenSystemOperands" ]; then elif [ $file_name = "GenSystemOperands" ]; then
if [ $arch != "PPC" ] ; then if [ $arch != "PPC" ] && [ $arch != "LoongArch" ] ; then
$repo_root/build/bin/llvm-tblgen --gen-searchable-tables "$table_type" -o "$out_file" -I "$arch_include" -I "$repo_root/llvm/include" "$arch_include/$arch.td" $repo_root/build/bin/llvm-tblgen --gen-searchable-tables "$table_type" -o "$out_file" -I "$arch_include" -I "$repo_root/llvm/include" "$arch_include/$arch.td"
fi fi
else else

3
llvm/lib/Target/Alpha/Alpha.td
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@ -48,9 +48,6 @@ include "AlphaSchedule.td"
include "AlphaInstrInfo.td" include "AlphaInstrInfo.td"
def AlphaInstrInfo : InstrInfo { def AlphaInstrInfo : InstrInfo {
let noNamedPositionallyEncodedOperands = 1;
let useDeprecatedPositionallyEncodedOperands = 1;
let decodePositionallyEncodedOperands = 1;
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//