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Fix off-by-one error in armv7 mach-o corefile register context
The sanity check on the size of the register context we found in the corefile was off by one, so lldb would not add the register contents. Add a test case to ensure it doesn't regress. Differential Revision: https://reviews.llvm.org/D149224 rdar://108306070
This commit is contained in:
Jason Molenda
parent
6e8ce16797
commit
6b6bac2cd8
@ -531,21 +531,18 @@ public:
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lldb::offset_t next_thread_state = offset + (count * 4);
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switch (flavor) {
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case GPRAltRegSet:
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case GPRRegSet:
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// On ARM, the CPSR register is also included in the count but it is
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// not included in gpr.r so loop until (count-1).
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// Prevent static analysis warnings by explicitly contstraining 'count'
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// to acceptable range. Handle possible underflow of count-1
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if (count > 0 && count <= sizeof(gpr.r) / sizeof(gpr.r[0])) {
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case GPRRegSet: {
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// r0-r15, plus CPSR
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uint32_t gpr_buf_count = (sizeof(gpr.r) / sizeof(gpr.r[0])) + 1;
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if (count == gpr_buf_count) {
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for (uint32_t i = 0; i < (count - 1); ++i) {
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gpr.r[i] = data.GetU32(&offset);
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}
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}
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// Save cpsr explicitly.
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gpr.cpsr = data.GetU32(&offset);
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gpr.cpsr = data.GetU32(&offset);
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SetError(GPRRegSet, Read, 0);
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SetError(GPRRegSet, Read, 0);
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}
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}
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offset = next_thread_state;
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break;
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6
lldb/test/API/macosx/arm-corefile-regctx/Makefile
Normal file
6
lldb/test/API/macosx/arm-corefile-regctx/Makefile
Normal file
@ -0,0 +1,6 @@
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MAKE_DSYM := NO
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CXX_SOURCES := create-arm-corefiles.cpp
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include Makefile.rules
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@ -0,0 +1,69 @@
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"""Test that Mach-O armv7/arm64 corefile register contexts are read by lldb."""
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import os
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import re
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import subprocess
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import lldb
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from lldbsuite.test.decorators import *
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from lldbsuite.test.lldbtest import *
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from lldbsuite.test import lldbutil
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class TestArmMachoCorefileRegctx(TestBase):
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NO_DEBUG_INFO_TESTCASE = True
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@skipUnlessDarwin
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def setUp(self):
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TestBase.setUp(self)
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self.build()
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self.create_corefile = self.getBuildArtifact("a.out")
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self.corefile = self.getBuildArtifact("core")
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def test_armv7_corefile(self):
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### Create corefile
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retcode = call(self.create_corefile + " armv7 " + self.corefile, shell=True)
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target = self.dbg.CreateTarget('')
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err = lldb.SBError()
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process = target.LoadCore(self.corefile)
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self.assertEqual(process.IsValid(), True)
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thread = process.GetSelectedThread()
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frame = thread.GetSelectedFrame()
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lr = frame.FindRegister("lr")
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self.assertTrue(lr.IsValid())
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self.assertEqual(lr.GetValueAsUnsigned(), 0x000f0000)
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pc = frame.FindRegister("pc")
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self.assertTrue(pc.IsValid())
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self.assertEqual(pc.GetValueAsUnsigned(), 0x00100000)
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exception = frame.FindRegister("exception")
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self.assertTrue(exception.IsValid())
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self.assertEqual(exception.GetValueAsUnsigned(), 0x00003f5c)
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def test_arm64_corefile(self):
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### Create corefile
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retcode = call(self.create_corefile + " arm64 " + self.corefile, shell=True)
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target = self.dbg.CreateTarget('')
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err = lldb.SBError()
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process = target.LoadCore(self.corefile)
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self.assertEqual(process.IsValid(), True)
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thread = process.GetSelectedThread()
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frame = thread.GetSelectedFrame()
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lr = frame.FindRegister("lr")
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self.assertTrue(lr.IsValid())
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self.assertEqual(lr.GetValueAsUnsigned(), 0x000000018cd97f28)
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pc = frame.FindRegister("pc")
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self.assertTrue(pc.IsValid())
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self.assertEqual(pc.GetValueAsUnsigned(), 0x0000000100003f5c)
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exception = frame.FindRegister("far")
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self.assertTrue(exception.IsValid())
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self.assertEqual(exception.GetValueAsUnsigned(), 0x0000000100003f5c)
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@ -0,0 +1,199 @@
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#include <mach-o/loader.h>
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#include <mach/thread_status.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string>
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#include <vector>
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union uint32_buf {
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uint8_t bytebuf[4];
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uint32_t val;
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};
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union uint64_buf {
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uint8_t bytebuf[8];
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uint64_t val;
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};
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void add_uint64(std::vector<uint8_t> &buf, uint64_t val) {
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uint64_buf conv;
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conv.val = val;
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for (int i = 0; i < 8; i++)
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buf.push_back(conv.bytebuf[i]);
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}
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void add_uint32(std::vector<uint8_t> &buf, uint32_t val) {
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uint32_buf conv;
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conv.val = val;
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for (int i = 0; i < 4; i++)
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buf.push_back(conv.bytebuf[i]);
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}
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std::vector<uint8_t> armv7_lc_thread_load_command() {
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std::vector<uint8_t> data;
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add_uint32(data, LC_THREAD); // thread_command.cmd
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add_uint32(data, 104); // thread_command.cmdsize
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add_uint32(data, ARM_THREAD_STATE); // thread_command.flavor
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add_uint32(data, ARM_THREAD_STATE_COUNT); // thread_command.count
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add_uint32(data, 0x00010000); // r0
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add_uint32(data, 0x00020000); // r1
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add_uint32(data, 0x00030000); // r2
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add_uint32(data, 0x00040000); // r3
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add_uint32(data, 0x00050000); // r4
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add_uint32(data, 0x00060000); // r5
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add_uint32(data, 0x00070000); // r6
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add_uint32(data, 0x00080000); // r7
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add_uint32(data, 0x00090000); // r8
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add_uint32(data, 0x000a0000); // r9
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add_uint32(data, 0x000b0000); // r10
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add_uint32(data, 0x000c0000); // r11
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add_uint32(data, 0x000d0000); // r12
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add_uint32(data, 0x000e0000); // sp
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add_uint32(data, 0x000f0000); // lr
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add_uint32(data, 0x00100000); // pc
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add_uint32(data, 0x00110000); // cpsr
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add_uint32(data, ARM_EXCEPTION_STATE); // thread_command.flavor
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add_uint32(data, ARM_EXCEPTION_STATE_COUNT); // thread_command.count
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add_uint32(data, 0x00003f5c); // far
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add_uint32(data, 0xf2000000); // esr
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add_uint32(data, 0x00000000); // exception
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return data;
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}
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std::vector<uint8_t> arm64_lc_thread_load_command() {
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std::vector<uint8_t> data;
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add_uint32(data, LC_THREAD); // thread_command.cmd
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add_uint32(data, 312); // thread_command.cmdsize
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add_uint32(data, ARM_THREAD_STATE64); // thread_command.flavor
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add_uint32(data, ARM_THREAD_STATE64_COUNT); // thread_command.count
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add_uint64(data, 0x0000000000000001); // x0
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add_uint64(data, 0x000000016fdff3c0); // x1
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add_uint64(data, 0x000000016fdff3d0); // x2
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add_uint64(data, 0x000000016fdff510); // x3
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add_uint64(data, 0x0000000000000000); // x4
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add_uint64(data, 0x0000000000000000); // x5
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add_uint64(data, 0x0000000000000000); // x6
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add_uint64(data, 0x0000000000000000); // x7
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add_uint64(data, 0x000000010000d910); // x8
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add_uint64(data, 0x0000000000000001); // x9
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add_uint64(data, 0xe1e88de000000000); // x10
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add_uint64(data, 0x0000000000000003); // x11
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add_uint64(data, 0x0000000000000148); // x12
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add_uint64(data, 0x0000000000004000); // x13
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add_uint64(data, 0x0000000000000008); // x14
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add_uint64(data, 0x0000000000000000); // x15
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add_uint64(data, 0x0000000000000000); // x16
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add_uint64(data, 0x0000000100003f5c); // x17
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add_uint64(data, 0x0000000000000000); // x18
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add_uint64(data, 0x0000000100003f5c); // x19
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add_uint64(data, 0x000000010000c000); // x20
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add_uint64(data, 0x000000010000d910); // x21
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add_uint64(data, 0x000000016fdff250); // x22
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add_uint64(data, 0x000000018ce12366); // x23
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add_uint64(data, 0x000000016fdff1d0); // x24
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add_uint64(data, 0x0000000000000001); // x25
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add_uint64(data, 0x0000000000000000); // x26
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add_uint64(data, 0x0000000000000000); // x27
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add_uint64(data, 0x0000000000000000); // x28
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add_uint64(data, 0x000000016fdff3a0); // fp
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add_uint64(data, 0x000000018cd97f28); // lr
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add_uint64(data, 0x000000016fdff140); // sp
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add_uint64(data, 0x0000000100003f5c); // pc
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add_uint32(data, 0x80001000); // cpsr
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add_uint32(data, 0x00000000); // padding
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add_uint32(data, ARM_EXCEPTION_STATE64); // thread_command.flavor
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add_uint32(data, ARM_EXCEPTION_STATE64_COUNT); // thread_command.count
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add_uint64(data, 0x0000000100003f5c); // far
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add_uint32(data, 0xf2000000); // esr
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add_uint32(data, 0x00000000); // exception
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return data;
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}
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enum arch { unspecified, armv7, arm64 };
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int main(int argc, char **argv) {
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if (argc != 3) {
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fprintf(stderr,
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"usage: create-arm-corefiles [armv7|arm64] <output-core-name>\n");
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exit(1);
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}
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arch arch = unspecified;
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if (strcmp(argv[1], "armv7") == 0)
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arch = armv7;
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else if (strcmp(argv[1], "arm64") == 0)
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arch = arm64;
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else {
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fprintf(stderr, "unrecognized architecture %s\n", argv[1]);
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exit(1);
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}
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// An array of load commands (in the form of byte arrays)
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std::vector<std::vector<uint8_t>> load_commands;
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// An array of corefile contents (page data, lc_note data, etc)
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std::vector<uint8_t> payload;
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// First add all the load commands / payload so we can figure out how large
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// the load commands will actually be.
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if (arch == armv7)
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load_commands.push_back(armv7_lc_thread_load_command());
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else if (arch == arm64)
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load_commands.push_back(arm64_lc_thread_load_command());
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int size_of_load_commands = 0;
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for (const auto &lc : load_commands)
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size_of_load_commands += lc.size();
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int header_and_load_cmd_room =
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sizeof(struct mach_header_64) + size_of_load_commands;
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// Erase the load commands / payload now that we know how much space is
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// needed, redo it.
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load_commands.clear();
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payload.clear();
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if (arch == armv7)
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load_commands.push_back(armv7_lc_thread_load_command());
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else if (arch == arm64)
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load_commands.push_back(arm64_lc_thread_load_command());
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struct mach_header_64 mh;
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mh.magic = MH_MAGIC_64;
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if (arch == armv7) {
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mh.cputype = CPU_TYPE_ARM;
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mh.cpusubtype = CPU_SUBTYPE_ARM_V7M;
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} else if (arch == arm64) {
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mh.cputype = CPU_TYPE_ARM64;
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mh.cpusubtype = CPU_SUBTYPE_ARM64_ALL;
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}
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mh.filetype = MH_CORE;
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mh.ncmds = load_commands.size();
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mh.sizeofcmds = size_of_load_commands;
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mh.flags = 0;
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mh.reserved = 0;
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FILE *f = fopen(argv[2], "w");
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if (f == nullptr) {
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fprintf(stderr, "Unable to open file %s for writing\n", argv[2]);
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exit(1);
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}
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fwrite(&mh, sizeof(struct mach_header_64), 1, f);
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for (const auto &lc : load_commands)
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fwrite(lc.data(), lc.size(), 1, f);
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fseek(f, header_and_load_cmd_room, SEEK_SET);
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fwrite(payload.data(), payload.size(), 1, f);
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fclose(f);
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}
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