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Clean up my own mess.

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X86 lowering normalize vector 0 to v4i32. However DAGCombine can fold (sub x, x) -> 0 after legalization. It can create a zero vector of a type that's not expected (e.g. v8i16). We don't want to disable the optimization since leaving a (sub x, x) is really bad. Add isel patterns for other types of vector 0 to ensure correctness. It's highly unlikely to happen other than in bugpoint reduced test cases.

llvm-svn: 48279
This commit is contained in:
Evan Cheng 2008-03-12 07:02:50 +00:00
parent 944b1c76ab
commit 99ee78ef63
3 changed files with 15 additions and 7 deletions
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8
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@ -1102,14 +1102,8 @@ SDOperand DAGCombiner::visitSUB(SDNode *N) {
}
// fold (sub x, x) -> 0
if (N0 == N1) {
if (AfterLegalize && ISD::isBuildVectorAllZeros(N0.Val))
// For example, zero vectors might be normalized to a particular vector
// type to ensure they are CSE'd. Avoid issuing zero vector nodes of
// *unexpected* type after legalization.
return N0;
if (N0 == N1)
return DAG.getConstant(0, N->getValueType(0));
}
// fold (sub c1, c2) -> c1-c2
if (N0C && N1C)
return DAG.getNode(ISD::SUB, VT, N0, N1);

6
llvm/lib/Target/X86/X86InstrMMX.td
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@ -510,6 +510,12 @@ let isReMaterializable = 1 in {
[(set VR64:$dst, (v2i32 immAllOnesV))]>;
}
let Predicates = [HasMMX] in {
def : Pat<(v1i64 immAllZerosV), (MMX_V_SET0)>;
def : Pat<(v4i16 immAllZerosV), (MMX_V_SET0)>;
def : Pat<(v8i8 immAllZerosV), (MMX_V_SET0)>;
}
//===----------------------------------------------------------------------===//
// Non-Instruction Patterns
//===----------------------------------------------------------------------===//

8
llvm/lib/Target/X86/X86InstrSSE.td
View File

@ -969,6 +969,14 @@ def V_SET0 : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins),
"xorps\t$dst, $dst",
[(set VR128:$dst, (v4i32 immAllZerosV))]>;
let Predicates = [HasSSE1] in {
def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
def : Pat<(v4f32 immAllZerosV), (V_SET0)>;
}
// FR32 to 128-bit vector conversion.
def MOVSS2PSrr : SSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins FR32:$src),
"movss\t{$src, $dst|$dst, $src}",