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commit
d1baa87528
@ -16,12 +16,13 @@ def PPCDispRID12Operand : AsmOperandClass {
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}
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def dispRID12 : Operand<iPTR> {
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let PrintMethod = "printS12ImmOperand";
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let ParserMatchClass = PPCDispRID12Operand;
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let OperandType = "OPERAND_IMMEDIATE";
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}
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def memrid12 : Operand<iPTR> { // Paired Single displacement where imm is 12 bits.
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let PrintMethod = "printMemRegImm";
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let PrintMethod = "printMemRegImmPS";
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let MIOperandInfo = (ops dispRID12:$imm, ptr_rc_nor0:$reg);
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let OperandType = "OPERAND_MEMORY";
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}
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@ -3052,7 +3052,11 @@ void printOpPrintGroupEnum(StringRef const &TargetName,
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"SVELogicalImm_int16_t",
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"SVELogicalImm_int32_t",
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"SVELogicalImm_int64_t",
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"ZPRasFPR_128"};
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"ZPRasFPR_128"
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};
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static const std::set<std::string> PPCExceptions = {
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"S12ImmOperand", // PS S12 immediates. Used as memory disponent.
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};
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bool NoExceptions = false;
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const std::set<std::string> *Exc;
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@ -3060,6 +3064,8 @@ void printOpPrintGroupEnum(StringRef const &TargetName,
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Exc = &ARMExceptions;
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else if (TargetName == "AArch64")
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Exc = &AArch64Exceptions;
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else if (TargetName == "PPC")
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Exc = &PPCExceptions;
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else
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NoExceptions = true;
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