71 Commits

Author SHA1 Message Date
Bill Wendling
d163405df8 Remove tabs.
llvm-svn: 160475
2012-07-19 00:04:14 +00:00
Nick Lewycky
765c699370 Remove ParentMap. You can just ask the domnode for its parent. No functionality
change.

Move the "Not profitable, avoid CSE!" debug message next to where we fail the
check for profitability and use a different message for avoiding CSE due to
being in different register classes.

llvm-svn: 159729
2012-07-05 06:19:21 +00:00
Jakob Stoklund Olesen
92a0083944 Switch some getAliasSet clients to MCRegAliasIterator.
MCRegAliasIterator can optionally visit the register itself, allowing
for simpler code.

llvm-svn: 157837
2012-06-01 20:36:54 +00:00
Craig Topper
1d32658877 Use uint16_t to store register overlaps to reduce static data.
llvm-svn: 152001
2012-03-04 10:43:23 +00:00
Jakob Stoklund Olesen
4c5ad2b812 Handle regmasks in MachineCSE.
Don't attempt to extend physreg live ranges across calls.

<rdar://problem/10942095>

llvm-svn: 151610
2012-02-28 02:08:50 +00:00
Lang Hames
5bade3dc6e Re-enable 150652 and 150654 - Make FPSCR non-reserved, and make MachineCSE bail on reserved registers. This *should* be safe as of r150786.
llvm-svn: 150769
2012-02-17 00:27:16 +00:00
Lang Hames
55a2a96153 Oop - r150653 + r150654 broke one of my test cases. Backing out for now...
llvm-svn: 150655
2012-02-16 02:32:10 +00:00
Lang Hames
2055493b97 MachineCSE shouldn't extend the live ranges of reserved or allocatable registers.
llvm-svn: 150653
2012-02-16 02:19:35 +00:00
Andrew Trick
1fa5bcbe2a Codegen pass definition cleanup. No functionality.
Moving toward a uniform style of pass definition to allow easier target configuration.
Globally declare Pass ID.
Globally declare pass initializer.
Use INITIALIZE_PASS consistently.
Add a call to the initializer from CodeGen.cpp.
Remove redundant "createPass" functions and "getPassName" methods.

While cleaning up declarations, cleaned up comments (sorry for large diff).

llvm-svn: 150100
2012-02-08 21:23:13 +00:00
Andrew Trick
9e761997d8 whitespace
llvm-svn: 150094
2012-02-08 21:22:43 +00:00
Duncan Sands
ae22c60f90 Persuade GCC that there is nothing worth warning about here (there isn't).
llvm-svn: 149834
2012-02-05 14:20:11 +00:00
Evan Cheng
d9725a38d6 Avoid CSE of instructions which define physical registers across MBBs unless
the physical registers are not allocatable.

llvm-svn: 147902
2012-01-11 00:38:11 +00:00
Evan Cheng
0be4144a68 Allow machine-cse to look across MBB boundary when cse'ing instructions that
define physical registers. It's currently very restrictive, only catching
cases where the CE is in an immediate (and only) predecessor. But it catches
a surprising large number of cases.

rdar://10660865

llvm-svn: 147827
2012-01-10 02:02:58 +00:00
Evan Cheng
7f8e563a69 Add bundle aware API for querying instruction properties and switch the code
generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.

For properties like mayLoad / mayStore, look into the bundle and if any of the
bundled instructions has the property it would return true.
For properties like isPredicable, only return true if *all* of the bundled
instructions have the property.
For properties like canFoldAsLoad, isCompare, conservatively return false for
bundles.

llvm-svn: 146026
2011-12-07 07:15:52 +00:00
Bill Wendling
3e5409df77 We need to verify that the machine instruction we're using as a replacement for
our current machine instruction defines a register with the same register class
as what's being replaced. This showed up in the SPEC 403.gcc benchmark, where it
would ICE because a tail call was expecting one register class but was given
another. (The machine instruction verifier catches this situation.)
<rdar://problem/10270968>

llvm-svn: 141830
2011-10-12 23:03:40 +00:00
Evan Cheng
6cc775f905 - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and
sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.

llvm-svn: 134021
2011-06-28 19:10:37 +00:00
Eli Friedman
5401962643 Re-revert r130877; it's apparently causing a regression on 197.parser,
possibly related to cbnz formation.

llvm-svn: 130977
2011-05-06 05:23:07 +00:00
Eli Friedman
2311bdfa7b Minor correction to r130877; fixes PR9846 and hopefully the buildbot failures.
llvm-svn: 130925
2011-05-05 16:18:11 +00:00
Eli Friedman
0fe4608af2 Re-commit r130862 with a minor change to avoid an iterator running off the edge in some cases.
Original message:

Teach MachineCSE how to do simple cross-block CSE involving physregs.  This allows, for example, eliminating duplicate cmpl's on x86. Part of rdar://problem/8259436 .

llvm-svn: 130877
2011-05-04 22:10:36 +00:00
Eli Friedman
3bd79ba856 Back out r130862; it appears to be breaking bootstrap.
llvm-svn: 130867
2011-05-04 20:48:42 +00:00
Eli Friedman
a16fc2fec0 Teach MachineCSE how to do simple cross-block CSE involving physregs. This allows, for example, eliminating duplicate cmpl's on x86. Part of rdar://problem/8259436 .
llvm-svn: 130862
2011-05-04 19:54:24 +00:00
Evan Cheng
fe917efc8b Fix a couple of places where changes are made but not tracked.
llvm-svn: 129287
2011-04-11 18:47:20 +00:00
Chris Lattner
6c8b8dd522 fit in 80 cols and use MBB::isSuccessor instead of a hand
rolled std::find.

llvm-svn: 123164
2011-01-10 07:51:31 +00:00
Jakob Stoklund Olesen
2fb5b31578 Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic.
These functions not longer assert when passed 0, but simply return false instead.

No functional change intended.

llvm-svn: 123155
2011-01-10 02:58:51 +00:00
Evan Cheng
6eb516dbea Do not model all INLINEASM instructions as having unmodelled side effects.
Instead encode llvm IR level property "HasSideEffects" in an operand (shared
with IsAlignStack). Added MachineInstrs::hasUnmodeledSideEffects() to check
the operand when the instruction is an INLINEASM.

This allows memory instructions to be moved around INLINEASM instructions.

llvm-svn: 123044
2011-01-07 23:50:32 +00:00
Cameron Zwarich
18f164f7c9 Use a RecyclingAllocator to allocate values for MachineCSE's ScopedHashTable for
a 28% speedup of MachineCSE time on 403.gcc.

llvm-svn: 122735
2011-01-03 04:07:46 +00:00
Evan Cheng
b7ff5a0f20 Teach machine cse to commute instructions.
llvm-svn: 121903
2010-12-15 22:16:21 +00:00
Evan Cheng
2b3f25e031 Teach machine cse to eliminate instructions with multiple physreg uses and defs. rdar://8610857.
llvm-svn: 117745
2010-10-29 23:36:03 +00:00
Owen Anderson
6c18d1aac0 Get rid of static constructors for pass registration. Instead, every pass exposes an initializeMyPassFunction(), which
must be called in the pass's constructor.  This function uses static dependency declarations to recursively initialize
the pass's dependencies.

Clients that only create passes through the createFooPass() APIs will require no changes.  Clients that want to use the
CommandLine options for passes will need to manually call the appropriate initialization functions in PassInitialization.h
before parsing commandline arguments.

I have tested this with all standard configurations of clang and llvm-gcc on Darwin.  It is possible that there are problems
with the static dependencies that will only be visible with non-standard options.  If you encounter any crash in pass
registration/creation, please send the testcase to me directly.

llvm-svn: 116820
2010-10-19 17:21:58 +00:00
Owen Anderson
8ac477ffb5 Begin adding static dependence information to passes, which will allow us to
perform initialization without static constructors AND without explicit initialization
by the client.  For the moment, passes are required to initialize both their
(potential) dependencies and any passes they preserve.  I hope to be able to relax
the latter requirement in the future.

llvm-svn: 116334
2010-10-12 19:48:12 +00:00
Owen Anderson
df7a4f2515 Now with fewer extraneous semicolons!
llvm-svn: 115996
2010-10-07 22:25:06 +00:00
Jakob Stoklund Olesen
18842783cc Add MachineRegisterInfo::constrainRegClass and use it in MachineCSE.
This function is intended to be used when inserting a machine instruction that
trivially restricts the legal registers, like LEA requiring a GR32_NOSP
argument.

llvm-svn: 115875
2010-10-06 23:54:39 +00:00
Evan Cheng
b08377e0db Machine CSE was forgetting to clear some data structures.
llvm-svn: 114222
2010-09-17 21:59:42 +00:00
Evan Cheng
0dcd3362bd Fix a potential bug that can cause miscomparison with and without debug info.
llvm-svn: 114220
2010-09-17 21:56:26 +00:00
Evan Cheng
e0db9d01d9 Machine CSE preserves CFG. Pass manager was freeing machineloopinfo after machine cse before.
llvm-svn: 111281
2010-08-17 20:57:42 +00:00
Owen Anderson
a7aed18624 Reapply r110396, with fixes to appease the Linux buildbot gods.
llvm-svn: 110460
2010-08-06 18:33:48 +00:00
Owen Anderson
bda59bd247 Revert r110396 to fix buildbots.
llvm-svn: 110410
2010-08-06 00:23:35 +00:00
Owen Anderson
755aceb5d0 Don't use PassInfo* as a type identifier for passes. Instead, use the address of the static
ID member as the sole unique type identifier.  Clean up APIs related to this change.

llvm-svn: 110396
2010-08-05 23:42:04 +00:00
Owen Anderson
a57b97e7e7 Fix batch of converting RegisterPass<> to INTIALIZE_PASS().
llvm-svn: 109045
2010-07-21 22:09:45 +00:00
Jakob Stoklund Olesen
37c42a3d02 Remove many calls to TII::isMoveInstr. Targets should be producing COPY anyway.
TII::isMoveInstr is going tobe completely removed.

llvm-svn: 108507
2010-07-16 04:45:42 +00:00
Jakob Stoklund Olesen
00264624a9 Convert EXTRACT_SUBREG to COPY when emitting machine instrs.
EXTRACT_SUBREG no longer appears as a machine instruction. Use COPY instead.

Add isCopy() checks in many places using isMoveInstr() and isExtractSubreg().
The isMoveInstr hook will be removed later.

llvm-svn: 107879
2010-07-08 16:40:22 +00:00
Jakob Stoklund Olesen
4c82a9e7d0 Detect and handle COPY in many places.
This code is transitional, it will soon be possible to eliminate
isExtractSubreg, isInsertSubreg, and isMoveInstr in most places.

llvm-svn: 107547
2010-07-03 00:04:37 +00:00
Evan Cheng
a03e6f85fe Re-apply 105308 with fix.
llvm-svn: 105502
2010-06-04 23:28:13 +00:00
Bob Wilson
30093b5d8b Revert 105308.
llvm-svn: 105399
2010-06-03 18:28:31 +00:00
Evan Cheng
a2da22734f Enable machine cse of instructions which define physical registers.
llvm-svn: 105308
2010-06-02 01:08:27 +00:00
Eric Christopher
53ff992dde Make this LookAheadLimit, not the uninitialized LookAheadLeft.
Evan please verify!

llvm-svn: 104408
2010-05-21 23:40:03 +00:00
Evan Cheng
2c8bdead9e Allow machine cse to cse instructions which define physical registers. Controlled by option -machine-cse-phys-defs.
llvm-svn: 104385
2010-05-21 21:22:19 +00:00
Dan Gohman
7767d2747b Add a utility function for conservatively clearing kill flags, and make
use of it in MachineCSE.

llvm-svn: 103726
2010-05-13 19:24:00 +00:00
Evan Cheng
4b2ef56ad2 Rewrite machine cse to avoid recursion.
llvm-svn: 101964
2010-04-21 00:21:07 +00:00
Evan Cheng
4019d571d9 Typo.
llvm-svn: 101914
2010-04-20 17:27:38 +00:00