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Mono Color

• 26bc587b01
  Alpha Fixups (#77) auto-sync auto-sync-18 Rot127 2025-03-29 11:50:05 +00:00
• a5c8bdfe84
  Mark hvc, smc and svc as call. (#76) Rot127 2025-03-25 15:41:18 +00:00
• 93d64ce9ba
  Fix wrong version requirement of tricore instructions: (#75) Changqing Jing 2025-02-06 17:44:28 +08:00
• 159c98411e
  Add tricore tc1.8 instructions (#73) Changqing Jing 2025-01-14 23:14:29 +08:00
• ee9eebb40a Add Mips, SystemZ, Xtensa Rot127 2025-01-13 10:34:47 -05:00
• b6b6e8825c Add TriCore to CI Rot127 2025-01-13 10:31:08 -05:00
• 5cd3fa147a Add ARC patterns R33v0LT 2025-01-05 14:34:24 +03:00
• d4b34a1dae Set GPR32Reduced OperandType #71 R33v0LT 2024-12-06 20:35:38 +03:00
• 2e8642c70d Add ARC to Capstone Printer R33v0LT 2024-12-05 19:48:43 +03:00
• f6a22fb898 Tread crbitm as register Rot127 2024-12-06 14:28:36 -05:00
• 9f87617a17 Fix LI/LIS are no real instructions. Rot127 2024-12-06 14:28:25 -05:00
• 1002f679be Fix priv store/load: Make register pointer like regs Rot127 2024-12-06 13:02:38 -05:00
• b709f9c82c Fix endless loop if ReplaceDot = False Rot127 2024-12-06 12:45:08 -05:00
• 52da756484 Clean up normalizeMnemonic a little and allow to pass on removal patterns. Rot127 2024-11-25 13:25:27 -05:00
• e6420b28d3 Set correct printer for PS memory operands Rot127 2024-11-18 13:41:19 -05:00
• 7c6840d171 Fix QPX instructions. Rot127 2024-11-18 12:41:07 -05:00
• e57d7e2b55 Don't replace dot in alias mnemonic map Rot127 2024-11-18 07:48:58 -05:00
• a3cc36f886 Remove branching instructions which are actually alias. Rot127 2024-11-09 11:26:55 -05:00
• 0162e01063 Move store to correct block so meta info is set correclty. Rot127 2024-11-09 08:07:42 -05:00
• c4f934f472 Add memory access infor to ARM Rot127 2024-11-07 12:28:53 -05:00
• c06b997485 Revert for Capstone: We want to know that the instruction is v8. Because this is how it is defined in the ISA. Rot127 2024-11-07 11:53:38 -05:00
• 92c98d24a3 Fix printer functions which get Address as argument Rot127 2024-11-01 09:55:01 -05:00
• 290cd0784e Fix Xtensa reachable assert. Rot127 2024-10-05 05:01:04 -05:00
• 396ba323c8 Xtensa: Add GenCSInsnFormatsEnum.inc support billow 2024-11-05 03:30:53 +08:00
• 7f069f5af9 Add getArchSupplInfoXtensa billow 2024-11-05 03:20:45 +08:00
• 8b806d4f41 fix: - in Operand Group Name billow 2024-11-04 03:25:12 +08:00
• 8bdb4963c2 fix printInsnAliasEnum billow 2024-11-04 00:52:54 +08:00
• 48774db25f tricore: fixes all billow 2024-10-24 02:59:23 +08:00
• a1d54201a3 tricore: try fixes billow 2024-10-23 23:29:38 +08:00
• 717740dd49 fix: tricore billow 2024-10-22 15:22:37 +08:00
• 4b2ed3ee95 fix: tricore billow 2024-10-18 17:53:17 +08:00
• 6d32f27923 Add TriCore td files billow 2024-09-21 23:32:07 +08:00
• c0bc1e2f34 Add InsnBytesAsUint24 and add Xtensa to InsnBytesAsUint24 billow 2024-09-27 08:41:20 +08:00
• 2361b73798 Replace hard asserts with assert macros with different behavior. Rot127 2024-09-11 04:58:21 -05:00
• 600a1b3d97 Fix: Src operand is not the out operand Rot127 2024-09-07 09:46:42 -05:00
• 139e42930c Revert "Add curly brackets to normalize mnemonic." Rot127 2024-09-07 06:24:58 -05:00
• 26a30270a6 Remove incorrect SP reads. Rot127 2024-09-07 05:55:57 -05:00
• 6c5a12b5eb Update LLVM release/18.x release/18.x github-actions[bot] 2024-09-16 00:59:21 +00:00
• 1cc0208738 Add instruction formats for SystemZ Rot127 2024-08-30 05:24:46 -05:00
• ac6fd33f56 Add curly brackets to normalize mnemonic. Rot127 2024-08-28 05:08:02 -05:00
• 12424fa530 Fix incorrect parameter Rot127 2024-08-28 02:22:33 -05:00
• 830c7a8e6f Replace | char of SystemZ insn enums Rot127 2024-08-26 05:12:09 -05:00
• ca07088b26 Add SystemZ decoder macro. Rot127 2024-08-26 04:51:09 -05:00
• 1496434327
  Mips + microMips + nanoMips (#56) Giovanni 2024-09-01 00:57:34 +08:00
• 029bac0e9b Allow to patch multiple default template arguments for Mips. Rot127 2024-08-25 03:22:40 -05:00
• 6464d962f4 Handle MIPS SIMM9 operand Rot127 2024-07-28 02:22:32 -05:00
• 584efadbc4 Panic if no decoder was initialized. Rot127 2024-07-28 02:21:37 -05:00
• 90b6007454 Clear MCInst when the decode fails, to reset operand counter. Rot127 2024-07-20 05:49:32 -05:00
• dddf0d1faa Simplify name comparison Rot127 2024-07-01 00:41:07 -05:00
• 933e2a85cf OP_GROUP enums can't be all upper case currently Rot127 2024-06-29 00:28:38 -05:00
• 5f266ccfb9 Fix template patching for AArch64 Rot127 2024-06-26 23:43:05 -05:00
• a795ea9719 Emit CS enum values in all capital letters Rot127 2024-06-19 04:53:29 -05:00
• 5943ec6923 Add Alpha and LoongArch to the CI tests. Rot127 2024-06-04 03:29:20 -05:00
• 3c619b615d Tblgen capstone backends - add Alpha architecture (#17) R3v0LT 2023-08-23 06:02:14 +03:00
• c302509824 Remove incorrect NZCV write. Rot127 2024-05-28 02:38:50 -05:00
• 16baaaf307 Rename CS_AC_READ_WRTE to CS_AC_READ_WRITE Jiajie Chen 2024-05-19 10:51:02 +08:00
• 5c6d1fa0c9 Emit formats enum and supplemental info for LoongArch Jiajie Chen 2024-05-04 21:01:29 +08:00
• d93bd71b15 Set OperandType to OPERAND_IMMEDIATE for immediate operands Jiajie Chen 2024-05-03 21:10:21 +08:00
• 4d5ca55385 Handle INVALID_SIMPLE_VALUE_TYPE in getEnumName Jiajie Chen 2024-05-03 19:17:19 +08:00
• 1a7acd3aee Assign OPERAND_IMMEDIATE as OperandType of BareSymbol Rot127 2024-05-03 19:13:41 +08:00
• bece35d7fa Avoid using llvm_unreachable Jiajie Chen 2024-05-03 17:46:00 +08:00
• af1ff9c099 Change RegDiffLists type to MCPhysReg Jiajie Chen 2024-05-03 17:45:00 +08:00
• 91da70b398 Handle multiple template arguments in handleDefaultArg Jiajie Chen 2024-05-03 17:38:58 +08:00
• 1ac920cc21 Add LoongArch support Jiajie Chen 2024-01-23 17:03:20 +08:00
• 1f5a51cec8 Generate BOUND flags for SME operands. Rot127 2024-05-21 01:50:51 -05:00
• 118ad37dd0 Fix regex pattern to not match operand names between ] and [ Rot127 2024-05-16 01:44:57 -05:00
• 1312d742a5 Add memory access info as supplementary AArch64 info Rot127 2024-05-15 08:39:23 -05:00
• f5c4f04bd6 Check in patterns for memory operand properties. Rot127 2024-05-15 06:09:50 -05:00
• 162c1c0002 Initialize DecoderComplete flag in generated decoder function. Rot127 2024-05-15 03:03:03 -05:00
• b025bae5cf Assign enum value to the raw_val member to prevent compiler warnings. Rot127 2024-04-30 05:18:19 -05:00
• d386558ab6 Remove check for same name, different signature functions. Rot127 2024-04-30 04:41:21 -05:00
• a35941283f Add AdrLabel and AdrpLable to OP_GROUPS Rot127 2024-04-25 03:06:24 -05:00
• 2be2c0fed8 Add MatrixIndex_... to the OP_GROUP list Rot127 2024-04-25 02:51:16 -05:00
• 04b82d5399 Fix template function translation Rot127 2024-04-25 02:47:27 -05:00
• 86c1c566e6 Fix: Don't return NULL for a struct Rot127 2024-04-25 00:06:01 -05:00
• 1318024d0c Format code Rot127 2024-04-25 00:01:50 -05:00
• 2e51e2eded Generate InstDecs tables with references to the OpInfo structs. Rot127 2024-04-25 00:01:38 -05:00
• f3c60336ba Add default argument for printSVERegOp Rot127 2024-04-25 00:00:03 -05:00
• a7d6b2f4e1 Define the InstrTable as own type Rot127 2024-04-24 22:12:56 -05:00
• 1d9e607d63 Remove asserts Rot127 2024-04-24 22:05:46 -05:00
• 9cbe1f3883 Add missing include guard to ignore list. Rot127 2024-04-24 21:42:52 -05:00
• 9b0af77cd4 Extends docs Rot127 2024-04-24 21:39:34 -05:00
• 1beb1667d4 Enable EmitMapTable to print C tables. Rot127 2024-04-23 22:42:12 -05:00
• 100ca315f2 Remove instruction encoding information. Rot127 2024-04-23 22:13:16 -05:00
• d77b8e1e18 Fix no-return values warning from compiler. Rot127 2024-04-10 03:21:41 -05:00
• 77cde4e9bb Fix mismatch in generated C++ SystemOperands files. Rot127 2024-03-20 07:35:54 -05:00
• 3d027d2146 Fix mismatch in C++ Subtarget files Rot127 2024-03-20 07:29:57 -05:00
• b9cb107187 Fix mismatches in generated C++ code. Rot127 2024-03-20 07:19:30 -05:00
• 31564d0004 Remove syntax check, because it doesn't work that easy. Rot127 2024-03-20 05:09:22 -05:00
• 38c9f1312a Make gen scripts use the repository root dir. Rot127 2024-03-20 02:43:07 -05:00
• 1a0c3b2478 Fix some incorrectly generated source code after rebase. Rot127 2024-03-20 02:42:25 -05:00
• 01fe52b2cc Fix workflows Rot127 2024-03-19 04:49:45 -05:00
• 4d0bf508b2 Separate generating of tables into different scripts so we can use Github action for branch checkout. Rot127 2024-03-19 04:20:12 -05:00
• 4392b8b518 Add build instructions Rot127 2024-03-19 03:28:34 -05:00
• 7416021692 Build debug llvm-tblgen in CI Rot127 2024-03-19 03:22:07 -05:00
• 147ee550e6 Fix some incorrect generated LLVM code. Rot127 2024-03-19 03:03:16 -05:00
• e1baf17a75 Use Python provided cmake and Ninja for CI build and select gnu compiler 12 Rot127 2024-03-19 02:36:58 -05:00
• 994c2a0930 Don't dump output of build in /dev/null Rot127 2024-03-12 02:40:44 -05:00
• d8f1e22274 Fix incorrect use of variable. Rot127 2024-03-12 02:35:10 -05:00
• b0ada691e5 Blind fix for Github CI build Rot127 2024-03-12 02:19:43 -05:00