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• 0d106785f5
  Merge d23037a363 into e6420b28d3 #68 Rot127 2024-11-25 18:26:10 +0000
• d23037a363
  Clean up normalizeMnemonic a little and allow to pass on removal patterns. #68 Rot127 2024-11-25 13:25:27 -0500
• e6420b28d3 Set correct printer for PS memory operands auto-sync auto-sync-18 Rot127 2024-11-18 13:41:19 -0500
• 7c6840d171 Fix QPX instructions. Rot127 2024-11-18 12:41:07 -0500
• e57d7e2b55 Don't replace dot in alias mnemonic map Rot127 2024-11-18 07:48:58 -0500
• a3cc36f886 Remove branching instructions which are actually alias. Rot127 2024-11-09 11:26:55 -0500
• 7d8c11422c
  Set correct printer for PS memory operands #67 Rot127 2024-11-18 13:41:19 -0500
• 0d07b818a3
  Fix QPX instructions. Rot127 2024-11-18 12:41:07 -0500
• 28a66ccc71
  Don't replace dot in alias mnemonic map Rot127 2024-11-18 07:48:58 -0500
• c4efb40ade
  Remove branching instructions which are actually alias. Rot127 2024-11-09 11:26:55 -0500
• 0162e01063 Move store to correct block so meta info is set correclty. Rot127 2024-11-09 08:07:42 -0500
• c4f934f472 Add memory access infor to ARM Rot127 2024-11-07 12:28:53 -0500
• c06b997485 Revert for Capstone: We want to know that the instruction is v8. Because this is how it is defined in the ISA. Rot127 2024-11-07 11:53:38 -0500
• 982f907c92
  Move store to correct block so meta info is set correclty. #66 Rot127 2024-11-09 08:07:42 -0500
• 5aa724ddb6
  Add memory access infor to ARM Rot127 2024-11-07 12:28:53 -0500
• 426db95f42
  Revert for Capstone: We want to know that the instruction is v8. Because this is how it is defined in the ISA. Rot127 2024-11-07 11:53:38 -0500
• 92c98d24a3 Fix printer functions which get Address as argument Rot127 2024-11-01 09:55:01 -0500
• 290cd0784e Fix Xtensa reachable assert. Rot127 2024-10-05 05:01:04 -0500
• 396ba323c8 Xtensa: Add GenCSInsnFormatsEnum.inc support billow 2024-11-05 03:30:53 +0800
• 7f069f5af9 Add getArchSupplInfoXtensa billow 2024-11-05 03:20:45 +0800
• 8b806d4f41 fix: - in Operand Group Name billow 2024-11-04 03:25:12 +0800
• 8bdb4963c2 fix printInsnAliasEnum billow 2024-11-04 00:52:54 +0800
• d7047deb02 Xtensa: Add GenCSInsnFormatsEnum.inc support #65 billow 2024-11-05 03:30:53 +0800
• 69e3d20abd Add getArchSupplInfoXtensa billow 2024-11-05 03:20:45 +0800
• 34ba748432 fix: - in Operand Group Name billow 2024-11-04 03:25:12 +0800
• 44ecb08638 fix printInsnAliasEnum billow 2024-11-04 00:52:54 +0800
• 5b4b1194f1
  Fix printer functions which get Address as argument #64 Rot127 2024-11-01 09:55:01 -0500
• 48774db25f tricore: fixes all billow 2024-10-24 02:59:23 +0800
• a1d54201a3 tricore: try fixes billow 2024-10-23 23:29:38 +0800
• 717740dd49 fix: tricore billow 2024-10-22 15:22:37 +0800
• 4b2ed3ee95 fix: tricore billow 2024-10-18 17:53:17 +0800
• 987e17b748 tricore: fixes all #63 billow 2024-10-24 02:59:23 +0800
• 4435aa018b tricore: try fixes billow 2024-10-23 23:29:38 +0800
• 7bfe0f6409 fix: tricore billow 2024-10-22 15:22:37 +0800
• 834eb9b0ea fix: tricore billow 2024-10-18 17:53:17 +0800
• 6d32f27923 Add TriCore td files billow 2024-09-21 23:32:07 +0800
• 56ed8a2877
  Fix Xtensa reachable assert. #62 Rot127 2024-10-05 05:01:04 -0500
• c0bc1e2f34 Add InsnBytesAsUint24 and add Xtensa to InsnBytesAsUint24 billow 2024-09-27 08:41:20 +0800
• 076ca30de4 Add InsnBytesAsUint24 and add Xtensa to InsnBytesAsUint24 #61 billow 2024-09-27 08:41:20 +0800
• 22cfa1a4b5 Add TriCore td files #60 billow 2024-09-21 23:32:07 +0800
• 2361b73798 Replace hard asserts with assert macros with different behavior. Rot127 2024-09-11 04:58:21 -0500
• 600a1b3d97 Fix: Src operand is not the out operand Rot127 2024-09-07 09:46:42 -0500
• 139e42930c Revert "Add curly brackets to normalize mnemonic." Rot127 2024-09-07 06:24:58 -0500
• 26a30270a6 Remove incorrect SP reads. Rot127 2024-09-07 05:55:57 -0500
• 6c5a12b5eb Update LLVM release/18.x release/18.x github-actions[bot] 2024-09-16 00:59:21 +0000
• cd0ed90237
  Replace hard asserts with assert macros with different behavior. #58 Rot127 2024-09-11 04:58:21 -0500
• 73a647af93
  Fix: Src operand is not the out operand #57 Rot127 2024-09-07 09:46:42 -0500
• 65a9134221
  Revert "Add curly brackets to normalize mnemonic." Rot127 2024-09-07 06:24:58 -0500
• 720c99d476
  Remove incorrect SP reads. Rot127 2024-09-07 05:55:57 -0500
• 1cc0208738 Add instruction formats for SystemZ Rot127 2024-08-30 05:24:46 -0500
• ac6fd33f56 Add curly brackets to normalize mnemonic. Rot127 2024-08-28 05:08:02 -0500
• 12424fa530 Fix incorrect parameter Rot127 2024-08-28 02:22:33 -0500
• 830c7a8e6f Replace | char of SystemZ insn enums Rot127 2024-08-26 05:12:09 -0500
• ca07088b26 Add SystemZ decoder macro. Rot127 2024-08-26 04:51:09 -0500
• 1496434327
  Mips + microMips + nanoMips (#56) Giovanni 2024-09-01 00:57:34 +0800
• 082c88c48b Add nanomips tests #56 wargio 2024-09-01 00:56:34 +0800
• 08e30b458b
  Add instruction formats for SystemZ #55 Rot127 2024-08-30 05:24:46 -0500
• 5d909efd48 Mips + microMips + nanoMips wargio 2024-07-28 15:37:09 +0800
• f611643186
  Add curly brackets to normalize mnemonic. Rot127 2024-08-28 05:08:02 -0500
• 029bac0e9b Allow to patch multiple default template arguments for Mips. Rot127 2024-08-25 03:22:40 -0500
• b25fd030d0
  Fix incorrect parameter Rot127 2024-08-28 02:22:33 -0500
• 5c1684d042
  Replace | char of SystemZ insn enums Rot127 2024-08-26 05:12:09 -0500
• 174e970f5d
  Add SystemZ decoder macro. Rot127 2024-08-26 04:51:09 -0500
• 5b5c4e577f
  Allow to patch multiple default template arguments for Mips. #54 Rot127 2024-08-25 03:22:40 -0500
• 6464d962f4 Handle MIPS SIMM9 operand Rot127 2024-07-28 02:22:32 -0500
• 584efadbc4 Panic if no decoder was initialized. Rot127 2024-07-28 02:21:37 -0500
• 90b6007454 Clear MCInst when the decode fails, to reset operand counter. Rot127 2024-07-20 05:49:32 -0500
• 747c9627a5
  Handle MIPS SIMM9 operand #52 Rot127 2024-07-28 02:22:32 -0500
• bbe3c6f723
  Panic if no decoder was initialized. Rot127 2024-07-28 02:21:37 -0500
• 3219b645fa [mips] Add OPERAND_MEM_SIMM9 #53 wargio 2024-07-28 14:12:25 +0800
• ee37023fbc
  Clear MCInst when the decode fails, to reset operand counter. Rot127 2024-07-20 05:49:32 -0500
• dddf0d1faa Simplify name comparison Rot127 2024-07-01 00:41:07 -0500
• 933e2a85cf OP_GROUP enums can't be all upper case currently Rot127 2024-06-29 00:28:38 -0500
• 5f266ccfb9 Fix template patching for AArch64 Rot127 2024-06-26 23:43:05 -0500
• 1580de1117
  Simplify name comparison #51 Rot127 2024-07-01 00:41:07 -0500
• 751b161766
  OP_GROUP enums can't be all upper case currently Rot127 2024-06-29 00:28:38 -0500
• 1db56321fd
  Fix template patching for AArch64 Rot127 2024-06-26 23:43:05 -0500
• a795ea9719 Emit CS enum values in all capital letters Rot127 2024-06-19 04:53:29 -0500
• 975d5361f4
  Emit CS enum values in all capital letters #50 Rot127 2024-06-19 04:53:29 -0500
• 5943ec6923 Add Alpha and LoongArch to the CI tests. Rot127 2024-06-04 03:29:20 -0500
• 3c619b615d Tblgen capstone backends - add Alpha architecture (#17) R3v0LT 2023-08-23 06:02:14 +0300
• 6d2ec85d87
  Add Alpha and LoongArch to the CI tests. #49 Rot127 2024-06-04 03:29:20 -0500
• 5ba55958f5
  Tblgen capstone backends - add Alpha architecture (#17) R3v0LT 2023-08-23 06:02:14 +0300
• c302509824 Remove incorrect NZCV write. Rot127 2024-05-28 02:38:50 -0500
• cfd716f06f
  Remove incorrect NZCV write. #48 Rot127 2024-05-28 02:38:50 -0500
• 16baaaf307 Rename CS_AC_READ_WRTE to CS_AC_READ_WRITE Jiajie Chen 2024-05-19 10:51:02 +0800
• 5c6d1fa0c9 Emit formats enum and supplemental info for LoongArch Jiajie Chen 2024-05-04 21:01:29 +0800
• d93bd71b15 Set OperandType to OPERAND_IMMEDIATE for immediate operands Jiajie Chen 2024-05-03 21:10:21 +0800
• 4d5ca55385 Handle INVALID_SIMPLE_VALUE_TYPE in getEnumName Jiajie Chen 2024-05-03 19:17:19 +0800
• 1a7acd3aee Assign OPERAND_IMMEDIATE as OperandType of BareSymbol Rot127 2024-05-03 19:13:41 +0800
• bece35d7fa Avoid using llvm_unreachable Jiajie Chen 2024-05-03 17:46:00 +0800
• af1ff9c099 Change RegDiffLists type to MCPhysReg Jiajie Chen 2024-05-03 17:45:00 +0800
• 91da70b398 Handle multiple template arguments in handleDefaultArg Jiajie Chen 2024-05-03 17:38:58 +0800
• 1ac920cc21 Add LoongArch support Jiajie Chen 2024-01-23 17:03:20 +0800
• 1f5a51cec8 Generate BOUND flags for SME operands. Rot127 2024-05-21 01:50:51 -0500
• 118ad37dd0 Fix regex pattern to not match operand names between ] and [ Rot127 2024-05-16 01:44:57 -0500
• 1312d742a5 Add memory access info as supplementary AArch64 info Rot127 2024-05-15 08:39:23 -0500
• f5c4f04bd6 Check in patterns for memory operand properties. Rot127 2024-05-15 06:09:50 -0500
• 162c1c0002 Initialize DecoderComplete flag in generated decoder function. Rot127 2024-05-15 03:03:03 -0500
• b025bae5cf Assign enum value to the raw_val member to prevent compiler warnings. Rot127 2024-04-30 05:18:19 -0500